From: Daniel Ng <daniel.ng1234@gmail.com>
To: Scott Wood <scottwood@freescale.com>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: Device Tree setup for 8272-based board
Date: Thu, 22 Jan 2009 18:47:01 +1100 [thread overview]
Message-ID: <547eba1b0901212347v47c9ee4at40e2188c50351952@mail.gmail.com> (raw)
In-Reply-To: <20090121175225.GB31266@ld0162-tx32.am.freescale.net>
On Thu, Jan 22, 2009 at 4:52 AM, Scott Wood <scottwood@freescale.com> wrote:
>> 3) In the PIC: interrupt-controller@10c00 node-
>> reg = <0x10c00 0x80>;
>
> Offset and length of PIC registers.
Thanks Scott. What is the meaning of the Ethernet reg field?:
reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
Is it-
0x11300-> GFMR1 ie. the GFMR for FCC1?
0x20-> GFMR1 Fields are a total of 32 bits?
0x8400-> initial value of bits 0-15 of GFMR1?
0x100-> initial value of bits 16-31 of GFMR1?
0x11390-> GFEMR1?
0x1-> length of GFEMR1 is 1 bit in size?? (this doesn't make sense
because it's a 3-bit field)
Where would we specify the initial value of GFEMR1?
Cheers,
Daniel
next prev parent reply other threads:[~2009-01-22 7:47 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-01-16 1:22 Device Tree setup for 8272-based board Daniel Ng
2009-01-16 3:40 ` Daniel Ng
2009-01-16 18:14 ` Scott Wood
2009-01-19 1:58 ` Daniel Ng
2009-01-19 17:29 ` Scott Wood
2009-01-20 7:23 ` Daniel Ng
2009-01-20 16:41 ` Scott Wood
2009-01-21 7:37 ` Daniel Ng
2009-01-21 17:52 ` Scott Wood
2009-01-22 7:47 ` Daniel Ng [this message]
2009-01-22 17:05 ` Scott Wood
-- strict thread matches above, loose matches on Subject: below --
2008-12-19 6:31 Daniel Ng
2008-12-19 16:37 ` mingqian
2008-12-19 20:03 ` Scott Wood
2008-12-22 6:57 ` Daniel Ng
2008-12-22 17:37 ` Scott Wood
2008-12-23 0:52 ` Daniel Ng
2008-12-23 16:09 ` Scott Wood
2008-12-23 23:21 ` Daniel Ng
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