[PATCH v1 0/3] SHA256 for PPC/SPE

[PATCH v1 0/3] SHA256 for PPC/SPE

[Markus Stockhausen]

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[PATCH v1 0/3] SHA256 for PPC/SPE

The following patches add support for SIMD accelerated SHA256 
calculation on PPC processors with SPE instruction set. The 
implementation takes care of the following constraints:

- independant of processor endianess
- fallback to generic code if called from interrupt context
- disable preemtion only for short intervals

Performance numbers from insmod tcrypt sec=3 mode=304 taken
on e500v2 800 MHz (TP Link WDR4900)

data    per      generic     this patch  speedup  cycles
length  update   bytes/sec   bytes/sec   factor   per byte
------  -------  ----------  ----------  -------  --------
    16       16   5,558,336   8,248,272	  x1.48      96.99
    64       16  10,730,602  14,872,789   x1.38      53.79
    64       64  12,841,621  19,268,885   x1.50      41.52
   256       16  16,223,317  21,295,957   x1.31      37.57
   256       64  21,135,957  30,941,696   x1.46      25,86
   256      256	 22,664,448  35,765,845   x1.57      22,37
  1024       16  18,608,128  23,893,674   x1.28      33.48
  1024      256  27,427,840  43,427,498   x1.58      18.42
  1024     1024  28,064,768  45,659,136   x1.62      17.52
  2048       16  19,054,592  24,425,130   x1.28      32.75
  2048      256  28,435,797  45,087,402   x1.58      17.74
  2048     1024  29,091,157  47,395,498   x1.62      16.88
  2048     2048  29,225,642  47,756,629   x1.63      16.75

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Re: [PATCH v1 0/3] SHA256 for PPC/SPE

[Herbert Xu]

Markus Stockhausen <stockhausen@collogia.de> wrote:
> 
> [PATCH v1 0/3] SHA256 for PPC/SPE
> 
> The following patches add support for SIMD accelerated SHA256 
> calculation on PPC processors with SPE instruction set. The 
> implementation takes care of the following constraints:
> 
> - independant of processor endianess
> - fallback to generic code if called from interrupt context
> - disable preemtion only for short intervals

Thanks for the patch! Unfortunately the interrupt context test
is a bummer because that means your code won't be used by IPsec
at all.

Would it be possible to relax the conditions similar to sha1_ssse3
on x86? If not how about going async with cryptd?

Cheers,
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Re: [PATCH v1 0/3] SHA256 for PPC/SPE

[Markus Stockhausen]

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> Von: linux-crypto-owner@vger.kernel.org [linux-crypto-owner@vger.kernel.org]" im Auftrag von "Herbert Xu [herbert@gondor.apana.org.au]
> Gesendet: Montag, 26. Januar 2015 01:18
> An: Markus Stockhausen
> Cc: linux-crypto@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
> Betreff: Re: [PATCH v1 0/3] SHA256 for PPC/SPE
> 
> Markus Stockhausen <stockhausen@collogia.de> wrote:
> >
> >  [PATCH v1 0/3] SHA256 for PPC/SPE
> >
> > The following patches add support for SIMD accelerated SHA256
> > calculation on PPC processors with SPE instruction set. The
> > implementation takes care of the following constraints:
> >
> > - independant of processor endianess
> > - fallback to generic code if called from interrupt context
> > - disable preemtion only for short intervals
> 
> Thanks for the patch! Unfortunately the interrupt context test
> is a bummer because that means your code won't be used by IPsec
> at all.
> 
> Would it be possible to relax the conditions similar to sha1_ssse3
> on x86? If not how about going async with cryptd?

@Herbert: thanks for that annotation. IPsec is the desired use case.
Do you have a programming template for the cryptd integration?
E.g. ghash-clmulni-intel_glue.c?

@linuxppc: Intel world checks for usable FPU (SSE3, ...) in the crypto 
modules with

bool irq_fpu_usable(void)
{
  return !in_interrupt() ||
    interrupted_user_mode() ||
    interrupted_kernel_fpu_idle();
}

I guess interrupted_kernel_fpu_idle() is the part that allows IPsec 
inside an interrupt to make use of the accelerated module. 
Explanation reads:

* On others, we can do a kernel_fpu_begin/end() pair *ONLY* if 
* that pair does nothing at all: the thread must not have fpu (so
* that we don't try to save the FPU state), and TS must
* be set (so that the clts/stts pair does nothing that is
* visible in the interrupted kernel thread).

Do I have the chance to use something similiar in the PPC/SPE 
case? Or is there a simple way like saving the SPE registers
myself?

Thanks in advance.

Markus=

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Re: [PATCH v1 0/3] SHA256 for PPC/SPE

[Conor O'Gorman]

On 24/01/15 21:10, Markus Stockhausen wrote:
> [PATCH v1 0/3] SHA256 for PPC/SPE
>
> The following patches add support for SIMD accelerated SHA256
> calculation on PPC processors with SPE instruction set. The

Nice boost.

Many of the SoCs with e500 core have crypto hardware accelerators. How 
does this compare?

Thanks,
Conor

AW: [PATCH v1 0/3] SHA256 for PPC/SPE

[Markus Stockhausen]

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> Von: Conor O'Gorman [i@conorogorman.net]
> Gesendet: Freitag, 30. Januar 2015 13:02
> An: Markus Stockhausen; linux-crypto@vger.kernel.org
> Cc: linuxppc-dev@lists.ozlabs.org
> Betreff: Re: [PATCH v1 0/3] SHA256 for PPC/SPE
> 
> On 24/01/15 21:10, Markus Stockhausen wrote:
> > [PATCH v1 0/3] SHA256 for PPC/SPE
> >
> > The following patches add support for SIMD accelerated SHA256
> > calculation on PPC processors with SPE instruction set. The
> 
> Nice boost.
> 
> Many of the SoCs with e500 core have crypto hardware accelerators. How
> does this compare?

May sound stupid but I failed to activate the device in my TP-Link WDR4900.
The whole story here: https://community.freescale.com/message/475816

Markus
=

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