* [PATCH 1/7] soc/fman: Add the FMan FLIB headers
2015-03-05 5:45 [PATCH 0/7] Freescale DPAA FMan FLIB(s) Emil Medve
@ 2015-03-05 5:45 ` Emil Medve
2015-03-06 16:32 ` Kumar Gala
2015-03-05 5:45 ` [PATCH 2/7] soc/fman: Add the FMan FLIB Emil Medve
` (6 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Emil Medve @ 2015-03-05 5:45 UTC (permalink / raw)
To: linuxppc-dev, netdev, linux-kernel; +Cc: Igal Liberman
From: Igal Liberman <Igal.Liberman@freescale.com>
The Freescale Data Path Acceleration Architecture (DPAA) is a set of
hardware components on specific QorIQ P and T series multicore processors.
This architecture provides the infrastructure to support simplified
sharing of networking interfaces and accelerators by multiple CPU cores,
and the accelerators themselves.
One of the DPAA accelerators is the Frame Manager (FMan), which
combines the Ethernet network interfaces with packet distribution
logic to provide intelligent distribution and queuing decisions for
incoming traffic at line rate.
This patch presents the FMan Foundation Libraries (FLIB) headers.
The FMan FLIB suite adds basic support for the DPAA FMan hardware register access.
The FMan FLIB suite is used in Freescale's SDK Releases.
Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
---
drivers/soc/fsl/fman/flib/common/general.h | 45 +
drivers/soc/fsl/fman/flib/fman_common.h | 74 ++
drivers/soc/fsl/fman/flib/fsl_enet.h | 276 ++++++
drivers/soc/fsl/fman/flib/fsl_fman.h | 801 +++++++++++++++
drivers/soc/fsl/fman/flib/fsl_fman_dtsec.h | 1017 ++++++++++++++++++++
drivers/soc/fsl/fman/flib/fsl_fman_dtsec_mii_acc.h | 104 ++
drivers/soc/fsl/fman/flib/fsl_fman_kg.h | 506 ++++++++++
drivers/soc/fsl/fman/flib/fsl_fman_memac.h | 492 ++++++++++
drivers/soc/fsl/fman/flib/fsl_fman_memac_mii_acc.h | 77 ++
drivers/soc/fsl/fman/flib/fsl_fman_port.h | 602 ++++++++++++
drivers/soc/fsl/fman/flib/fsl_fman_prs.h | 106 ++
drivers/soc/fsl/fman/flib/fsl_fman_rtc.h | 415 ++++++++
drivers/soc/fsl/fman/flib/fsl_fman_sp.h | 133 +++
drivers/soc/fsl/fman/flib/fsl_fman_tgec.h | 484 ++++++++++
14 files changed, 5132 insertions(+)
create mode 100644 drivers/soc/fsl/fman/flib/common/general.h
create mode 100644 drivers/soc/fsl/fman/flib/fman_common.h
create mode 100644 drivers/soc/fsl/fman/flib/fsl_enet.h
create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman.h
create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_dtsec.h
create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_dtsec_mii_acc.h
create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_kg.h
create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_memac.h
create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_memac_mii_acc.h
create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_port.h
create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_prs.h
create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_rtc.h
create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_sp.h
create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_tgec.h
diff --git a/drivers/soc/fsl/fman/flib/common/general.h b/drivers/soc/fsl/fman/flib/common/general.h
new file mode 100644
index 0000000..e5f56af
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/common/general.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __GENERAL_H
+#define __GENERAL_H
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+#define UNUSED(X) (X = X)
+#define KILOBYTE 0x400UL /* 1024 */
+
+#define iowrite32be(val, addr) out_be32(&(*addr), val)
+#define ioread32be(addr) in_be32(&(*addr))
+
+#endif /* __GENERAL_H */
diff --git a/drivers/soc/fsl/fman/flib/fman_common.h b/drivers/soc/fsl/fman/flib/fman_common.h
new file mode 100644
index 0000000..60f2bc4
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fman_common.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FMAN_COMMON_H
+#define __FMAN_COMMON_H
+
+/* NIA Description */
+#define NIA_ORDER_RESTOR 0x00800000
+#define NIA_ENG_FM_CTL 0x00000000
+#define NIA_ENG_PRS 0x00440000
+#define NIA_ENG_KG 0x00480000
+#define NIA_ENG_PLCR 0x004C0000
+#define NIA_ENG_BMI 0x00500000
+#define NIA_ENG_QMI_ENQ 0x00540000
+#define NIA_ENG_QMI_DEQ 0x00580000
+#define NIA_ENG_MASK 0x007C0000
+
+#define NIA_FM_CTL_AC_CC 0x00000006
+#define NIA_FM_CTL_AC_HC 0x0000000C
+#define NIA_FM_CTL_AC_IND_MODE_TX 0x00000008
+#define NIA_FM_CTL_AC_IND_MODE_RX 0x0000000A
+#define NIA_FM_CTL_AC_FRAG 0x0000000e
+#define NIA_FM_CTL_AC_PRE_FETCH 0x00000010
+#define NIA_FM_CTL_AC_POST_FETCH_PCD 0x00000012
+#define NIA_FM_CTL_AC_POST_FETCH_PCD_UDP_LEN 0x00000018
+#define NIA_FM_CTL_AC_POST_FETCH_NO_PCD 0x00000012
+#define NIA_FM_CTL_AC_FRAG_CHECK 0x00000014
+#define NIA_FM_CTL_AC_PRE_CC 0x00000020
+
+#define NIA_BMI_AC_ENQ_FRAME 0x00000002
+#define NIA_BMI_AC_TX_RELEASE 0x000002C0
+#define NIA_BMI_AC_RELEASE 0x000000C0
+#define NIA_BMI_AC_DISCARD 0x000000C1
+#define NIA_BMI_AC_TX 0x00000274
+#define NIA_BMI_AC_FETCH 0x00000208
+#define NIA_BMI_AC_MASK 0x000003FF
+
+#define NIA_KG_DIRECT 0x00000100
+#define NIA_KG_CC_EN 0x00000200
+#define NIA_PLCR_ABSOLUTE 0x00008000
+
+#define NIA_BMI_AC_ENQ_FRAME_WITHOUT_DMA 0x00000202
+#define NIA_BMI_AC_FETCH_ALL_FRAME 0x0000020c
+
+#endif /* __FMAN_COMMON_H */
diff --git a/drivers/soc/fsl/fman/flib/fsl_enet.h b/drivers/soc/fsl/fman/flib/fsl_enet.h
new file mode 100644
index 0000000..cbfc91d
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fsl_enet.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_ENET_H
+#define __FSL_ENET_H
+
+/*Ethernet MAC-PHY Interface */
+
+enum enet_interface {
+ E_ENET_IF_MII = 0x00010000, /* MII interface */
+ E_ENET_IF_RMII = 0x00020000, /* RMII interface */
+ E_ENET_IF_SMII = 0x00030000, /* SMII interface */
+ E_ENET_IF_GMII = 0x00040000, /* GMII interface */
+ E_ENET_IF_RGMII = 0x00050000, /* RGMII interface */
+ E_ENET_IF_TBI = 0x00060000, /* TBI interface */
+ E_ENET_IF_RTBI = 0x00070000, /* RTBI interface */
+ E_ENET_IF_SGMII = 0x00080000, /* SGMII interface */
+ E_ENET_IF_XGMII = 0x00090000, /* XGMII interface */
+ E_ENET_IF_QSGMII = 0x000a0000, /* QSGMII interface */
+ E_ENET_IF_XFI = 0x000b0000 /* XFI interface */
+};
+
+/* Ethernet Speed (nominal data rate) */
+enum enet_speed {
+ E_ENET_SPEED_10 = 10, /* 10 Mbps */
+ E_ENET_SPEED_100 = 100, /* 100 Mbps */
+ E_ENET_SPEED_1000 = 1000, /* 1000 Mbps = 1 Gbps */
+ E_ENET_SPEED_10000 = 10000 /* 10000 Mbps = 10 Gbps */
+};
+
+enum mac_type {
+ E_MAC_DTSEC,
+ E_MAC_TGEC,
+ E_MAC_MEMAC
+};
+
+/* Enum for inter-module interrupts registration */
+enum fman_event_modules {
+ E_FMAN_MOD_PRS, /* Parser event */
+ E_FMAN_MOD_KG, /* Keygen event */
+ E_FMAN_MOD_PLCR, /* Policer event */
+ E_FMAN_MOD_10G_MAC, /* 10G MAC event */
+ E_FMAN_MOD_1G_MAC, /* 1G MAC event */
+ E_FMAN_MOD_TMR, /* Timer event */
+ E_FMAN_MOD_FMAN_CTRL, /* FMAN Controller Timer event */
+ E_FMAN_MOD_MACSEC,
+ E_FMAN_MOD_DUMMY_LAST
+};
+
+/* Enum for interrupts types */
+enum fman_intr_type {
+ E_FMAN_INTR_TYPE_ERR,
+ E_FMAN_INTR_TYPE_NORMAL
+};
+
+/* enum for defining MAC types */
+enum fman_mac_type {
+ E_FMAN_MAC_10G = 0, /* 10G MAC */
+ E_FMAN_MAC_1G /* 1G MAC */
+};
+
+enum fman_mac_exceptions {
+ E_FMAN_MAC_EX_10G_MDIO_SCAN_EVENTMDIO = 0,
+ /* 10GEC MDIO scan event interrupt */
+ E_FMAN_MAC_EX_10G_MDIO_CMD_CMPL,
+ /* 10GEC MDIO command completion interrupt */
+ E_FMAN_MAC_EX_10G_REM_FAULT,
+ /* 10GEC, mEMAC Remote fault interrupt */
+ E_FMAN_MAC_EX_10G_LOC_FAULT,
+ /* 10GEC, mEMAC Local fault interrupt */
+ E_FMAN_MAC_EX_10G_1TX_ECC_ER,
+ /* 10GEC, mEMAC Transmit frame ECC error interrupt */
+ E_FMAN_MAC_EX_10G_TX_FIFO_UNFL,
+ /* 10GEC, mEMAC Transmit FIFO underflow interrupt */
+ E_FMAN_MAC_EX_10G_TX_FIFO_OVFL,
+ /* 10GEC, mEMAC Transmit FIFO overflow interrupt */
+ E_FMAN_MAC_EX_10G_TX_ER,
+ /* 10GEC Transmit frame error interrupt */
+ E_FMAN_MAC_EX_10G_RX_FIFO_OVFL,
+ /* 10GEC, mEMAC Receive FIFO overflow interrupt */
+ E_FMAN_MAC_EX_10G_RX_ECC_ER,
+ /* 10GEC, mEMAC Receive frame ECC error interrupt */
+ E_FMAN_MAC_EX_10G_RX_JAB_FRM,
+ /* 10GEC Receive jabber frame interrupt */
+ E_FMAN_MAC_EX_10G_RX_OVRSZ_FRM,
+ /* 10GEC Receive oversized frame interrupt */
+ E_FMAN_MAC_EX_10G_RX_RUNT_FRM,
+ /* 10GEC Receive runt frame interrupt */
+ E_FMAN_MAC_EX_10G_RX_FRAG_FRM,
+ /* 10GEC Receive fragment frame interrupt */
+ E_FMAN_MAC_EX_10G_RX_LEN_ER,
+ /* 10GEC Receive payload length error interrupt */
+ E_FMAN_MAC_EX_10G_RX_CRC_ER,
+ /* 10GEC Receive CRC error interrupt */
+ E_FMAN_MAC_EX_10G_RX_ALIGN_ER,
+ /* 10GEC Receive alignment error interrupt */
+ E_FMAN_MAC_EX_1G_BAB_RX,
+ /* dTSEC Babbling receive error */
+ E_FMAN_MAC_EX_1G_RX_CTL,
+ /* dTSEC Receive control (pause frame) interrupt */
+ E_FMAN_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET,
+ /* dTSEC Graceful transmit stop complete */
+ E_FMAN_MAC_EX_1G_BAB_TX,
+ /* dTSEC Babbling transmit error */
+ E_FMAN_MAC_EX_1G_TX_CTL,
+ /* dTSEC Transmit control (pause frame) interrupt */
+ E_FMAN_MAC_EX_1G_TX_ERR,
+ /* dTSEC Transmit error */
+ E_FMAN_MAC_EX_1G_LATE_COL,
+ /* dTSEC Late collision */
+ E_FMAN_MAC_EX_1G_COL_RET_LMT,
+ /* dTSEC Collision retry limit */
+ E_FMAN_MAC_EX_1G_TX_FIFO_UNDRN,
+ /* dTSEC Transmit FIFO underrun */
+ E_FMAN_MAC_EX_1G_MAG_PCKT,
+ /* dTSEC Magic Packet detection */
+ E_FMAN_MAC_EX_1G_MII_MNG_RD_COMPLET,
+ /* dTSEC MII management read completion */
+ E_FMAN_MAC_EX_1G_MII_MNG_WR_COMPLET,
+ /* dTSEC MII management write completion */
+ E_FMAN_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET,
+ /* dTSEC Graceful receive stop complete */
+ E_FMAN_MAC_EX_1G_TX_DATA_ERR,
+ /* dTSEC Internal data error on transmit */
+ E_FMAN_MAC_EX_1G_RX_DATA_ERR,
+ /* dTSEC Internal data error on receive */
+ E_FMAN_MAC_EX_1G_1588_TS_RX_ERR,
+ /* dTSEC Time-Stamp Receive Error */
+ E_FMAN_MAC_EX_1G_RX_MIB_CNT_OVFL,
+ /* dTSEC MIB counter overflow */
+ E_FMAN_MAC_EX_TS_FIFO_ECC_ERR,
+ /* < mEMAC Time-stamp FIFO ECC error interrupt;
+ * not supported on T4240/B4860 rev1 chips
+ */
+};
+
+/* SGMII/QSGII interface with 1000BaseX auto-negotiation between MAC
+ * and phy or backplane;
+ * Note: 1000BaseX auto-negotiation relates only to interface between MAC
+ * and phy/backplane, SGMII phy can still synchronize with far-end phy at
+ * 10Mbps, 100Mbps or 1000Mbps
+ */
+#define ENET_IF_SGMII_BASEX 0x80000000
+
+enum enet_mode {
+ E_ENET_MODE_INVALID = 0,
+ /* Invalid Ethernet mode */
+ E_ENET_MODE_MII_10 = (E_ENET_IF_MII | E_ENET_SPEED_10),
+ /* 10 Mbps MII */
+ E_ENET_MODE_MII_100 = (E_ENET_IF_MII | E_ENET_SPEED_100),
+ /* 100 Mbps MII */
+ E_ENET_MODE_RMII_10 = (E_ENET_IF_RMII | E_ENET_SPEED_10),
+ /* 10 Mbps RMII */
+ E_ENET_MODE_RMII_100 = (E_ENET_IF_RMII | E_ENET_SPEED_100),
+ /* 100 Mbps RMII */
+ E_ENET_MODE_SMII_10 = (E_ENET_IF_SMII | E_ENET_SPEED_10),
+ /* 10 Mbps SMII */
+ E_ENET_MODE_SMII_100 = (E_ENET_IF_SMII | E_ENET_SPEED_100),
+ /* 100 Mbps SMII */
+ E_ENET_MODE_GMII_1000 = (E_ENET_IF_GMII | E_ENET_SPEED_1000),
+ /* 1000 Mbps GMII */
+ E_ENET_MODE_RGMII_10 = (E_ENET_IF_RGMII | E_ENET_SPEED_10),
+ /* 10 Mbps RGMII */
+ E_ENET_MODE_RGMII_100 = (E_ENET_IF_RGMII | E_ENET_SPEED_100),
+ /* 100 Mbps RGMII */
+ E_ENET_MODE_RGMII_1000 = (E_ENET_IF_RGMII | E_ENET_SPEED_1000),
+ /* 1000 Mbps RGMII */
+ E_ENET_MODE_TBI_1000 = (E_ENET_IF_TBI | E_ENET_SPEED_1000),
+ /* 1000 Mbps TBI */
+ E_ENET_MODE_RTBI_1000 = (E_ENET_IF_RTBI | E_ENET_SPEED_1000),
+ /* 1000 Mbps RTBI */
+ E_ENET_MODE_SGMII_10 = (E_ENET_IF_SGMII | E_ENET_SPEED_10),
+ /* 10 Mbps SGMII with auto-negotiation between MAC and
+ * SGMII phy according to Cisco SGMII specification
+ */
+ E_ENET_MODE_SGMII_100 = (E_ENET_IF_SGMII | E_ENET_SPEED_100),
+ /* 100 Mbps SGMII with auto-negotiation between MAC and
+ * SGMII phy according to Cisco SGMII specification
+ */
+ E_ENET_MODE_SGMII_1000 = (E_ENET_IF_SGMII | E_ENET_SPEED_1000),
+ /* 1000 Mbps SGMII with auto-negotiation between MAC and
+ * SGMII phy according to Cisco SGMII specification
+ */
+ E_ENET_MODE_SGMII_BASEX_10 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII
+ | E_ENET_SPEED_10),
+ /* 10 Mbps SGMII with 1000BaseX auto-negotiation between
+ * MAC and SGMII phy or backplane
+ */
+ E_ENET_MODE_SGMII_BASEX_100 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII
+ | E_ENET_SPEED_100),
+ /* 100 Mbps SGMII with 1000BaseX auto-negotiation between
+ * MAC and SGMII phy or backplane
+ */
+ E_ENET_MODE_SGMII_BASEX_1000 = (ENET_IF_SGMII_BASEX | E_ENET_IF_SGMII
+ | E_ENET_SPEED_1000),
+ /* 1000 Mbps SGMII with 1000BaseX auto-negotiation between
+ * MAC and SGMII phy or backplane
+ */
+ E_ENET_MODE_QSGMII_1000 = (E_ENET_IF_QSGMII | E_ENET_SPEED_1000),
+ /* 1000 Mbps QSGMII with auto-negotiation between MAC and
+ * QSGMII phy according to Cisco QSGMII specification
+ */
+ E_ENET_MODE_QSGMII_BASEX_1000 = (ENET_IF_SGMII_BASEX | E_ENET_IF_QSGMII
+ | E_ENET_SPEED_1000),
+ /* 1000 Mbps QSGMII with 1000BaseX auto-negotiation between
+ * MAC and QSGMII phy or backplane
+ */
+ E_ENET_MODE_XGMII_10000 = (E_ENET_IF_XGMII | E_ENET_SPEED_10000),
+ /* 10000 Mbps XGMII */
+ E_ENET_MODE_XFI_10000 = (E_ENET_IF_XFI | E_ENET_SPEED_10000)
+ /* 10000 Mbps XFI */
+};
+
+enum fmam_mac_statistics_level {
+ E_FMAN_MAC_NONE_STATISTICS, /* No statistics */
+ E_FMAN_MAC_PARTIAL_STATISTICS, /* Only error counters are available;
+ * Optimized for performance
+ */
+ E_FMAN_MAC_FULL_STATISTICS /* All counters available; Not
+ * optimized for performance
+ */
+};
+
+#define _MAKE_ENET_MODE(_interface, _speed) (enum enet_mode)((_interface) \
+ | (_speed))
+
+#define _ENET_INTERFACE_FROM_MODE(mode) \
+ ((enum enet_interface)((mode) & 0x0FFF0000))
+
+#define _ENET_SPEED_FROM_MODE(mode) (enum enet_speed)((mode) & 0x0000FFFF)
+#define _ENET_ADDR_TO_UINT64(_enet_addr) \
+ (uint64_t)(((uint64_t)(_enet_addr)[0] << 40) | \
+ ((uint64_t)(_enet_addr)[1] << 32) | \
+ ((uint64_t)(_enet_addr)[2] << 24) | \
+ ((uint64_t)(_enet_addr)[3] << 16) | \
+ ((uint64_t)(_enet_addr)[4] << 8) | \
+ ((uint64_t)(_enet_addr)[5]))
+
+#define _MAKE_ENET_ADDR_FROM_UINT64(_addr64, _enet_addr) \
+ do { \
+ int i; \
+ for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++) \
+ (_enet_addr)[i] = \
+ (uint8_t)((_addr64) >> ((5 - i) * 8)); \
+ } while (0)
+
+#endif /* __FSL_ENET_H */
diff --git a/drivers/soc/fsl/fman/flib/fsl_fman.h b/drivers/soc/fsl/fman/flib/fsl_fman.h
new file mode 100644
index 0000000..76fd991
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fsl_fman.h
@@ -0,0 +1,801 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FMAN_H
+#define __FSL_FMAN_H
+
+#include "common/general.h"
+#include <linux/delay.h>
+
+struct fman_ext_pool_params {
+ uint8_t id; /* External buffer pool id */
+ uint16_t size; /* External buffer pool buffer size */
+};
+
+struct fman_ext_pools {
+ uint8_t num_pools_used; /* Number of pools use by this port */
+ struct fman_ext_pool_params *ext_buf_pool;
+ /* Parameters for each port */
+};
+
+struct fman_backup_bm_pools {
+ uint8_t num_backup_pools; /* Number of BM backup pools -
+ * must be smaller than the total
+ * number of pools defined for the
+ * specified port.
+ */
+ uint8_t *pool_ids; /* num_of_backup_pools pool id's,
+ * specifying which pools should be
+ * used only as backup. Pool id's
+ * specified here must be a subset
+ * of the pools used by the specified
+ * port.
+ */
+};
+
+/* A structure for defining BM pool depletion criteria */
+struct fman_buf_pool_depletion {
+ bool buf_pool_depletion_enabled;
+ bool pools_grp_mode_enable; /* select mode in which pause frames
+ * will be sent after a number of pools
+ * (all together!) are depleted
+ */
+ uint8_t num_pools; /* the number of depleted pools that
+ * will invoke pause frames transmission.
+ */
+ bool *pools_to_consider; /* For each pool, true if it should be
+ * considered for depletion (Note - this
+ * pool must be used by this port!).
+ */
+ bool single_pool_mode_enable; /* select mode in which pause frames
+ * will be sent after a single-pool
+ * is depleted;
+ */
+ bool *pools_to_consider_for_single_mode;
+ /* For each pool, true if it should be
+ * considered for depletion (Note - this
+ * pool must be used by this port!)
+ */
+ bool has_pfc_priorities;
+ bool *pfc_priorities_en; /* This field is used by the MAC as
+ * the Priority Enable Vector in the PFC
+ * frame which is transmitted
+ */
+};
+
+/* Enum for defining port DMA swap mode */
+enum fman_dma_swap_option {
+ FMAN_DMA_NO_SWP, /* No swap, transfer data as is.*/
+ FMAN_DMA_SWP_PPC_LE, /* The transferred data should be swapped
+ * in PowerPc Little Endian mode.
+ */
+ FMAN_DMA_SWP_BE /* The transferred data should be swapped
+ * in Big Endian mode
+ */
+};
+
+/* Enum for defining port DMA cache attributes */
+enum fman_dma_cache_option {
+ FMAN_DMA_NO_STASH = 0, /* Cacheable, no Allocate (No Stashing) */
+ FMAN_DMA_STASH = 1 /* Cacheable and Allocate (Stashing on) */
+};
+
+typedef struct fm_prs_result_t fm_prs_result;
+typedef enum e_enet_mode enet_mode_t;
+
+struct fman_revision_info {
+ uint8_t major_rev; /* Major revision */
+ uint8_t minor_rev; /* Minor revision */
+};
+
+/* sizes */
+#define CAPWAP_FRAG_EXTRA_SPACE 32
+#define OFFSET_UNITS 16
+#define MAX_INT_OFFSET 240
+#define MAX_IC_SIZE 256
+#define MAX_EXT_OFFSET 496
+#define MAX_EXT_BUFFER_OFFSET 511
+
+/* Memory Mapped Registers */
+#define FMAN_LIODN_TBL 64 /* size of LIODN table */
+
+struct fman_fpm_regs {
+ uint32_t fmfp_tnc; /* FPM TNUM Control 0x00 */
+ uint32_t fmfp_prc; /* FPM Port_ID FmCtl Association 0x04 */
+ uint32_t fmfp_brkc; /* FPM Breakpoint Control 0x08 */
+ uint32_t fmfp_mxd; /* FPM Flush Control 0x0c */
+ uint32_t fmfp_dist1; /* FPM Dispatch Thresholds1 0x10 */
+ uint32_t fmfp_dist2; /* FPM Dispatch Thresholds2 0x14 */
+ uint32_t fm_epi; /* FM Error Pending Interrupts 0x18 */
+ uint32_t fm_rie; /* FM Error Interrupt Enable 0x1c */
+ uint32_t fmfp_fcev[4]; /* FPM FMan-Controller Event 1-4 0x20-0x2f */
+ uint32_t res0030[4]; /* res 0x30 - 0x3f */
+ uint32_t fmfp_cee[4]; /* PM FMan-Controller Event 1-4 0x40-0x4f */
+ uint32_t res0050[4]; /* res 0x50-0x5f */
+ uint32_t fmfp_tsc1; /* FPM TimeStamp Control1 0x60 */
+ uint32_t fmfp_tsc2; /* FPM TimeStamp Control2 0x64 */
+ uint32_t fmfp_tsp; /* FPM Time Stamp 0x68 */
+ uint32_t fmfp_tsf; /* FPM Time Stamp Fraction 0x6c */
+ uint32_t fm_rcr; /* FM Rams Control 0x70 */
+ uint32_t fmfp_extc; /* FPM External Requests Control 0x74 */
+ uint32_t fmfp_ext1; /* FPM External Requests Config1 0x78 */
+ uint32_t fmfp_ext2; /* FPM External Requests Config2 0x7c */
+ uint32_t fmfp_drd[16]; /* FPM Data_Ram Data 0-15 0x80 - 0xbf */
+ uint32_t fmfp_dra; /* FPM Data Ram Access 0xc0 */
+ uint32_t fm_ip_rev_1; /* FM IP Block Revision 1 0xc4 */
+ uint32_t fm_ip_rev_2; /* FM IP Block Revision 2 0xc8 */
+ uint32_t fm_rstc; /* FM Reset Command 0xcc */
+ uint32_t fm_cld; /* FM Classifier Debug 0xd0 */
+ uint32_t fm_npi; /* FM Normal Pending Interrupts 0xd4 */
+ uint32_t fmfp_exte; /* FPM External Requests Enable 0xd8 */
+ uint32_t fmfp_ee; /* FPM Event&Mask 0xdc */
+ uint32_t fmfp_cev[4]; /* FPM CPU Event 1-4 0xe0-0xef */
+ uint32_t res00f0[4]; /* res 0xf0-0xff */
+ uint32_t fmfp_ps[50]; /* FPM Port Status 0x100-0x1c7 */
+ uint32_t res01c8[14]; /* res 0x1c8-0x1ff */
+ uint32_t fmfp_clfabc; /* FPM CLFABC 0x200 */
+ uint32_t fmfp_clfcc; /* FPM CLFCC 0x204 */
+ uint32_t fmfp_clfaval; /* FPM CLFAVAL 0x208 */
+ uint32_t fmfp_clfbval; /* FPM CLFBVAL 0x20c */
+ uint32_t fmfp_clfcval; /* FPM CLFCVAL 0x210 */
+ uint32_t fmfp_clfamsk; /* FPM CLFAMSK 0x214 */
+ uint32_t fmfp_clfbmsk; /* FPM CLFBMSK 0x218 */
+ uint32_t fmfp_clfcmsk; /* FPM CLFCMSK 0x21c */
+ uint32_t fmfp_clfamc; /* FPM CLFAMC 0x220 */
+ uint32_t fmfp_clfbmc; /* FPM CLFBMC 0x224 */
+ uint32_t fmfp_clfcmc; /* FPM CLFCMC 0x228 */
+ uint32_t fmfp_decceh; /* FPM DECCEH 0x22c */
+ uint32_t res0230[116]; /* res 0x230 - 0x3ff */
+ uint32_t fmfp_ts[128]; /* 0x400: FPM Task Status 0x400 - 0x5ff */
+ uint32_t res0600[0x400 - 384];
+};
+
+struct fman_bmi_regs {
+ uint32_t fmbm_init; /* BMI Initialization 0x00 */
+ uint32_t fmbm_cfg1; /* BMI Configuration 1 0x04 */
+ uint32_t fmbm_cfg2; /* BMI Configuration 2 0x08 */
+ uint32_t res000c[5]; /* 0x0c - 0x1f */
+ uint32_t fmbm_ievr; /* Interrupt Event Register 0x20 */
+ uint32_t fmbm_ier; /* Interrupt Enable Register 0x24 */
+ uint32_t fmbm_ifr; /* Interrupt Force Register 0x28 */
+ uint32_t res002c[5]; /* 0x2c - 0x3f */
+ uint32_t fmbm_arb[8]; /* BMI Arbitration 0x40 - 0x5f */
+ uint32_t res0060[12]; /*0x60 - 0x8f */
+ uint32_t fmbm_dtc[3]; /* Debug Trap Counter 0x90 - 0x9b */
+ uint32_t res009c; /* 0x9c */
+ uint32_t fmbm_dcv[3][4]; /* Debug Compare val 0xa0-0xcf */
+ uint32_t fmbm_dcm[3][4]; /* Debug Compare Mask 0xd0-0xff */
+ uint32_t fmbm_gde; /* BMI Global Debug Enable 0x100 */
+ uint32_t fmbm_pp[63]; /* BMI Port Parameters 0x104 - 0x1ff */
+ uint32_t res0200; /* 0x200 */
+ uint32_t fmbm_pfs[63]; /* BMI Port FIFO Size 0x204 - 0x2ff */
+ uint32_t res0300; /* 0x300 */
+ uint32_t fmbm_spliodn[63]; /* Port Partition ID 0x304 - 0x3ff */
+};
+
+struct fman_qmi_regs {
+ uint32_t fmqm_gc; /* General Configuration Register 0x00 */
+ uint32_t res0004; /* 0x04 */
+ uint32_t fmqm_eie; /* Error Interrupt Event Register 0x08 */
+ uint32_t fmqm_eien; /* Error Interrupt Enable Register 0x0c */
+ uint32_t fmqm_eif; /* Error Interrupt Force Register 0x10 */
+ uint32_t fmqm_ie; /* Interrupt Event Register 0x14 */
+ uint32_t fmqm_ien; /* Interrupt Enable Register 0x18 */
+ uint32_t fmqm_if; /* Interrupt Force Register 0x1c */
+ uint32_t fmqm_gs; /* Global Status Register 0x20 */
+ uint32_t fmqm_ts; /* Task Status Register 0x24 */
+ uint32_t fmqm_etfc; /* Enqueue Total Frame Counter 0x28 */
+ uint32_t fmqm_dtfc; /* Dequeue Total Frame Counter 0x2c */
+ uint32_t fmqm_dc0; /* Dequeue Counter 0 0x30 */
+ uint32_t fmqm_dc1; /* Dequeue Counter 1 0x34 */
+ uint32_t fmqm_dc2; /* Dequeue Counter 2 0x38 */
+ uint32_t fmqm_dc3; /* Dequeue Counter 3 0x3c */
+ uint32_t fmqm_dfdc; /* Dequeue FQID from Default Counter 0x40 */
+ uint32_t fmqm_dfcc; /* Dequeue FQID from Context Counter 0x44 */
+ uint32_t fmqm_dffc; /* Dequeue FQID from FD Counter 0x48 */
+ uint32_t fmqm_dcc; /* Dequeue Confirm Counter 0x4c */
+ uint32_t res0050[7]; /* 0x50 - 0x6b */
+ uint32_t fmqm_tapc; /* Tnum Aging Period Control 0x6c */
+ uint32_t fmqm_dmcvc; /* Dequeue MAC Command Valid Counter 0x70 */
+ uint32_t fmqm_difdcc; /* Dequeue Invalid FD Command Counter 0x74 */
+ uint32_t fmqm_da1v; /* Dequeue A1 Valid Counter 0x78 */
+ uint32_t res007c; /* 0x7c */
+ uint32_t fmqm_dtc; /* 0x80 Debug Trap Counter 0x80 */
+ uint32_t fmqm_efddd; /* 0x84 Enqueue Frame desc Dynamic dbg 0x84 */
+ uint32_t res0088[2]; /* 0x88 - 0x8f */
+ struct {
+ uint32_t fmqm_dtcfg1; /* 0x90 dbg trap cfg 1 Register 0x00 */
+ uint32_t fmqm_dtval1; /* Debug Trap Value 1 Register 0x04 */
+ uint32_t fmqm_dtm1; /* Debug Trap Mask 1 Register 0x08 */
+ uint32_t fmqm_dtc1; /* Debug Trap Counter 1 Register 0x0c */
+ uint32_t fmqm_dtcfg2; /* dbg Trap cfg 2 Register 0x10 */
+ uint32_t fmqm_dtval2; /* Debug Trap Value 2 Register 0x14 */
+ uint32_t fmqm_dtm2; /* Debug Trap Mask 2 Register 0x18 */
+ uint32_t res001c; /* 0x1c */
+ } dbg_traps[3]; /* 0x90 - 0xef */
+ uint8_t res00f0[0x400 - 0xf0]; /* 0xf0 - 0x3ff */
+};
+
+struct fman_dma_regs {
+ uint32_t fmdmsr; /* FM DMA status register 0x00 */
+ uint32_t fmdmmr; /* FM DMA mode register 0x04 */
+ uint32_t fmdmtr; /* FM DMA bus threshold register 0x08 */
+ uint32_t fmdmhy; /* FM DMA bus hysteresis register 0x0c */
+ uint32_t fmdmsetr; /* FM DMA SOS emergency Threshold Register 0x10 */
+ uint32_t fmdmtah; /* FM DMA transfer bus address high reg 0x14 */
+ uint32_t fmdmtal; /* FM DMA transfer bus address low reg 0x18 */
+ uint32_t fmdmtcid; /* FM DMA transfer bus communication ID reg 0x1c */
+ uint32_t fmdmra; /* FM DMA bus internal ram address register 0x20 */
+ uint32_t fmdmrd; /* FM DMA bus internal ram data register 0x24 */
+ uint32_t fmdmwcr; /* FM DMA CAM watchdog counter value 0x28 */
+ uint32_t fmdmebcr; /* FM DMA CAM base in MURAM register 0x2c */
+ uint32_t fmdmccqdr; /* FM DMA CAM and CMD Queue Debug reg 0x30 */
+ uint32_t fmdmccqvr1; /* FM DMA CAM and CMD Queue Value reg #1 0x34 */
+ uint32_t fmdmccqvr2; /* FM DMA CAM and CMD Queue Value reg #2 0x38 */
+ uint32_t fmdmcqvr3; /* FM DMA CMD Queue Value register #3 0x3c */
+ uint32_t fmdmcqvr4; /* FM DMA CMD Queue Value register #4 0x40 */
+ uint32_t fmdmcqvr5; /* FM DMA CMD Queue Value register #5 0x44 */
+ uint32_t fmdmsefrc; /* FM DMA Semaphore Entry Full Reject Cntr 0x48 */
+ uint32_t fmdmsqfrc; /* FM DMA Semaphore Queue Full Reject Cntr 0x4c */
+ uint32_t fmdmssrc; /* FM DMA Semaphore SYNC Reject Counter 0x50 */
+ uint32_t fmdmdcr; /* FM DMA Debug Counter 0x54 */
+ uint32_t fmdmemsr; /* FM DMA Emergency Smoother Register 0x58 */
+ uint32_t res005c; /* 0x5c */
+ uint32_t fmdmplr[FMAN_LIODN_TBL / 2]; /* DMA LIODN regs 0x60-0xdf */
+ uint32_t res00e0[0x400 - 56];
+};
+
+struct fman_rg {
+ struct fman_fpm_regs __iomem *fpm_rg;
+ struct fman_dma_regs __iomem *dma_rg;
+ struct fman_bmi_regs __iomem *bmi_rg;
+ struct fman_qmi_regs __iomem *qmi_rg;
+};
+
+enum fman_dma_cache_override {
+ E_FMAN_DMA_NO_CACHE_OR = 0, /* No override of the Cache field */
+ E_FMAN_DMA_NO_STASH_DATA, /* No data stashing in system level cache */
+ E_FMAN_DMA_MAY_STASH_DATA, /* Stashing allowed in sys level cache */
+ E_FMAN_DMA_STASH_DATA /* Stashing performed in system level cache */
+};
+
+enum fman_dma_aid_mode {
+ E_FMAN_DMA_AID_OUT_PORT_ID = 0, /* 4 LSB of PORT_ID */
+ E_FMAN_DMA_AID_OUT_TNUM /* 4 LSB of TNUM */
+};
+
+enum fman_dma_dbg_cnt_mode {
+ E_FMAN_DMA_DBG_NO_CNT = 0, /* No counting */
+ E_FMAN_DMA_DBG_CNT_DONE, /* Count DONE commands */
+ E_FMAN_DMA_DBG_CNT_COMM_Q_EM, /* command Q emergency signal */
+ E_FMAN_DMA_DBG_CNT_INT_READ_EM, /* Read buf emergency signal */
+ E_FMAN_DMA_DBG_CNT_INT_WRITE_EM, /* Write buf emergency signal */
+ E_FMAN_DMA_DBG_CNT_FPM_WAIT, /* FPM WAIT signal */
+ E_FMAN_DMA_DBG_CNT_SIGLE_BIT_ECC, /* Single bit ECC errors */
+ E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT /* RAW&WAR protection counter */
+};
+
+enum fman_dma_emergency_level {
+ E_FMAN_DMA_EM_EBS = 0, /* EBS emergency */
+ E_FMAN_DMA_EM_SOS /* SOS emergency */
+};
+
+enum fman_catastrophic_err {
+ E_FMAN_CATAST_ERR_STALL_PORT = 0, /* Port_ID stalled reset required */
+ E_FMAN_CATAST_ERR_STALL_TASK /* Only erroneous task is stalled */
+};
+
+enum fman_dma_err {
+ E_FMAN_DMA_ERR_CATASTROPHIC = 0, /* Catastrophic DMA error */
+ E_FMAN_DMA_ERR_REPORT /* Reported DMA error */
+};
+
+struct fman_cfg {
+ uint16_t liodn_bs_pr_port[FMAN_LIODN_TBL]; /* base per port */
+ bool en_counters;
+ uint8_t disp_limit_tsh;
+ uint8_t prs_disp_tsh;
+ uint8_t plcr_disp_tsh;
+ uint8_t kg_disp_tsh;
+ uint8_t bmi_disp_tsh;
+ uint8_t qmi_enq_disp_tsh;
+ uint8_t qmi_deq_disp_tsh;
+ uint8_t fm_ctl1_disp_tsh;
+ uint8_t fm_ctl2_disp_tsh;
+ enum fman_dma_cache_override dma_cache_override;
+ enum fman_dma_aid_mode dma_aid_mode;
+ bool dma_aid_override;
+ uint8_t dma_axi_dbg_num_of_beats;
+ uint8_t dma_cam_num_of_entries;
+ uint32_t dma_watchdog;
+ uint8_t dma_comm_qtsh_asrt_emer;
+ uint8_t dma_write_buf_tsh_asrt_emer;
+ uint8_t dma_read_buf_tsh_asrt_emer;
+ uint8_t dma_comm_qtsh_clr_emer;
+ uint8_t dma_write_buf_tsh_clr_emer;
+ uint8_t dma_read_buf_tsh_clr_emer;
+ uint32_t dma_sos_emergency;
+ enum fman_dma_dbg_cnt_mode dma_dbg_cnt_mode;
+ bool dma_stop_on_bus_error;
+ bool dma_en_emergency;
+ uint32_t dma_emergency_bus_select;
+ enum fman_dma_emergency_level dma_emergency_level;
+ bool dma_en_emergency_smoother;
+ uint32_t dma_emergency_switch_counter;
+ bool halt_on_external_activ;
+ bool halt_on_unrecov_ecc_err;
+ enum fman_catastrophic_err catastrophic_err;
+ enum fman_dma_err dma_err;
+ bool en_muram_test_mode;
+ bool en_iram_test_mode;
+ bool external_ecc_rams_enable;
+ uint16_t tnum_aging_period;
+ uint32_t exceptions;
+ uint16_t clk_freq;
+ bool pedantic_dma;
+ uint32_t cam_base_addr;
+ uint32_t fifo_base_addr;
+ uint32_t total_fifo_size;
+ uint8_t total_num_of_tasks;
+ bool qmi_deq_option_support;
+ uint32_t qmi_def_tnums_thresh;
+ bool fman_partition_array;
+ uint8_t num_of_fman_ctrl_evnt_regs;
+};
+
+/* Exceptions */
+#define FMAN_EX_DMA_BUS_ERROR 0x80000000
+#define FMAN_EX_DMA_READ_ECC 0x40000000
+#define FMAN_EX_DMA_SYSTEM_WRITE_ECC 0x20000000
+#define FMAN_EX_DMA_FM_WRITE_ECC 0x10000000
+#define FMAN_EX_FPM_STALL_ON_TASKS 0x08000000
+#define FMAN_EX_FPM_SINGLE_ECC 0x04000000
+#define FMAN_EX_FPM_DOUBLE_ECC 0x02000000
+#define FMAN_EX_QMI_SINGLE_ECC 0x01000000
+#define FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000
+#define FMAN_EX_QMI_DOUBLE_ECC 0x00400000
+#define FMAN_EX_BMI_LIST_RAM_ECC 0x00200000
+#define FMAN_EX_BMI_PIPELINE_ECC 0x00100000
+#define FMAN_EX_BMI_STATISTICS_RAM_ECC 0x00080000
+#define FMAN_EX_IRAM_ECC 0x00040000
+#define FMAN_EX_NURAM_ECC 0x00020000
+#define FMAN_EX_BMI_DISPATCH_RAM_ECC 0x00010000
+
+enum fman_exceptions {
+ E_FMAN_EX_DMA_BUS_ERROR = 0, /* DMA bus error. */
+ E_FMAN_EX_DMA_READ_ECC, /* Read Buffer ECC error */
+ E_FMAN_EX_DMA_SYSTEM_WRITE_ECC, /* Write Buffer ECC err on sys side */
+ E_FMAN_EX_DMA_FM_WRITE_ECC, /* Write Buffer ECC error on FM side */
+ E_FMAN_EX_FPM_STALL_ON_TASKS, /* Stall of tasks on FPM */
+ E_FMAN_EX_FPM_SINGLE_ECC, /* Single ECC on FPM. */
+ E_FMAN_EX_FPM_DOUBLE_ECC, /* Double ECC error on FPM ram access */
+ E_FMAN_EX_QMI_SINGLE_ECC, /* Single ECC on QMI. */
+ E_FMAN_EX_QMI_DOUBLE_ECC, /* Double bit ECC occurred on QMI */
+ E_FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID,/* DeQ from unknown port id */
+ E_FMAN_EX_BMI_LIST_RAM_ECC, /* Linked List RAM ECC error */
+ E_FMAN_EX_BMI_STORAGE_PROFILE_ECC, /* storage profile */
+ E_FMAN_EX_BMI_STATISTICS_RAM_ECC, /* Statistics RAM ECC Err Enable */
+ E_FMAN_EX_BMI_DISPATCH_RAM_ECC, /* Dispatch RAM ECC Error Enable */
+ E_FMAN_EX_IRAM_ECC, /* Double bit ECC occurred on IRAM*/
+ E_FMAN_EX_MURAM_ECC /* Double bit ECC occurred on MURAM*/
+};
+
+enum fman_counters {
+ E_FMAN_COUNTERS_ENQ_TOTAL_FRAME = 0, /* QMI tot enQ frames counter */
+ E_FMAN_COUNTERS_DEQ_TOTAL_FRAME, /* QMI tot deQ frames counter */
+ E_FMAN_COUNTERS_DEQ_0, /* QMI 0 frames from QMan counter */
+ E_FMAN_COUNTERS_DEQ_1, /* QMI 1 frames from QMan counter */
+ E_FMAN_COUNTERS_DEQ_2, /* QMI 2 frames from QMan counter */
+ E_FMAN_COUNTERS_DEQ_3, /* QMI 3 frames from QMan counter */
+ E_FMAN_COUNTERS_DEQ_FROM_DEFAULT, /* QMI deQ from dflt queue cntr */
+ E_FMAN_COUNTERS_DEQ_FROM_CONTEXT, /* QMI deQ from FQ context cntr */
+ E_FMAN_COUNTERS_DEQ_FROM_FD, /* QMI deQ from FD command field cntr */
+ E_FMAN_COUNTERS_DEQ_CONFIRM, /* QMI dequeue confirm counter */
+ E_FMAN_COUNTERS_SEMAPHOR_ENTRY_FULL_REJECT, /* DMA full entry cntr */
+ E_FMAN_COUNTERS_SEMAPHOR_QUEUE_FULL_REJECT, /* DMA full CAM Q cntr */
+ E_FMAN_COUNTERS_SEMAPHOR_SYNC_REJECT /* DMA sync counter */
+};
+
+#define FPM_PRT_FM_CTL1 0x00000001
+#define FPM_PRT_FM_CTL2 0x00000002
+
+/* DMA definitions */
+
+/* masks */
+#define DMA_MODE_AID_OR 0x20000000
+#define DMA_MODE_SBER 0x10000000
+#define DMA_MODE_BER 0x00200000
+#define DMA_MODE_EB 0x00100000
+#define DMA_MODE_ECC 0x00000020
+#define DMA_MODE_PRIVILEGE_PROT 0x00001000
+#define DMA_MODE_SECURE_PROT 0x00000800
+#define DMA_MODE_EMER_READ 0x00080000
+#define DMA_MODE_EMER_WRITE 0x00040000
+#define DMA_MODE_CACHE_OR_MASK 0xC0000000
+#define DMA_MODE_CEN_MASK 0x0000E000
+#define DMA_MODE_DBG_MASK 0x00000380
+#define DMA_MODE_AXI_DBG_MASK 0x0F000000
+
+#define DMA_EMSR_EMSTR_MASK 0x0000FFFF
+
+#define DMA_TRANSFER_PORTID_MASK 0xFF000000
+#define DMA_TRANSFER_TNUM_MASK 0x00FF0000
+#define DMA_TRANSFER_LIODN_MASK 0x00000FFF
+
+#define DMA_HIGH_LIODN_MASK 0x0FFF0000
+#define DMA_LOW_LIODN_MASK 0x00000FFF
+
+#define DMA_STATUS_CMD_QUEUE_NOT_EMPTY 0x10000000
+#define DMA_STATUS_BUS_ERR 0x08000000
+#define DMA_STATUS_READ_ECC 0x04000000
+#define DMA_STATUS_SYSTEM_WRITE_ECC 0x02000000
+#define DMA_STATUS_FM_WRITE_ECC 0x01000000
+#define DMA_STATUS_SYSTEM_DPEXT_ECC 0x00800000
+#define DMA_STATUS_FM_DPEXT_ECC 0x00400000
+#define DMA_STATUS_SYSTEM_DPDAT_ECC 0x00200000
+#define DMA_STATUS_FM_DPDAT_ECC 0x00100000
+#define DMA_STATUS_FM_SPDAT_ECC 0x00080000
+
+#define FM_LIODN_BASE_MASK 0x00000FFF
+
+/* shifts */
+#define DMA_MODE_CACHE_OR_SHIFT 30
+#define DMA_MODE_BUS_PRI_SHIFT 16
+#define DMA_MODE_AXI_DBG_SHIFT 24
+#define DMA_MODE_CEN_SHIFT 13
+#define DMA_MODE_BUS_PROT_SHIFT 10
+#define DMA_MODE_DBG_SHIFT 7
+#define DMA_MODE_EMER_LVL_SHIFT 6
+#define DMA_MODE_AID_MODE_SHIFT 4
+#define DMA_MODE_MAX_AXI_DBG_NUM_OF_BEATS 16
+#define DMA_MODE_MAX_CAM_NUM_OF_ENTRIES 32
+
+#define DMA_THRESH_COMMQ_SHIFT 24
+#define DMA_THRESH_READ_INT_BUF_SHIFT 16
+
+#define DMA_LIODN_SHIFT 16
+
+#define DMA_TRANSFER_PORTID_SHIFT 24
+#define DMA_TRANSFER_TNUM_SHIFT 16
+
+/* sizes */
+#define DMA_MAX_WATCHDOG 0xffffffff
+
+/* others */
+#define DMA_CAM_SIZEOF_ENTRY 0x40
+#define DMA_CAM_ALIGN 0x40
+#define DMA_CAM_UNITS 8
+
+/* General defines */
+
+#define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL
+#define FM_UCODE_DEBUG_INSTRUCTION 0x6ffff805UL
+
+/* FPM defines */
+
+/* masks */
+#define FPM_EV_MASK_DOUBLE_ECC 0x80000000
+#define FPM_EV_MASK_STALL 0x40000000
+#define FPM_EV_MASK_SINGLE_ECC 0x20000000
+#define FPM_EV_MASK_RELEASE_FM 0x00010000
+#define FPM_EV_MASK_DOUBLE_ECC_EN 0x00008000
+#define FPM_EV_MASK_STALL_EN 0x00004000
+#define FPM_EV_MASK_SINGLE_ECC_EN 0x00002000
+#define FPM_EV_MASK_EXTERNAL_HALT 0x00000008
+#define FPM_EV_MASK_ECC_ERR_HALT 0x00000004
+
+#define FPM_RAM_RAMS_ECC_EN 0x80000000
+#define FPM_RAM_IRAM_ECC_EN 0x40000000
+#define FPM_RAM_MURAM_ECC 0x00008000
+#define FPM_RAM_IRAM_ECC 0x00004000
+#define FPM_RAM_MURAM_TEST_ECC 0x20000000
+#define FPM_RAM_IRAM_TEST_ECC 0x10000000
+#define FPM_RAM_RAMS_ECC_EN_SRC_SEL 0x08000000
+
+#define FPM_IRAM_ECC_ERR_EX_EN 0x00020000
+#define FPM_MURAM_ECC_ERR_EX_EN 0x00040000
+
+#define FPM_REV1_MAJOR_MASK 0x0000FF00
+#define FPM_REV1_MINOR_MASK 0x000000FF
+
+#define FPM_REV2_INTEG_MASK 0x00FF0000
+#define FPM_REV2_ERR_MASK 0x0000FF00
+#define FPM_REV2_CFG_MASK 0x000000FF
+
+#define FPM_TS_FRACTION_MASK 0x0000FFFF
+#define FPM_TS_CTL_EN 0x80000000
+
+#define FPM_PRC_REALSE_STALLED 0x00800000
+
+#define FPM_PS_STALLED 0x00800000
+#define FPM_PS_FM_CTL1_SEL 0x80000000
+#define FPM_PS_FM_CTL2_SEL 0x40000000
+#define FPM_PS_FM_CTL_SEL_MASK (FPM_PS_FM_CTL1_SEL | FPM_PS_FM_CTL2_SEL)
+
+#define FPM_RSTC_FM_RESET 0x80000000
+
+#define FPM_DISP_LIMIT_MASK 0x1F000000
+#define FPM_THR1_PRS_MASK 0xFF000000
+#define FPM_THR1_KG_MASK 0x00FF0000
+#define FPM_THR1_PLCR_MASK 0x0000FF00
+#define FPM_THR1_BMI_MASK 0x000000FF
+
+#define FPM_THR2_QMI_ENQ_MASK 0xFF000000
+#define FPM_THR2_QMI_DEQ_MASK 0x000000FF
+#define FPM_THR2_FM_CTL1_MASK 0x00FF0000
+#define FPM_THR2_FM_CTL2_MASK 0x0000FF00
+
+/* shifts */
+#define FPM_DISP_LIMIT_SHIFT 24
+
+#define FPM_THR1_PRS_SHIFT 24
+#define FPM_THR1_KG_SHIFT 16
+#define FPM_THR1_PLCR_SHIFT 8
+#define FPM_THR1_BMI_SHIFT 0
+
+#define FPM_THR2_QMI_ENQ_SHIFT 24
+#define FPM_THR2_QMI_DEQ_SHIFT 0
+#define FPM_THR2_FM_CTL1_SHIFT 16
+#define FPM_THR2_FM_CTL2_SHIFT 8
+
+#define FPM_EV_MASK_CAT_ERR_SHIFT 1
+#define FPM_EV_MASK_DMA_ERR_SHIFT 0
+
+#define FPM_REV1_MAJOR_SHIFT 8
+#define FPM_REV1_MINOR_SHIFT 0
+
+#define FPM_REV2_INTEG_SHIFT 16
+#define FPM_REV2_ERR_SHIFT 8
+#define FPM_REV2_CFG_SHIFT 0
+
+#define FPM_TS_INT_SHIFT 16
+
+#define FPM_PORT_FM_CTL_PORTID_SHIFT 24
+
+#define FPM_PS_FM_CTL_SEL_SHIFT 30
+#define FPM_PRC_ORA_FM_CTL_SEL_SHIFT 16
+
+#define FPM_DISP_LIMIT_SHIFT 24
+
+/* Interrupts defines */
+#define FPM_EVENT_FM_CTL_0 0x00008000
+#define FPM_EVENT_FM_CTL 0x0000FF00
+#define FPM_EVENT_FM_CTL_BRK 0x00000080
+
+/* others */
+#define FPM_MAX_DISP_LIMIT 31
+#define FPM_RSTC_FM_RESET 0x80000000
+#define FPM_RSTC_MAC0_RESET 0x40000000
+#define FPM_RSTC_MAC1_RESET 0x20000000
+#define FPM_RSTC_MAC2_RESET 0x10000000
+#define FPM_RSTC_MAC3_RESET 0x08000000
+#define FPM_RSTC_MAC8_RESET 0x04000000
+#define FPM_RSTC_MAC4_RESET 0x02000000
+#define FPM_RSTC_MAC5_RESET 0x01000000
+#define FPM_RSTC_MAC6_RESET 0x00800000
+#define FPM_RSTC_MAC7_RESET 0x00400000
+#define FPM_RSTC_MAC9_RESET 0x00200000
+/* BMI defines */
+/* masks */
+#define BMI_INIT_START 0x80000000
+#define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000
+#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000
+#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000
+#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000
+#define BMI_NUM_OF_TASKS_MASK 0x3F000000
+#define BMI_NUM_OF_EXTRA_TASKS_MASK 0x000F0000
+#define BMI_NUM_OF_DMAS_MASK 0x00000F00
+#define BMI_NUM_OF_EXTRA_DMAS_MASK 0x0000000F
+#define BMI_FIFO_SIZE_MASK 0x000003FF
+#define BMI_EXTRA_FIFO_SIZE_MASK 0x03FF0000
+#define BMI_CFG2_DMAS_MASK 0x0000003F
+#define BMI_TOTAL_FIFO_SIZE_MASK 0x07FF0000
+#define BMI_TOTAL_NUM_OF_TASKS_MASK 0x007F0000
+
+/* shifts */
+#define BMI_CFG2_TASKS_SHIFT 16
+#define BMI_CFG2_DMAS_SHIFT 0
+#define BMI_CFG1_FIFO_SIZE_SHIFT 16
+#define BMI_FIFO_SIZE_SHIFT 0
+#define BMI_EXTRA_FIFO_SIZE_SHIFT 16
+#define BMI_NUM_OF_TASKS_SHIFT 24
+#define BMI_EXTRA_NUM_OF_TASKS_SHIFT 16
+#define BMI_NUM_OF_DMAS_SHIFT 8
+#define BMI_EXTRA_NUM_OF_DMAS_SHIFT 0
+
+/* others */
+#define BMI_FIFO_ALIGN 0x100
+#define FMAN_BMI_FIFO_UNITS 0x100
+
+/* QMI defines */
+/* masks */
+#define QMI_CFG_ENQ_EN 0x80000000
+#define QMI_CFG_DEQ_EN 0x40000000
+#define QMI_CFG_EN_COUNTERS 0x10000000
+#define QMI_CFG_SOFT_RESET 0x01000000
+#define QMI_CFG_DEQ_MASK 0x0000003F
+#define QMI_CFG_ENQ_MASK 0x00003F00
+
+#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000
+#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000
+#define QMI_INTR_EN_SINGLE_ECC 0x80000000
+
+/* shifts */
+#define QMI_CFG_ENQ_SHIFT 8
+#define QMI_TAPC_TAP 22
+
+#define QMI_GS_HALT_NOT_BUSY 0x00000002
+
+/* IRAM defines */
+/* masks */
+#define IRAM_IADD_AIE 0x80000000
+#define IRAM_READY 0x80000000
+
+uint32_t fman_get_bmi_err_event(struct fman_bmi_regs __iomem *bmi_rg);
+uint32_t fman_get_qmi_err_event(struct fman_qmi_regs __iomem *qmi_rg);
+uint32_t fman_get_dma_com_id(struct fman_dma_regs __iomem *dma_rg);
+uint64_t fman_get_dma_addr(struct fman_dma_regs __iomem *dma_rg);
+uint32_t fman_get_dma_err_event(struct fman_dma_regs __iomem *dma_rg);
+uint32_t fman_get_fpm_err_event(struct fman_fpm_regs __iomem *fpm_rg);
+uint32_t fman_get_muram_err_event(struct fman_fpm_regs __iomem *fpm_rg);
+uint32_t fman_get_iram_err_event(struct fman_fpm_regs __iomem *fpm_rg);
+uint32_t fman_get_qmi_event(struct fman_qmi_regs __iomem *qmi_rg);
+uint32_t fman_get_fpm_error_interrupts(struct fman_fpm_regs __iomem *fpm_rg);
+uint32_t fman_get_ctrl_intr(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t event_reg_id);
+uint8_t fman_get_qmi_deq_th(struct fman_qmi_regs __iomem *qmi_rg);
+uint8_t fman_get_qmi_enq_th(struct fman_qmi_regs __iomem *qmi_rg);
+uint16_t fman_get_size_of_fifo(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id);
+uint32_t fman_get_total_fifo_size(struct fman_bmi_regs __iomem *bmi_rg);
+uint16_t fman_get_size_of_extra_fifo(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id);
+uint8_t fman_get_num_of_tasks(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id);
+uint8_t fman_get_num_extra_tasks(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id);
+uint8_t fman_get_num_of_dmas(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id);
+uint8_t fman_get_num_extra_dmas(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id);
+uint32_t fman_get_normal_pending(struct fman_fpm_regs __iomem *fpm_rg);
+uint32_t fman_get_controller_event(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t reg_id);
+uint32_t fman_get_error_pending(struct fman_fpm_regs __iomem *fpm_rg);
+void fman_get_revision(struct fman_fpm_regs __iomem *fpm_rg, uint8_t *major,
+ uint8_t *minor);
+uint32_t fman_get_counter(struct fman_rg *fman_rg, enum fman_counters reg_name);
+uint32_t fman_get_dma_status(struct fman_dma_regs __iomem *dma_rg);
+
+int fman_set_erratum_10gmac_a004_wa(struct fman_fpm_regs __iomem *fpm_rg);
+void fman_set_ctrl_intr(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t event_reg_id,
+ uint32_t enable_events);
+void fman_set_num_of_riscs_per_port(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t port_id,
+ uint8_t num_fman_ctrls,
+ uint32_t or_fman_ctrl);
+void fman_set_order_restoration_per_port(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t port_id, bool is_rx_port);
+void fman_set_qmi_enq_th(struct fman_qmi_regs __iomem *qmi_rg, uint8_t val);
+void fman_set_qmi_deq_th(struct fman_qmi_regs __iomem *qmi_rg, uint8_t val);
+void fman_set_liodn_per_port(struct fman_rg *fman_rg,
+ uint8_t port_id,
+ uint16_t liodn_base, uint16_t liodn_offset);
+void fman_set_size_of_fifo(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id,
+ uint32_t size_of_fifo, uint32_t extra_size_of_fifo);
+void fman_set_num_of_tasks(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id,
+ uint8_t num_of_tasks, uint8_t num_of_extra_tasks);
+void fman_set_num_of_open_dmas(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id,
+ uint8_t num_of_open_dmas,
+ uint8_t num_of_extra_open_dmas,
+ uint8_t total_num_of_dmas);
+void fman_set_ports_bandwidth(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t *weights);
+int fman_set_exception(struct fman_rg *fman_rg,
+ enum fman_exceptions exception, bool enable);
+void fman_set_dma_emergency(struct fman_dma_regs __iomem *dma_rg,
+ bool is_write,
+ bool enable);
+void fman_set_dma_ext_bus_pri(struct fman_dma_regs __iomem *dma_rg,
+ uint32_t pri);
+void fman_set_congestion_group_pfc_priority(uint32_t __iomem *cpg_rg,
+ uint32_t congestion_group_id,
+ uint8_t priority_bit_map,
+ uint32_t reg_num);
+
+void fman_defconfig(struct fman_cfg *cfg);
+void fman_regconfig(struct fman_rg *fman_rg, struct fman_cfg *cfg);
+int fman_fpm_init(struct fman_fpm_regs __iomem *fpm_rg, struct fman_cfg *cfg);
+int fman_bmi_init(struct fman_bmi_regs __iomem *bmi_rg, struct fman_cfg *cfg);
+int fman_qmi_init(struct fman_qmi_regs __iomem *qmi_rg, struct fman_cfg *cfg);
+int fman_dma_init(struct fman_dma_regs __iomem *dma_rg, struct fman_cfg *cfg);
+void fman_free_resources(struct fman_rg *fman_rg);
+int fman_enable(struct fman_rg *fman_rg, struct fman_cfg *cfg);
+void fman_reset(struct fman_fpm_regs __iomem *fpm_rg);
+void fman_resume(struct fman_fpm_regs __iomem *fpm_rg);
+
+void fman_enable_time_stamp(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t count1ubit, uint16_t fm_clk_freq);
+void fman_enable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg);
+void fman_qmi_disable_dispatch_limit(struct fman_fpm_regs __iomem *fpm_rg);
+void fman_disable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg);
+void fman_resume_stalled_port(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t port_id);
+int fman_reset_mac(struct fman_fpm_regs __iomem *fpm_rg, uint8_t mac_id);
+bool fman_is_port_stalled(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t port_id);
+bool fman_rams_ecc_is_external_ctl(struct fman_fpm_regs __iomem *fpm_rg);
+bool fman_is_qmi_halt_not_busy_state(struct fman_qmi_regs __iomem *qmi_rg);
+int fman_modify_counter(struct fman_rg *fman_rg,
+ enum fman_counters reg_name, uint32_t val);
+void fman_force_intr(struct fman_rg *fman_rg, enum fman_exceptions exception);
+void fman_set_vsp_window(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id,
+ uint8_t base_storage_profile,
+ uint8_t log2_num_of_profiles);
+
+/* default values */
+#define DEFAULT_CATASTROPHIC_ERR E_FMAN_CATAST_ERR_STALL_PORT
+#define DEFAULT_DMA_ERR E_FMAN_DMA_ERR_CATASTROPHIC
+/* do not change! if changed, must be disabled for rev1 ! */
+#define DEFAULT_HALT_ON_EXTERNAL_ACTIVATION false
+/* do not change! if changed, must be disabled for rev1 ! */
+#define DEFAULT_HALT_ON_UNRECOVERABLE_ECC_ERROR false
+#define DEFAULT_EXTERNAL_ECC_RAMS_ENABLE false
+#define DEFAULT_AID_OVERRIDE false
+#define DEFAULT_AID_MODE E_FMAN_DMA_AID_OUT_TNUM
+#define DEFAULT_DMA_COMM_Q_LOW 0x2A
+#define DEFAULT_DMA_COMM_Q_HIGH 0x3F
+#define DEFAULT_CACHE_OVERRIDE E_FMAN_DMA_NO_CACHE_OR
+#define DEFAULT_DMA_CAM_NUM_OF_ENTRIES 64
+#define DEFAULT_DMA_DBG_CNT_MODE E_FMAN_DMA_DBG_NO_CNT
+#define DEFAULT_DMA_EN_EMERGENCY false
+#define DEFAULT_DMA_SOS_EMERGENCY 0
+#define DEFAULT_DMA_WATCHDOG 0 /* disabled */
+#define DEFAULT_DMA_EN_EMERGENCY_SMOOTHER false
+#define DEFAULT_DMA_EMERGENCY_SWITCH_COUNTER 0
+#define DEFAULT_DISP_LIMIT 0
+#define DEFAULT_PRS_DISP_TH 16
+#define DEFAULT_PLCR_DISP_TH 16
+#define DEFAULT_KG_DISP_TH 16
+#define DEFAULT_BMI_DISP_TH 16
+#define DEFAULT_QMI_ENQ_DISP_TH 16
+#define DEFAULT_QMI_DEQ_DISP_TH 16
+#define DEFAULT_FM_CTL1_DISP_TH 16
+#define DEFAULT_FM_CTL2_DISP_TH 16
+#define DEFAULT_TNUM_AGING_PERIOD 4
+
+#endif /* __FSL_FMAN_H */
diff --git a/drivers/soc/fsl/fman/flib/fsl_fman_dtsec.h b/drivers/soc/fsl/fman/flib/fsl_fman_dtsec.h
new file mode 100644
index 0000000..104352c
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fsl_fman_dtsec.h
@@ -0,0 +1,1017 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FMAN_DTSEC_H
+#define __FSL_FMAN_DTSEC_H
+
+#include "common/general.h"
+#include "fsl_enet.h"
+
+/* dTSEC Init sequence
+ *To prepare dTSEC block for transfer use the following call sequence:
+ *- fman_dtsec_defconfig() - This step is optional and yet recommended. Its
+ *use is to obtain the default dTSEC configuration parameters.
+ *- Change dtsec configuration in &dtsec_cfg. This structure will be used
+ *to customize the dTSEC behavior.
+ *- fman_dtsec_init() - Applies the configuration on dTSEC hardware. Note that
+ *dTSEC is initialized while both Tx and Rx are disabled.
+ *- fman_dtsec_set_mac_address() - Set the station address (mac address).
+ *This is used by dTSEC to match against received packets.
+ *
+ *- fman_dtsec_adjust_link() - Set the link speed and duplex parameters
+ *after the PHY establishes the link.
+ *- dtsec_enable_tx() and dtsec_enable_rx() to enable transmission and
+ *reception.
+ */
+
+/* dTSEC Graceful stop
+ *To temporary stop dTSEC activity use fman_dtsec_stop_tx() and
+ *fman_dtsec_stop_rx(). Note that these functions request dTSEC graceful stop
+ *but return before this stop is complete. To query for graceful stop
+ *completion use fman_dtsec_get_event() and check DTSEC_IEVENT_GTSC and
+ *DTSEC_IEVENT_GRSC bits. Alternatively the dTSEC interrupt mask can be set to
+ *enable graceful stop interrupts.
+ *To resume operation after graceful stop use fman_dtsec_start_tx() and
+ *fman_dtsec_start_rx().
+ */
+
+/* dTSEC interrupt handling
+ *
+ *This code does not provide an interrupt handler for dTSEC. Instead this
+ *handler should be implemented and registered to the operating system by the
+ *caller. Some primitives for accessing the event status and mask registers
+ *are provided.
+ *See "dTSEC Events" section for a list of events that dTSEC can generate.
+ */
+
+/*dTSEC Events
+ *Interrupt events cause dTSEC event bits to be set. Software may poll the
+ *event register at any time to check for pending interrupts. If an event
+ *occurs and its corresponding enable bit is set in the interrupt mask
+ *register, the event also causes a hardware interrupt at the PIC.
+ *To poll for event status use the fman_dtsec_get_event() function.
+ *To configure the interrupt mask use fman_dtsec_enable_interrupt() and
+ *fman_dtsec_disable_interrupt() functions.
+ *After servicing a dTSEC interrupt use fman_dtsec_ack_event to reset the
+ *serviced event bit.
+ *The following events may be signaled by dTSEC hardware:
+ *%DTSEC_IEVENT_BABR - Babbling receive error. This bit indicates that
+ *a frame was received with length in excess of the MAC's maximum frame length
+ *register.
+ *%DTSEC_IEVENT_RXC - Receive control (pause frame) interrupt. A pause
+ *control frame was received while Rx pause frame handling is enabled.
+ *Also see fman_dtsec_handle_rx_pause().
+ *%DTSEC_IEVENT_MSRO - MIB counter overflow. The count for one of the MIB
+ *counters has exceeded the size of its register.
+ *%DTSEC_IEVENT_GTSC - Graceful transmit stop complete. Graceful stop is now
+ *complete. The transmitter is in a stopped state, in which only pause frames
+ *can be transmitted.
+ *Also see fman_dtsec_stop_tx().
+ *%DTSEC_IEVENT_BABT - Babbling transmit error. The transmitted frame length
+ *has exceeded the value in the MAC's Maximum Frame Length register.
+ *%DTSEC_IEVENT_TXC - Transmit control (pause frame) interrupt. his bit
+ *indicates that a control frame was transmitted.
+ *%DTSEC_IEVENT_TXE - Transmit error. This bit indicates that an error
+ *occurred on the transmitted channel. This bit is set whenever any transmit
+ *error occurs which causes the dTSEC to discard all or part of a frame
+ *(LC, CRL, XFUN).
+ *%DTSEC_IEVENT_LC - Late collision. This bit indicates that a collision
+ *occurred beyond the collision window (slot time) in half-duplex mode.
+ *The frame is truncated with a bad CRC and the remainder of the frame
+ *is discarded.
+ *%DTSEC_IEVENT_CRL - Collision retry limit. is bit indicates that the number
+ *of successive transmission collisions has exceeded the MAC's half-duplex
+ *register's retransmission maximum count. The frame is discarded without
+ *being transmitted and transmission of the next frame commences. This only
+ *occurs while in half-duplex mode.
+ *The number of retransmit attempts can be set in
+ *&dtsec_halfdup_cfg.retransmit before calling fman_dtsec_init().
+ *%DTSEC_IEVENT_XFUN - Transmit FIFO underrun. This bit indicates that the
+ *transmit FIFO became empty before the complete frame was transmitted.
+ *The frame is truncated with a bad CRC and the remainder of the frame is
+ *discarded.
+ *%DTSEC_IEVENT_MAG - TBD
+ *%DTSEC_IEVENT_MMRD - MII management read completion.
+ *%DTSEC_IEVENT_MMWR - MII management write completion.
+ *%DTSEC_IEVENT_GRSC - Graceful receive stop complete. It allows the user to
+ *know if the system has completed the stop and it is safe to write to receive
+ *registers (status, control or configuration registers) that are used by the
+ *system during normal operation.
+ *%DTSEC_IEVENT_TDPE - Internal data error on transmit. This bit indicates
+ *that the dTSEC has detected a parity error on its stored transmit data, which
+ *is likely to compromise the validity of recently transferred frames.
+ *%DTSEC_IEVENT_RDPE - Internal data error on receive. This bit indicates that
+ *the dTSEC has detected a parity error on its stored receive data, which is
+ *likely to compromise the validity of recently transferred frames.
+ */
+/* Interrupt Mask Register (IMASK) */
+#define DTSEC_IMASK_BREN 0x80000000
+#define DTSEC_IMASK_RXCEN 0x40000000
+#define DTSEC_IMASK_MSROEN 0x04000000
+#define DTSEC_IMASK_GTSCEN 0x02000000
+#define DTSEC_IMASK_BTEN 0x01000000
+#define DTSEC_IMASK_TXCEN 0x00800000
+#define DTSEC_IMASK_TXEEN 0x00400000
+#define DTSEC_IMASK_LCEN 0x00040000
+#define DTSEC_IMASK_CRLEN 0x00020000
+#define DTSEC_IMASK_XFUNEN 0x00010000
+#define DTSEC_IMASK_ABRTEN 0x00008000
+#define DTSEC_IMASK_IFERREN 0x00004000
+#define DTSEC_IMASK_MAGEN 0x00000800
+#define DTSEC_IMASK_MMRDEN 0x00000400
+#define DTSEC_IMASK_MMWREN 0x00000200
+#define DTSEC_IMASK_GRSCEN 0x00000100
+#define DTSEC_IMASK_TDPEEN 0x00000002
+#define DTSEC_IMASK_RDPEEN 0x00000001
+
+#define DTSEC_EVENTS_MASK \
+ ((uint32_t)(DTSEC_IMASK_BREN | \
+ DTSEC_IMASK_RXCEN | \
+ DTSEC_IMASK_BTEN | \
+ DTSEC_IMASK_TXCEN | \
+ DTSEC_IMASK_TXEEN | \
+ DTSEC_IMASK_ABRTEN | \
+ DTSEC_IMASK_LCEN | \
+ DTSEC_IMASK_CRLEN | \
+ DTSEC_IMASK_XFUNEN | \
+ DTSEC_IMASK_IFERREN | \
+ DTSEC_IMASK_MAGEN | \
+ DTSEC_IMASK_TDPEEN | \
+ DTSEC_IMASK_RDPEEN))
+
+/* dtsec timestamp event bits */
+#define TMR_PEMASK_TSREEN 0x00010000
+#define TMR_PEVENT_TSRE 0x00010000
+
+/* Group address bit indication */
+#define MAC_GROUP_ADDRESS 0x0000010000000000ULL
+/* size in bytes of L2 address */
+#define MAC_ADDRLEN 6
+
+#define DEFAULT_HALFDUP_ON false
+#define DEFAULT_HALFDUP_RETRANSMIT 0xf
+#define DEFAULT_HALFDUP_COLL_WINDOW 0x37
+#define DEFAULT_HALFDUP_EXCESS_DEFER true
+#define DEFAULT_HALFDUP_NO_BACKOFF false
+#define DEFAULT_HALFDUP_BP_NO_BACKOFF false
+#define DEFAULT_HALFDUP_ALT_BACKOFF_VAL 0x0A
+#define DEFAULT_HALFDUP_ALT_BACKOFF_EN false
+#define DEFAULT_RX_DROP_BCAST false
+#define DEFAULT_RX_SHORT_FRM true
+#define DEFAULT_RX_LEN_CHECK false
+#define DEFAULT_TX_PAD_CRC true
+#define DEFAULT_TX_CRC false
+#define DEFAULT_RX_CTRL_ACC false
+#define DEFAULT_TX_PAUSE_TIME 0xf000
+#define DEFAULT_TBIPA 5
+#define DEFAULT_RX_PREPEND 0
+#define DEFAULT_PTP_TSU_EN true
+#define DEFAULT_PTP_EXCEPTION_EN true
+#define DEFAULT_PREAMBLE_LEN 7
+#define DEFAULT_RX_PREAMBLE false
+#define DEFAULT_TX_PREAMBLE false
+#define DEFAULT_LOOPBACK false
+#define DEFAULT_RX_TIME_STAMP_EN false
+#define DEFAULT_TX_TIME_STAMP_EN false
+#define DEFAULT_RX_FLOW true
+#define DEFAULT_TX_FLOW true
+#define DEFAULT_RX_GROUP_HASH_EXD false
+#define DEFAULT_TX_PAUSE_TIME_EXTD 0
+#define DEFAULT_RX_PROMISC false
+#define DEFAULT_NON_BACK_TO_BACK_IPG1 0x40
+#define DEFAULT_NON_BACK_TO_BACK_IPG2 0x60
+#define DEFAULT_MIN_IFG_ENFORCEMENT 0x50
+#define DEFAULT_BACK_TO_BACK_IPG 0x60
+#define DEFAULT_MAXIMUM_FRAME 0x600
+#define DEFAULT_TBI_PHY_ADDR 5
+#define DEFAULT_WAKE_ON_LAN false
+
+/* register related defines (bits, field offsets..) */
+#define DTSEC_ID1_ID 0xffff0000
+#define DTSEC_ID1_REV_MJ 0x0000FF00
+#define DTSEC_ID1_REV_MN 0x000000ff
+
+#define DTSEC_ID2_INT_REDUCED_OFF 0x00010000
+#define DTSEC_ID2_INT_NORMAL_OFF 0x00020000
+
+#define DTSEC_ECNTRL_CLRCNT 0x00004000
+#define DTSEC_ECNTRL_AUTOZ 0x00002000
+#define DTSEC_ECNTRL_STEN 0x00001000
+#define DTSEC_ECNTRL_CFG_RO 0x80000000
+#define DTSEC_ECNTRL_GMIIM 0x00000040
+#define DTSEC_ECNTRL_TBIM 0x00000020
+#define DTSEC_ECNTRL_SGMIIM 0x00000002
+#define DTSEC_ECNTRL_RPM 0x00000010
+#define DTSEC_ECNTRL_R100M 0x00000008
+#define DTSEC_ECNTRL_RMM 0x00000004
+#define DTSEC_ECNTRL_QSGMIIM 0x00000001
+
+#define DTSEC_TCTRL_THDF 0x00000800
+#define DTSEC_TCTRL_TTSE 0x00000040
+#define DTSEC_TCTRL_GTS 0x00000020
+#define DTSEC_TCTRL_TFC_PAUSE 0x00000010
+
+/* PTV offsets */
+#define PTV_PTE_OFST 16
+
+#define RCTRL_CFA 0x00008000
+#define RCTRL_GHTX 0x00000400
+#define RCTRL_RTSE 0x00000040
+#define RCTRL_GRS 0x00000020
+#define RCTRL_BC_REJ 0x00000010
+#define RCTRL_MPROM 0x00000008
+#define RCTRL_RSF 0x00000004
+#define RCTRL_UPROM 0x00000001
+#define RCTRL_PROM (RCTRL_UPROM | RCTRL_MPROM)
+
+#define TMR_CTL_ESFDP 0x00000800
+#define TMR_CTL_ESFDE 0x00000400
+
+#define MACCFG1_SOFT_RESET 0x80000000
+#define MACCFG1_LOOPBACK 0x00000100
+#define MACCFG1_RX_FLOW 0x00000020
+#define MACCFG1_TX_FLOW 0x00000010
+#define MACCFG1_TX_EN 0x00000001
+#define MACCFG1_RX_EN 0x00000004
+
+#define MACCFG2_NIBBLE_MODE 0x00000100
+#define MACCFG2_BYTE_MODE 0x00000200
+#define MACCFG2_PRE_AM_RX_EN 0x00000080
+#define MACCFG2_PRE_AM_TX_EN 0x00000040
+#define MACCFG2_LENGTH_CHECK 0x00000010
+#define MACCFG2_MAGIC_PACKET_EN 0x00000008
+#define MACCFG2_PAD_CRC_EN 0x00000004
+#define MACCFG2_CRC_EN 0x00000002
+#define MACCFG2_FULL_DUPLEX 0x00000001
+
+#define PREAMBLE_LENGTH_SHIFT 12
+
+#define IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT 24
+#define IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT 16
+#define IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT 8
+
+#define IPGIFG_NON_BACK_TO_BACK_IPG_1 0x7F000000
+#define IPGIFG_NON_BACK_TO_BACK_IPG_2 0x007F0000
+#define IPGIFG_MIN_IFG_ENFORCEMENT 0x0000FF00
+#define IPGIFG_BACK_TO_BACK_IPG 0x0000007F
+
+#define HAFDUP_ALT_BEB 0x00080000
+#define HAFDUP_BP_NO_BACKOFF 0x00040000
+#define HAFDUP_NO_BACKOFF 0x00020000
+#define HAFDUP_EXCESS_DEFER 0x00010000
+#define HAFDUP_COLLISION_WINDOW 0x000003ff
+
+#define HAFDUP_ALTERNATE_BEB_TRUNCATION_SHIFT 20
+#define HAFDUP_RETRANSMISSION_MAX_SHIFT 12
+#define HAFDUP_RETRANSMISSION_MAX 0x0000f000
+
+#define NUM_OF_HASH_REGS 8 /* Number of hash table registers */
+
+/* CAR1/2 bits */
+#define DTSEC_CAR1_TR64 0x80000000
+#define DTSEC_CAR1_TR127 0x40000000
+#define DTSEC_CAR1_TR255 0x20000000
+#define DTSEC_CAR1_TR511 0x10000000
+#define DTSEC_CAR1_TRK1 0x08000000
+#define DTSEC_CAR1_TRMAX 0x04000000
+#define DTSEC_CAR1_TRMGV 0x02000000
+
+#define DTSEC_CAR1_RBYT 0x00010000
+#define DTSEC_CAR1_RPKT 0x00008000
+#define DTSEC_CAR1_RFCS 0x00004000
+#define DTSEC_CAR1_RMCA 0x00002000
+#define DTSEC_CAR1_RBCA 0x00001000
+#define DTSEC_CAR1_RXCF 0x00000800
+#define DTSEC_CAR1_RXPF 0x00000400
+#define DTSEC_CAR1_RXUO 0x00000200
+#define DTSEC_CAR1_RALN 0x00000100
+#define DTSEC_CAR1_RFLR 0x00000080
+#define DTSEC_CAR1_RCDE 0x00000040
+#define DTSEC_CAR1_RCSE 0x00000020
+#define DTSEC_CAR1_RUND 0x00000010
+#define DTSEC_CAR1_ROVR 0x00000008
+#define DTSEC_CAR1_RFRG 0x00000004
+#define DTSEC_CAR1_RJBR 0x00000002
+#define DTSEC_CAR1_RDRP 0x00000001
+
+#define DTSEC_CAR2_TJBR 0x00080000
+#define DTSEC_CAR2_TFCS 0x00040000
+#define DTSEC_CAR2_TXCF 0x00020000
+#define DTSEC_CAR2_TOVR 0x00010000
+#define DTSEC_CAR2_TUND 0x00008000
+#define DTSEC_CAR2_TFRG 0x00004000
+#define DTSEC_CAR2_TBYT 0x00002000
+#define DTSEC_CAR2_TPKT 0x00001000
+#define DTSEC_CAR2_TMCA 0x00000800
+#define DTSEC_CAR2_TBCA 0x00000400
+#define DTSEC_CAR2_TXPF 0x00000200
+#define DTSEC_CAR2_TDFR 0x00000100
+#define DTSEC_CAR2_TEDF 0x00000080
+#define DTSEC_CAR2_TSCL 0x00000040
+#define DTSEC_CAR2_TMCL 0x00000020
+#define DTSEC_CAR2_TLCL 0x00000010
+#define DTSEC_CAR2_TXCL 0x00000008
+#define DTSEC_CAR2_TNCL 0x00000004
+#define DTSEC_CAR2_TDRP 0x00000001
+
+#define CAM1_ERRORS_ONLY \
+ (DTSEC_CAR1_RXPF | DTSEC_CAR1_RALN | DTSEC_CAR1_RFLR \
+ | DTSEC_CAR1_RCDE | DTSEC_CAR1_RCSE | DTSEC_CAR1_RUND \
+ | DTSEC_CAR1_ROVR | DTSEC_CAR1_RFRG | DTSEC_CAR1_RJBR \
+ | DTSEC_CAR1_RDRP)
+
+#define CAM2_ERRORS_ONLY (DTSEC_CAR2_TFCS | DTSEC_CAR2_TXPF | DTSEC_CAR2_TDRP)
+
+/* Group of dTSEC specific counters relating to the standard RMON MIB Group 1
+ * (or Ethernet) statistics.
+ */
+#define CAM1_MIB_GRP_1 \
+ (DTSEC_CAR1_RDRP | DTSEC_CAR1_RBYT | DTSEC_CAR1_RPKT | DTSEC_CAR1_RMCA\
+ | DTSEC_CAR1_RBCA | DTSEC_CAR1_RALN | DTSEC_CAR1_RUND | DTSEC_CAR1_ROVR\
+ | DTSEC_CAR1_RFRG | DTSEC_CAR1_RJBR \
+ | DTSEC_CAR1_TR64 | DTSEC_CAR1_TR127 | DTSEC_CAR1_TR255 \
+ | DTSEC_CAR1_TR511 | DTSEC_CAR1_TRMAX)
+
+#define CAM2_MIB_GRP_1 (DTSEC_CAR2_TNCL | DTSEC_CAR2_TDRP)
+
+/* memory map */
+
+struct dtsec_regs {
+ /* dTSEC General Control and Status Registers */
+ uint32_t tsec_id; /* 0x000 ETSEC_ID register */
+ uint32_t tsec_id2; /* 0x004 ETSEC_ID2 register */
+ uint32_t ievent; /* 0x008 Interrupt event register */
+ uint32_t imask; /* 0x00C Interrupt mask register */
+ uint32_t reserved0010[1];
+ uint32_t ecntrl; /* 0x014 E control register */
+ uint32_t ptv; /* 0x018 Pause time value register */
+ uint32_t tbipa; /* 0x01C TBI PHY address register */
+ uint32_t tmr_ctrl; /* 0x020 Time-stamp Control register */
+ uint32_t tmr_pevent; /* 0x024 Time-stamp event register */
+ uint32_t tmr_pemask; /* 0x028 Timer event mask register */
+ uint32_t reserved002c[5];
+ uint32_t tctrl; /* 0x040 Transmit control register */
+ uint32_t reserved0044[3];
+ uint32_t rctrl; /* 0x050 Receive control register */
+ uint32_t reserved0054[11];
+ uint32_t igaddr[8]; /* 0x080-0x09C Individual/group address */
+ uint32_t gaddr[8]; /* 0x0A0-0x0BC Group address registers 0-7 */
+ uint32_t reserved00c0[16];
+ uint32_t maccfg1; /* 0x100 MAC configuration #1 */
+ uint32_t maccfg2; /* 0x104 MAC configuration #2 */
+ uint32_t ipgifg; /* 0x108 IPG/IFG */
+ uint32_t hafdup; /* 0x10C Half-duplex */
+ uint32_t maxfrm; /* 0x110 Maximum frame */
+ uint32_t reserved0114[10];
+ uint32_t ifstat; /* 0x13C Interface status */
+ uint32_t macstnaddr1; /* 0x140 Station Address,part 1 */
+ uint32_t macstnaddr2; /* 0x144 Station Address,part 2 */
+ struct {
+ uint32_t exact_match1; /* octets 1-4 */
+ uint32_t exact_match2; /* octets 5-6 */
+ } macaddr[15]; /* 0x148-0x1BC mac exact match addresses 1-15 */
+ uint32_t reserved01c0[16];
+ /* 0x200 transmit and receive 64 byte frame counter */
+ uint32_t tr64;
+ /* 0x204 transmit and receive 65 to 127 byte frame counter */
+ uint32_t tr127;
+ /* 0x208 transmit and receive 128 to 255 byte frame counter */
+ uint32_t tr255;
+ /* 0x20C transmit and receive 256 to 511 byte frame counter */
+ uint32_t tr511;
+ /* 0x210 transmit and receive 512 to 1023 byte frame counter */
+ uint32_t tr1k;
+ /* 0x214 transmit and receive 1024 to 1518 byte frame counter */
+ uint32_t trmax;
+ /* 0x218 transmit and receive 1519 to 1522 byte good VLAN frame count*/
+ uint32_t trmgv;
+ uint32_t rbyt; /* 0x21C receive byte counter */
+ uint32_t rpkt; /* 0x220 receive packet counter */
+ uint32_t rfcs; /* 0x224 receive FCS error counter */
+ /* 0x228 RMCA receive multicast packet counter */
+ uint32_t rmca;
+ uint32_t rbca; /* 0x22C receive broadcast packet counter */
+ uint32_t rxcf; /* 0x230 receive control frame packet counter */
+ uint32_t rxpf; /* 0x234 receive pause frame packet counter */
+ uint32_t rxuo; /* 0x238 receive unknown OP code counter */
+ uint32_t raln; /* 0x23C receive alignment error counter */
+ uint32_t rflr; /* 0x240 receive frame length error counter */
+ uint32_t rcde; /* 0x244 receive code error counter */
+ uint32_t rcse; /* 0x248 receive carrier sense error counter */
+ uint32_t rund; /* 0x24C receive undersize packet counter */
+ uint32_t rovr; /* 0x250 receive oversize packet counter */
+ uint32_t rfrg; /* 0x254 receive fragments counter */
+ uint32_t rjbr; /* 0x258 receive jabber counter */
+ uint32_t rdrp; /* 0x25C receive drop */
+ uint32_t tbyt; /* 0x260 transmit byte counter */
+ uint32_t tpkt; /* 0x264 transmit packet counter */
+ uint32_t tmca; /* 0x268 transmit multicast packet counter */
+ uint32_t tbca; /* 0x26C transmit broadcast packet counter */
+ uint32_t txpf; /* 0x270 transmit pause control frame counter */
+ uint32_t tdfr; /* 0x274 transmit deferral packet counter */
+ /* 0x278 transmit excessive deferral packet counter */
+ uint32_t tedf;
+ /* 0x27C transmit single collision packet counter */
+ uint32_t tscl;
+ /* 0x280 transmit multiple collision packet counter */
+ uint32_t tmcl;
+ /* 0x284 transmit late collision packet counter */
+ uint32_t tlcl;
+ /* 0x288 transmit excessive collision packet counter */
+ uint32_t txcl;
+ uint32_t tncl; /* 0x28C transmit total collision counter */
+ uint32_t reserved0290[1];
+ uint32_t tdrp; /* 0x294 transmit drop frame counter */
+ uint32_t tjbr; /* 0x298 transmit jabber frame counter */
+ uint32_t tfcs; /* 0x29C transmit FCS error counter */
+ uint32_t txcf; /* 0x2A0 transmit control frame counter */
+ uint32_t tovr; /* 0x2A4 transmit oversize frame counter */
+ uint32_t tund; /* 0x2A8 transmit undersize frame counter */
+ uint32_t tfrg; /* 0x2AC transmit fragments frame counter */
+ uint32_t car1; /* 0x2B0 carry register one register* */
+ uint32_t car2; /* 0x2B4 carry register two register* */
+ uint32_t cam1; /* 0x2B8 carry register one mask register */
+ uint32_t cam2; /* 0x2BC carry register two mask register */
+ uint32_t reserved02c0[848];
+};
+
+/*struct dtsec_mib_grp_1_counters - MIB counter overflows
+ *tr64: Transmit and Receive 64 byte frame count. Increment for each
+ * good or bad frame, of any type, transmitted or received, which
+ * is 64 bytes in length.
+ *tr127: Transmit and Receive 65 to 127 byte frame count. Increments for
+ * each good or bad frame of any type, transmitted or received,
+ * which is 65-127 bytes in length.
+ *tr255: Transmit and Receive 128 to 255 byte frame count. Increments
+ * for each good or bad frame, of any type, transmitted or
+ * received, which is 128-255 bytes in length.
+ *tr511: Transmit and Receive 256 to 511 byte frame count. Increments
+ * for each good or bad frame, of any type, transmitted or
+ * received, which is 256-511 bytes in length.
+ *tr1k: Transmit and Receive 512 to 1023 byte frame count. Increments
+ * for each good or bad frame, of any type, transmitted or
+ * received, which is 512-1023 bytes in length.
+ *trmax: Transmit and Receive 1024 to 1518 byte frame count. Increments
+ * for each good or bad frame, of any type, transmitted or
+ * received, which is 1024-1518 bytes in length.
+ *rfrg: Receive fragments count. Increments for each received frame
+ * which is less than 64 bytes in length and contains an invalid
+ * FCS. This includes integral and non-integral lengths.
+ *rjbr: Receive jabber count. Increments for received frames which
+ * exceed 1518 (non VLAN) or 1522 (VLAN) bytes and contain an
+ * invalid FCS. This includes alignment errors.
+ *rdrp: Receive dropped packets count. Increments for received frames
+ * which are streamed to system but are later dropped due to lack
+ * of system resources. Does not increment for frames rejected due
+ * to address filtering.
+ *raln: Receive alignment error count. Increments for each received
+ * frame from 64 to 1518 (non VLAN) or 1522 (VLAN) which contains
+ * an invalid FCS and is not an integral number of bytes.
+ *rund: Receive undersize packet count. Increments each time a frame is
+ * received which is less than 64 bytes in length and contains a
+ * valid FCS and is otherwise well formed. This count does not
+ * include range length errors.
+ *rovr: Receive oversize packet count. Increments each time a frame is
+ * received which exceeded 1518 (non VLAN) or 1522 (VLAN) and
+ * contains a valid FCS and is otherwise well formed.
+ *rbyt: Receive byte count. Increments by the byte count of frames
+ * received, including those in bad packets, excluding preamble and
+ * SFD but including FCS bytes.
+ *rpkt: Receive packet count. Increments for each received frame
+ * (including bad packets, all unicast, broadcast, and multicast
+ * packets).
+ *rmca: Receive multicast packet count. Increments for each multicast
+ * frame with valid CRC and of lengths 64 to 1518 (non VLAN) or
+ * 1522 (VLAN), excluding broadcast frames. This count does not
+ * include range/length errors.
+ *rbca: Receive broadcast packet count. Increments for each broadcast
+ * frame with valid CRC and of lengths 64 to 1518 (non VLAN) or
+ * 1522 (VLAN), excluding multicast frames. Does not include
+ * range/length errors.
+ *tdrp: Transmit drop frame count. Increments each time a memory error
+ * or an underrun has occurred.
+ *tncl: Transmit total collision counter. Increments by the number of
+ * collisions experienced during the transmission of a frame. Does
+ * not increment for aborted frames.
+ *
+ *The structure contains a group of dTSEC HW specific counters relating to the
+ *standard RMON MIB Group 1 (or Ethernet statistics) counters. This structure
+ *is counting only the carry events of the corresponding HW counters.
+ *
+ *tr64 to trmax notes: Frame sizes specified are considered excluding preamble
+ *and SFD but including FCS bytes.
+ */
+struct dtsec_mib_grp_1_counters {
+ uint64_t rdrp;
+ uint64_t tdrp;
+ uint64_t rbyt;
+ uint64_t rpkt;
+ uint64_t rbca;
+ uint64_t rmca;
+ uint64_t raln;
+ uint64_t rund;
+ uint64_t rovr;
+ uint64_t rfrg;
+ uint64_t rjbr;
+ uint64_t tncl;
+ uint64_t tr64;
+ uint64_t tr127;
+ uint64_t tr255;
+ uint64_t tr511;
+ uint64_t tr1k;
+ uint64_t trmax;
+};
+
+enum dtsec_stat_counters {
+ E_DTSEC_STAT_TR64,
+ E_DTSEC_STAT_TR127,
+ E_DTSEC_STAT_TR255,
+ E_DTSEC_STAT_TR511,
+ E_DTSEC_STAT_TR1K,
+ E_DTSEC_STAT_TRMAX,
+ E_DTSEC_STAT_TRMGV,
+ E_DTSEC_STAT_RBYT,
+ E_DTSEC_STAT_RPKT,
+ E_DTSEC_STAT_RMCA,
+ E_DTSEC_STAT_RBCA,
+ E_DTSEC_STAT_RXPF,
+ E_DTSEC_STAT_RALN,
+ E_DTSEC_STAT_RFLR,
+ E_DTSEC_STAT_RCDE,
+ E_DTSEC_STAT_RCSE,
+ E_DTSEC_STAT_RUND,
+ E_DTSEC_STAT_ROVR,
+ E_DTSEC_STAT_RFRG,
+ E_DTSEC_STAT_RJBR,
+ E_DTSEC_STAT_RDRP,
+ E_DTSEC_STAT_TFCS,
+ E_DTSEC_STAT_TBYT,
+ E_DTSEC_STAT_TPKT,
+ E_DTSEC_STAT_TMCA,
+ E_DTSEC_STAT_TBCA,
+ E_DTSEC_STAT_TXPF,
+ E_DTSEC_STAT_TNCL,
+ E_DTSEC_STAT_TDRP
+};
+
+enum dtsec_stat_level {
+ /* No statistics */
+ E_MAC_STAT_NONE = 0,
+ /* Only RMON MIB group 1 (ether stats). Optimized for performance */
+ E_MAC_STAT_MIB_GRP1,
+ /* Only error counters are available. Optimized for performance */
+ E_MAC_STAT_PARTIAL,
+ /* All counters available. Not optimized for performance */
+ E_MAC_STAT_FULL
+};
+
+/* struct dtsec_cfg - dTSEC configuration
+ * Transmit half-duplex flow control, under software
+ * control for 10/100-Mbps half-duplex media. If set,
+ * back pressure is applied to media by raising carrier.
+ * halfdup_retransmit:
+ * Number of retransmission attempts following a collision.
+ * If this is exceeded dTSEC aborts transmission due to
+ * excessive collisions. The standard specifies the
+ * attempt limit to be 15.
+ * halfdup_coll_window:
+ * The number of bytes of the frame during which
+ * collisions may occur. The default value of 55
+ * corresponds to the frame byte at the end of the
+ * standard 512-bit slot time window. If collisions are
+ * detected after this byte, the late collision event is
+ * asserted and transmission of current frame is aborted.
+ * rx_drop_bcast:
+ * Discard broadcast frames. If set, all broadcast frames
+ * will be discarded by dTSEC.
+ * rx_short_frm:
+ * Accept short frames. If set, dTSEC will accept frames
+ * of length 14..63 bytes.
+ * rx_len_check:
+ * Length check for received frames. If set, the MAC
+ * checks the frame's length field on receive to ensure it
+ * matches the actual data field length. This only works
+ * for received frames with length field less than 1500.
+ * No check is performed for larger frames.
+ * tx_pad_crc:
+ * Pad and append CRC. If set, the MAC pads all
+ * transmitted short frames and appends a CRC to every
+ * frame regardless of padding requirement.
+ * tx_crc:
+ * Transmission CRC enable. If set, the MAC appends a CRC
+ * to all frames. If frames presented to the MAC have a
+ * valid length and contain a valid CRC, tx_crc should be
+ * reset.
+ * This field is ignored if tx_pad_crc is set.
+ * rx_ctrl_acc:
+ * Control frame accept. If set, this overrides 802.3
+ * standard control frame behavior, and all Ethernet frames
+ * that have an ethertype of 0x8808 are treated as normal
+ * Ethernet frames and passed up to the packet interface on
+ * a DA match. Received pause control frames are passed to
+ * the packet interface only if Rx flow control is also
+ * disabled. See fman_dtsec_handle_rx_pause() function.
+ * tx_pause_time:
+ * Transmit pause time value. This pause value is used as
+ * part of the pause frame to be sent when a transmit pause
+ * frame is initiated. If set to 0 this disables
+ * transmission of pause frames.
+ * rx_preamble:
+ * Receive preamble enable. If set, the MAC recovers the
+ * received Ethernet 7-byte preamble and passes it to the
+ * packet interface at the start of each received frame.
+ * This field should be reset for internal MAC loop-back
+ * mode.
+ * tx_preamble: User defined preamble enable for transmitted frames.
+ * If set, a user-defined preamble must passed to the MAC
+ * and it is transmitted instead of the standard preamble.
+ * preamble_len:
+ * Length, in bytes, of the preamble field preceding each
+ * Ethernet start-of-frame delimiter byte. The default
+ * value of 0x7 should be used in order to guarantee
+ * reliable operation with IEEE 802.3 compliant hardware.
+ * rx_prepend:
+ * Packet alignment padding length. The specified number
+ * of bytes (1-31) of zero padding are inserted before the
+ * start of each received frame. For Ethernet, where
+ * optional preamble extraction is enabled, the padding
+ * appears before the preamble, otherwise the padding
+ * precedes the layer 2 header.
+ *
+ * This structure contains basic dTSEC configuration and must be passed to
+ * fman_dtsec_init() function. A default set of configuration values can be
+ * obtained by calling fman_dtsec_defconfig().
+ */
+struct dtsec_cfg {
+ bool halfdup_on;
+ bool halfdup_alt_backoff_en;
+ bool halfdup_excess_defer;
+ bool halfdup_no_backoff;
+ bool halfdup_bp_no_backoff;
+ uint8_t halfdup_alt_backoff_val;
+ uint16_t halfdup_retransmit;
+ uint16_t halfdup_coll_window;
+ bool rx_drop_bcast;
+ bool rx_short_frm;
+ bool rx_len_check;
+ bool tx_pad_crc;
+ bool tx_crc;
+ bool rx_ctrl_acc;
+ unsigned short tx_pause_time;
+ unsigned short tbipa;
+ bool ptp_tsu_en;
+ bool ptp_exception_en;
+ bool rx_preamble;
+ bool tx_preamble;
+ unsigned char preamble_len;
+ unsigned char rx_prepend;
+ bool loopback;
+ bool rx_time_stamp_en;
+ bool tx_time_stamp_en;
+ bool rx_flow;
+ bool tx_flow;
+ bool rx_group_hash_exd;
+ bool rx_promisc;
+ uint8_t tbi_phy_addr;
+ uint16_t tx_pause_time_extd;
+ uint16_t maximum_frame;
+ uint32_t non_back_to_back_ipg1;
+ uint32_t non_back_to_back_ipg2;
+ uint32_t min_ifg_enforcement;
+ uint32_t back_to_back_ipg;
+ bool wake_on_lan;
+};
+
+/*fman_dtsec_defconfig() - Get default dTSEC configuration
+ *cfg: pointer to configuration structure.
+ *
+ *Call this function to obtain a default set of configuration values for
+ *initializing dTSEC. The user can overwrite any of the values before calling
+ *fman_dtsec_init(), if specific configuration needs to be applied.
+ */
+void fman_dtsec_defconfig(struct dtsec_cfg *cfg);
+
+/*fman_dtsec_init() - Init dTSEC hardware block
+ *regs: Pointer to dTSEC register block
+ *cfg: dTSEC configuration data
+ *iface_mode: dTSEC interface mode, the type of MAC - PHY interface.
+ *iface_speed: 1G or 10G
+ *macaddr: MAC station address to be assigned to the device
+ *fm_rev_maj: major rev number
+ *fm_rev_min: minor rev number
+ *exceptions_mask: initial exceptions mask
+ *This function initializes dTSEC and applies basic configuration.
+ *
+ *dTSEC initialization sequence:
+ *Before enabling Rx/Tx call dtsec_set_address() to set MAC address,
+ *fman_dtsec_adjust_link() to configure interface speed and duplex and finally
+ *dtsec_enable_tx()/dtsec_enable_rx() to start transmission and reception.
+ *
+ *Returns: 0 if successful, an error code otherwise.
+ */
+int fman_dtsec_init(struct dtsec_regs __iomem *regs, struct dtsec_cfg *cfg,
+ enum enet_interface iface_mode,
+ enum enet_speed iface_speed,
+ uint8_t *macaddr, uint8_t fm_rev_maj,
+ uint8_t fm_rev_min, uint32_t exception_mask);
+
+/*fman_dtsec_enable() - Enable dTSEC Tx and Tx
+ *regs: Pointer to dTSEC register block
+ *apply_rx: enable rx side
+ *apply_tx: enable tx side
+ *This function resets Tx and Rx graceful stop bit and enables dTSEC Tx and Rx.
+ */
+void fman_dtsec_enable(struct dtsec_regs __iomem *regs, bool apply_rx,
+ bool apply_tx);
+
+/*fman_dtsec_disable() - Disable dTSEC Tx and Rx
+ *regs: Pointer to dTSEC register block
+ *apply_rx: disable rx side
+ *apply_tx: disable tx side
+ *This function disables Tx and Rx in dTSEC.
+ */
+void fman_dtsec_disable(struct dtsec_regs __iomem *regs, bool apply_rx,
+ bool apply_tx);
+
+/*fman_dtsec_get_revision() - Get dTSEC hardware revision
+ *regs: Pointer to dTSEC register block
+ *Returns dtsec_id content
+ *Call this function to obtain the dTSEC hardware version.
+ */
+uint32_t fman_dtsec_get_revision(struct dtsec_regs __iomem *regs);
+
+/*fman_dtsec_set_mac_address() - Set MAC station address
+ *regs: Pointer to dTSEC register block
+ *macaddr: MAC address array
+ *This function sets MAC station address. To enable unicast reception call
+ *this after fman_dtsec_init(). While promiscuous mode is disabled dTSEC will
+ *match the destination address of received unicast frames against this
+ *address.
+ */
+void fman_dtsec_set_mac_address(struct dtsec_regs __iomem *regs,
+ uint8_t *macaddr);
+
+/*fman_dtsec_get_mac_address() - Query MAC station address
+ *regs: Pointer to dTSEC register block
+ *macaddr: MAC address array
+ */
+void fman_dtsec_get_mac_address(struct dtsec_regs __iomem *regs,
+ uint8_t *macaddr);
+
+/*fman_dtsec_set_uc_promisc() - Sets unicast promiscuous mode
+ *regs: Pointer to dTSEC register block
+ *enable: Enable unicast promiscuous mode
+ *Use this function to enable/disable dTSEC L2 address filtering. If the
+ *address filtering is disabled all unicast packets are accepted.
+ *To set dTSEC in promiscuous mode call both fman_dtsec_set_uc_promisc() and
+ *fman_dtsec_set_mc_promisc() to disable filtering for both unicast and
+ *multicast addresses.
+ */
+void fman_dtsec_set_uc_promisc(struct dtsec_regs __iomem *regs, bool enable);
+
+/* fman_dtsec_set_wol() - Enable/Disable wake on lan
+ * regs: Pointer to dTSEC register block
+ * en: Enable Wake On Lan support in dTSEC
+ */
+void fman_dtsec_set_wol(struct dtsec_regs __iomem *regs, bool en);
+
+/*fman_dtsec_adjust_link() - Adjust dTSEC speed/duplex settings
+ *regs: Pointer to dTSEC register block
+ *iface_mode: dTSEC interface mode
+ *speed: Link speed
+ *full_dx: True for full-duplex, false for half-duplex.
+ *This function configures the MAC to function and the desired rates. Use it
+ *to configure dTSEC after fman_dtsec_init() and whenever the link speed
+ *changes (for instance following PHY auto-negociation).
+ *Returns: 0 if successful, an error code otherwise.
+ */
+int fman_dtsec_adjust_link(struct dtsec_regs __iomem *regs,
+ enum enet_interface iface_mode,
+ enum enet_speed speed, bool full_dx);
+
+/*fman_dtsec_set_tbi_phy_addr() - Updates TBI address field
+ *regs: Pointer to dTSEC register block
+ *address: Valid PHY address in the range of 1 to 31. 0 is reserved.
+ *In SGMII mode, the dTSEC's TBIPA field must contain a valid TBI PHY address
+ *so that the associated TBI PHY (i.e. the link) may be initialized.
+ *Returns: 0 if successful, an error code otherwise.
+ */
+int fman_dtsec_set_tbi_phy_addr(struct dtsec_regs __iomem *regs, uint8_t addr);
+
+/*fman_dtsec_set_max_frame_len() - Set max frame length
+ *regs: Pointer to dTSEC register block
+ *length: Max frame length.
+ *Sets maximum frame length for received and transmitted frames. Frames that
+ *exceeds this length are truncated.
+ */
+void fman_dtsec_set_max_frame_len(struct dtsec_regs __iomem *regs,
+ uint16_t length);
+
+/*fman_dtsec_get_max_frame_len() - Query max frame length
+ *regs: Pointer to dTSEC register block
+ *Returns: the current value of the maximum frame length.
+ */
+uint16_t fman_dtsec_get_max_frame_len(struct dtsec_regs __iomem *regs);
+
+/*fman_dtsec_handle_rx_pause() - Configure pause frame handling
+ *regs: Pointer to dTSEC register block
+ *en: Enable pause frame handling in dTSEC
+ *If enabled, dTSEC will handle pause frames internally. This must be disabled
+ *if dTSEC is set in half-duplex mode.
+ *If pause frame handling is disabled and &dtsec_cfg.rx_ctrl_acc is set, pause
+ *frames will be transferred to the packet interface just like regular Ethernet
+ *frames.
+ */
+void fman_dtsec_handle_rx_pause(struct dtsec_regs __iomem *regs, bool en);
+
+/*fman_dtsec_set_tx_pause_frames() - Configure Tx pause time
+ *regs: Pointer to dTSEC register block
+ *time: Time value included in pause frames
+ *Call this function to set the time value used in transmitted pause frames.
+ *If time is 0, transmission of pause frames is disabled
+ */
+void fman_dtsec_set_tx_pause_frames(struct dtsec_regs __iomem *regs,
+ uint16_t time);
+
+/*fman_dtsec_ack_event() - Acknowledge handled events
+ *regs: Pointer to dTSEC register block
+ *ev_mask: Events to acknowledge
+ *After handling events signaled by dTSEC in either polling or interrupt mode,
+ *call this function to reset the associated status bits in dTSEC event
+ *register.
+ */
+void fman_dtsec_ack_event(struct dtsec_regs __iomem *regs, uint32_t ev_mask);
+
+/*fman_dtsec_get_event() - Returns currently asserted events
+ *regs: Pointer to dTSEC register block
+ *ev_mask: Mask of relevant events
+ *Call this function to obtain a bit-mask of events that are currently asserted
+ *in dTSEC, taken from IEVENT register.
+ *Returns: a bit-mask of events asserted in dTSEC.
+ */
+uint32_t fman_dtsec_get_event(struct dtsec_regs __iomem *regs,
+ uint32_t ev_mask);
+
+/*fman_dtsec_get_interrupt_mask() - Returns a bit-mask of enabled interrupts
+ *regs: Pointer to dTSEC register block
+ *Call this function to obtain a bit-mask of enabled interrupts
+ *in dTSEC, taken from IMASK register.
+ *Returns: a bit-mask of enabled interrupts in dTSEC.
+ */
+uint32_t fman_dtsec_get_interrupt_mask(struct dtsec_regs __iomem *regs);
+
+void fman_dtsec_clear_addr_in_paddr(struct dtsec_regs __iomem *regs,
+ uint8_t paddr_num);
+
+void fman_dtsec_add_addr_in_paddr(struct dtsec_regs __iomem *regs,
+ uint64_t addr, uint8_t paddr_num);
+
+void fman_dtsec_enable_tmr_interrupt(struct dtsec_regs __iomem *regs);
+
+void fman_dtsec_disable_tmr_interrupt(struct dtsec_regs __iomem *regs);
+
+/*fman_dtsec_disable_interrupt() - Disables interrupts for the specified events
+ *regs: Pointer to dTSEC register block
+ *ev_mask: Mask of relevant events
+ *Call this function to disable interrupts in dTSEC for the specified events.
+ *To enable interrupts use fman_dtsec_enable_interrupt().
+ */
+void fman_dtsec_disable_interrupt(struct dtsec_regs __iomem *regs,
+ uint32_t ev_mask);
+
+/*fman_dtsec_enable_interrupt() - Enable interrupts for the specified events
+ *regs: Pointer to dTSEC register block
+ *ev_mask: Mask of relevant events
+ *Call this function to enable interrupts in dTSEC for the specified events.
+ *To disable interrupts use fman_dtsec_disable_interrupt().
+ */
+void fman_dtsec_enable_interrupt(struct dtsec_regs __iomem *regs,
+ uint32_t ev_mask);
+
+/*fman_dtsec_set_ts() - Enables dTSEC timestamps
+ *regs: Pointer to dTSEC register block
+ *en: true to enable timestamps, false to disable them
+ *Call this function to enable/disable dTSEC timestamps. This affects both
+ *Tx and Rx.
+ */
+void fman_dtsec_set_ts(struct dtsec_regs __iomem *regs, bool en);
+
+/*fman_dtsec_set_bucket() - Enables/disables a filter bucket
+ *regs: Pointer to dTSEC register block
+ *bucket: Bucket index
+ *enable: true/false to enable/disable this bucket
+ *This function enables or disables the specified bucket. Enabling a bucket
+ *associated with an address configures dTSEC to accept received packets
+ *with that destination address.
+ *Multiple addresses may be associated with the same bucket. Disabling a
+ *bucket will affect all addresses associated with that bucket. A bucket that
+ *is enabled requires further filtering and verification in the upper layers
+ */
+void fman_dtsec_set_bucket(struct dtsec_regs __iomem *regs, int bucket,
+ bool enable);
+
+/*dtsec_set_hash_table() - insert a crc code into thr filter table
+ *regs: Pointer to dTSEC register block
+ *crc: crc to insert
+ *mcast: true is this is a multicast address
+ *ghtx: true if we are in ghtx mode
+ *This function inserts a crc code into the filter table.
+ */
+void fman_dtsec_set_hash_table(struct dtsec_regs __iomem *regs, uint32_t crc,
+ bool mcast, bool ghtx);
+
+/*fman_dtsec_reset_filter_table() - Resets the address filtering table
+ *regs: Pointer to dTSEC register block
+ *mcast: Reset multicast entries
+ *ucast: Reset unicast entries
+ *Resets all entries in L2 address filter table. After calling this function
+ *all buckets enabled using fman_dtsec_set_bucket() will be disabled.
+ *If dtsec_init_filter_table() was called with unicast_hash set to false,
+ *ucast argument is ignored.
+ *This does not affect the primary nor the 15 additional addresses configured
+ *using dtsec_set_address() or dtsec_set_match_address().
+ */
+void fman_dtsec_reset_filter_table(struct dtsec_regs __iomem *regs, bool mcast,
+ bool ucast);
+
+/*fman_dtsec_set_mc_promisc() - Set multicast promiscuous mode
+ *regs: Pointer to dTSEC register block
+ *enable: Enable multicast promiscuous mode
+ *Call this to enable/disable L2 address filtering for multicast packets.
+ */
+void fman_dtsec_set_mc_promisc(struct dtsec_regs __iomem *regs, bool enable);
+
+/* statistics APIs */
+
+/*fman_dtsec_set_stat_level() - Enable a group of MIB statistics counters
+ *regs: Pointer to dTSEC register block
+ *level: Specifies a certain group of dTSEC MIB HW counters or _all_,
+ * to specify all the existing counters.
+ * If set to _none_, it disables all the counters.
+ *Enables the MIB statistics hw counters and sets up the carry interrupt
+ *masks for the counters corresponding to the level input parameter.
+ *Returns: error if invalid level value given.
+ */
+int fman_dtsec_set_stat_level(struct dtsec_regs __iomem *regs,
+ enum dtsec_stat_level level);
+
+/*fman_dtsec_reset_stat() - Completely resets all dTSEC HW counters
+ *regs: Pointer to dTSEC register block
+ */
+void fman_dtsec_reset_stat(struct dtsec_regs __iomem *regs);
+
+/*fman_dtsec_get_clear_carry_regs() - Read and clear carry bits
+ * (CAR1-2 registers)
+ *regs: Pointer to dTSEC register block
+ *car1: car1 register value
+ *car2: car2 register value
+ *When set, the carry bits signal that an overflow occurred on the
+ *corresponding counters.
+ *Note that the carry bits (CAR1-2 registers) will assert the
+ *%DTSEC_IEVENT_MSRO interrupt if unmasked (via CAM1-2 regs).
+ *Returns: true if overflow occurred, otherwise - false
+ */
+bool fman_dtsec_get_clear_carry_regs(struct dtsec_regs __iomem *regs,
+ uint32_t *car1, uint32_t *car2);
+
+uint32_t fman_dtsec_check_and_clear_tmr_event(struct dtsec_regs __iomem *regs);
+
+uint32_t fman_dtsec_get_stat_counter(struct dtsec_regs __iomem *regs,
+ enum dtsec_stat_counters reg_name);
+
+void fman_dtsec_start_tx(struct dtsec_regs __iomem *regs);
+void fman_dtsec_start_rx(struct dtsec_regs __iomem *regs);
+void fman_dtsec_stop_tx(struct dtsec_regs __iomem *regs);
+void fman_dtsec_stop_rx(struct dtsec_regs __iomem *regs);
+uint32_t fman_dtsec_get_rctrl(struct dtsec_regs __iomem *regs);
+
+#endif /* __FSL_FMAN_DTSEC_H */
diff --git a/drivers/soc/fsl/fman/flib/fsl_fman_dtsec_mii_acc.h b/drivers/soc/fsl/fman/flib/fsl_fman_dtsec_mii_acc.h
new file mode 100644
index 0000000..cd8f521
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fsl_fman_dtsec_mii_acc.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FMAN_DTSEC_MII_ACC_H
+#define __FSL_FMAN_DTSEC_MII_ACC_H
+
+#include "common/general.h"
+
+/* MII Management Configuration Register */
+#define MIIMCFG_RESET_MGMT 0x80000000
+#define MIIMCFG_MGNTCLK_MASK 0x00000007
+#define MIIMCFG_MGNTCLK_SHIFT 0
+
+/* MII Management Command Register */
+#define MIIMCOM_SCAN_CYCLE 0x00000002
+#define MIIMCOM_READ_CYCLE 0x00000001
+
+/* MII Management Address Register */
+#define MIIMADD_PHY_ADDR_SHIFT 8
+#define MIIMADD_PHY_ADDR_MASK 0x00001f00
+
+#define MIIMADD_REG_ADDR_SHIFT 0
+#define MIIMADD_REG_ADDR_MASK 0x0000001f
+
+/* MII Management Indicator Register */
+#define MIIMIND_BUSY 0x00000001
+
+/* PHY Control Register */
+#define PHY_CR_PHY_RESET 0x8000
+#define PHY_CR_LOOPBACK 0x4000
+#define PHY_CR_SPEED0 0x2000
+#define PHY_CR_ANE 0x1000
+#define PHY_CR_RESET_AN 0x0200
+#define PHY_CR_FULLDUPLEX 0x0100
+#define PHY_CR_SPEED1 0x0040
+
+#define PHY_TBICON_SRESET 0x8000
+#define PHY_TBICON_SPEED2 0x0020
+#define PHY_TBICON_CLK_SEL 0x0020
+#define PHY_TBIANA_SGMII 0x4001
+#define PHY_TBIANA_1000X 0x01a0
+/* register map */
+
+/* MII Configuration Control Memory Map Registers */
+struct dtsec_mii_reg {
+ uint32_t reserved1[72];
+ uint32_t miimcfg; /* MII Mgmt:configuration */
+ uint32_t miimcom; /* MII Mgmt:command */
+ uint32_t miimadd; /* MII Mgmt:address */
+ uint32_t miimcon; /* MII Mgmt:control 3 */
+ uint32_t miimstat; /* MII Mgmt:status */
+ uint32_t miimind; /* MII Mgmt:indicators */
+};
+
+/* dTSEC MII API */
+
+/* functions to access the mii registers for phy configuration.
+ * this functionality may not be available for all dtsecs in the system.
+ * consult the reference manual for details
+ **/
+void fman_dtsec_mii_reset(struct dtsec_mii_reg __iomem *regs);
+/* frequency is in MHz.
+ * note that dtsec clock is 1/2 of fman clock
+ **/
+void fman_dtsec_mii_init(struct dtsec_mii_reg __iomem *regs,
+ uint16_t dtsec_freq);
+int fman_dtsec_mii_write_reg(struct dtsec_mii_reg __iomem *regs,
+ uint8_t addr,
+ uint8_t reg, uint16_t data, uint16_t dtsec_freq);
+
+int fman_dtsec_mii_read_reg(struct dtsec_mii_reg __iomem *regs,
+ uint8_t addr,
+ uint8_t reg, uint16_t *data, uint16_t dtsec_freq);
+
+#endif /* __FSL_FMAN_DTSEC_MII_ACC_H */
diff --git a/drivers/soc/fsl/fman/flib/fsl_fman_kg.h b/drivers/soc/fsl/fman/flib/fsl_fman_kg.h
new file mode 100644
index 0000000..967ca81
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fsl_fman_kg.h
@@ -0,0 +1,506 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FMAN_KG_H
+#define __FSL_FMAN_KG_H
+
+#include "common/general.h"
+
+#define FM_KG_NUM_OF_GENERIC_REGS 8 /* Num of generic KeyGen regs */
+#define FMAN_MAX_NUM_OF_HW_PORTS 64
+/* Total num of masks allowed on KG extractions */
+#define FM_KG_EXTRACT_MASKS_NUM 4
+#define FM_KG_NUM_CLS_PLAN_ENTR 8 /* Num of class. plan regs */
+#define FM_KG_CLS_PLAN_GRPS_NUM 32 /* Max num of class. groups */
+
+struct fman_kg_regs {
+ uint32_t fmkg_gcr;
+ uint32_t res004;
+ uint32_t res008;
+ uint32_t fmkg_eer;
+ uint32_t fmkg_eeer;
+ uint32_t res014;
+ uint32_t res018;
+ uint32_t fmkg_seer;
+ uint32_t fmkg_seeer;
+ uint32_t fmkg_gsr;
+ uint32_t fmkg_tpc;
+ uint32_t fmkg_serc;
+ uint32_t res030[4];
+ uint32_t fmkg_fdor;
+ uint32_t fmkg_gdv0r;
+ uint32_t fmkg_gdv1r;
+ uint32_t res04c[6];
+ uint32_t fmkg_feer;
+ uint32_t res068[38];
+ uint32_t fmkg_indirect[63];
+ uint32_t fmkg_ar;
+};
+
+struct fman_kg_scheme_regs {
+ uint32_t kgse_mode; /* MODE */
+ uint32_t kgse_ekfc; /* Extract Known Fields Command */
+ uint32_t kgse_ekdv; /* Extract Known Default Value */
+ uint32_t kgse_bmch; /* Bit Mask Command High */
+ uint32_t kgse_bmcl; /* Bit Mask Command Low */
+ uint32_t kgse_fqb; /* Frame Queue Base */
+ uint32_t kgse_hc; /* Hash Command */
+ uint32_t kgse_ppc; /* Policer Profile Command */
+ uint32_t kgse_gec[FM_KG_NUM_OF_GENERIC_REGS];
+ /* Generic Extract Command */
+ uint32_t kgse_spc; /* KeyGen Scheme Entry Statistic Packet Counter */
+ uint32_t kgse_dv0; /* KeyGen Scheme Entry Default Value 0 */
+ uint32_t kgse_dv1; /* KeyGen Scheme Entry Default Value 1 */
+ uint32_t kgse_ccbs; /* KeyGen Scheme Entry Coarse Classification Bit*/
+ uint32_t kgse_mv; /* KeyGen Scheme Entry Match vector */
+ uint32_t kgse_om; /* KeyGen Scheme Entry Operation Mode bits */
+ uint32_t kgse_vsp; /* KeyGen Scheme Entry Virtual Storage Profile */
+};
+
+struct fman_kg_pe_regs {
+ uint32_t fmkg_pe_sp;
+ uint32_t fmkg_pe_cpp;
+};
+
+struct fman_kg_cp_regs {
+ uint32_t kgcpe[FM_KG_NUM_CLS_PLAN_ENTR];
+};
+
+#define FM_KG_KGAR_GO 0x80000000
+#define FM_KG_KGAR_READ 0x40000000
+#define FM_KG_KGAR_WRITE 0x00000000
+#define FM_KG_KGAR_SEL_SCHEME_ENTRY 0x00000000
+#define FM_KG_KGAR_SCM_WSEL_UPDATE_CNT 0x00008000
+
+#define KG_SCH_PP_SHIFT_HIGH 0x80000000
+#define KG_SCH_PP_NO_GEN 0x10000000
+#define KG_SCH_PP_SHIFT_LOW 0x0000F000
+#define KG_SCH_MODE_NIA_PLCR 0x40000000
+#define KG_SCH_GEN_EXTRACT_TYPE 0x00008000
+#define KG_SCH_BITMASK_MASK 0x000000FF
+#define KG_SCH_GEN_VALID 0x80000000
+#define KG_SCH_GEN_MASK 0x00FF0000
+#define FM_PCD_KG_KGAR_ERR 0x20000000
+#define FM_PCD_KG_KGAR_SEL_CLS_PLAN_ENTRY 0x01000000
+#define FM_PCD_KG_KGAR_SEL_PORT_ENTRY 0x02000000
+#define FM_PCD_KG_KGAR_SEL_PORT_WSEL_SP 0x00008000
+#define FM_PCD_KG_KGAR_SEL_PORT_WSEL_CPP 0x00004000
+#define FM_PCD_KG_KGAR_WSEL_MASK 0x0000FF00
+#define KG_SCH_HASH_CONFIG_NO_FQID 0x80000000
+#define KG_SCH_HASH_CONFIG_SYM 0x40000000
+
+#define FM_EX_KG_DOUBLE_ECC 0x80000000
+#define FM_EX_KG_KEYSIZE_OVERFLOW 0x40000000
+
+/* ECC capture register */
+#define KG_FMKG_SERC_CAP 0x80000000
+#define KG_FMKG_SERC_CET 0x40000000
+#define KG_FMKG_SERC_CNT_MSK 0x00FF0000
+#define KG_FMKG_SERC_CNT_SHIFT 16
+#define KG_FMKG_SERC_ADDR_MSK 0x000003FF
+
+/* Masks */
+#define FM_KG_KGGCR_EN 0x80000000
+#define KG_SCH_GEN_VALID 0x80000000
+#define KG_SCH_GEN_EXTRACT_TYPE 0x00008000
+#define KG_ERR_TYPE_DOUBLE 0x40000000
+#define KG_ERR_ADDR_MASK 0x00000FFF
+#define KG_SCH_MODE_EN 0x80000000
+
+/* shifts */
+#define FM_KG_KGAR_NUM_SHIFT 16
+#define FM_KG_PE_CPP_MASK_SHIFT 16
+#define FM_KG_KGAR_WSEL_SHIFT 8
+
+#define FM_KG_SCH_GEN_HT_INVALID 0
+
+#define FM_KG_MASK_SEL_GEN_BASE 0x20
+
+#define KG_GET_MASK_SEL_SHIFT(shift, i) do {\
+switch (i) { \
+case 0: \
+ (shift) = 26; \
+ break; \
+case 1: \
+ (shift) = 20; break; \
+case 2: \
+ (shift) = 10; break; \
+case 3: \
+ (shift) = 4; break; \
+default: \
+ (shift) = 0; \
+} \
+} while (0)
+
+#define KG_GET_MASK_OFFSET_SHIFT(shift, i) do {\
+switch (i) { \
+case 0: \
+ (shift) = 16; break; \
+case 1: \
+ (shift) = 0; break; \
+case 2: \
+ (shift) = 28; break; \
+case 3: \
+ (shift) = 24; break; \
+default: \
+ (shift) = 0; \
+} \
+} while (0)
+
+#define KG_GET_MASK_SHIFT(shift, i) do {\
+switch (i) { \
+case 0: \
+ shift = 24; break; \
+case 1: \
+ shift = 16; break; \
+case 2: \
+ shift = 8; break; \
+case 3: \
+ shift = 0; break; \
+default: \
+ shift = 0; \
+} \
+} while (0)
+
+/* Port entry CPP register */
+#define FMAN_KG_PE_CPP_MASK_SHIFT 16
+
+/* Scheme registers */
+#define FMAN_KG_SCH_MODE_EN 0x80000000
+#define FMAN_KG_SCH_MODE_NIA_PLCR 0x40000000
+#define FMAN_KG_SCH_MODE_CCOBASE_SHIFT 24
+
+#define FMAN_KG_SCH_DEF_MAC_ADDR_SHIFT 30
+#define FMAN_KG_SCH_DEF_VLAN_TCI_SHIFT 28
+#define FMAN_KG_SCH_DEF_ETYPE_SHIFT 26
+#define FMAN_KG_SCH_DEF_PPP_SID_SHIFT 24
+#define FMAN_KG_SCH_DEF_PPP_PID_SHIFT 22
+#define FMAN_KG_SCH_DEF_MPLS_SHIFT 20
+#define FMAN_KG_SCH_DEF_IP_ADDR_SHIFT 18
+#define FMAN_KG_SCH_DEF_PTYPE_SHIFT 16
+#define FMAN_KG_SCH_DEF_IP_TOS_TC_SHIFT 14
+#define FMAN_KG_SCH_DEF_IPV6_FL_SHIFT 12
+#define FMAN_KG_SCH_DEF_IPSEC_SPI_SHIFT 10
+#define FMAN_KG_SCH_DEF_L4_PORT_SHIFT 8
+#define FMAN_KG_SCH_DEF_TCP_FLG_SHIFT 6
+
+#define FMAN_KG_SCH_GEN_VALID 0x80000000
+#define FMAN_KG_SCH_GEN_SIZE_MAX 16
+#define FMAN_KG_SCH_GEN_OR 0x00008000
+
+#define FMAN_KG_SCH_GEN_DEF_SHIFT 29
+#define FMAN_KG_SCH_GEN_SIZE_SHIFT 24
+#define FMAN_KG_SCH_GEN_MASK_SHIFT 16
+#define FMAN_KG_SCH_GEN_HT_SHIFT 8
+
+#define FMAN_KG_SCH_HASH_HSHIFT_SHIFT 24
+#define FMAN_KG_SCH_HASH_HSHIFT_MAX 0x28
+#define FMAN_KG_SCH_HASH_SYM 0x40000000
+#define FMAN_KG_SCH_HASH_NO_FQID_GEN 0x80000000
+
+#define FMAN_KG_SCH_PP_SH_SHIFT 27
+#define FMAN_KG_SCH_PP_SL_SHIFT 12
+#define FMAN_KG_SCH_PP_SH_MASK 0x80000000
+#define FMAN_KG_SCH_PP_SL_MASK 0x0000F000
+#define FMAN_KG_SCH_PP_SHIFT_MAX 0x17
+#define FMAN_KG_SCH_PP_MASK_SHIFT 16
+#define FMAN_KG_SCH_PP_NO_GEN 0x10000000
+
+enum fman_kg_gen_extract_src {
+ E_FMAN_KG_GEN_EXTRACT_ETH,
+ E_FMAN_KG_GEN_EXTRACT_ETYPE,
+ E_FMAN_KG_GEN_EXTRACT_SNAP,
+ E_FMAN_KG_GEN_EXTRACT_VLAN_TCI_1,
+ E_FMAN_KG_GEN_EXTRACT_VLAN_TCI_N,
+ E_FMAN_KG_GEN_EXTRACT_PPPOE,
+ E_FMAN_KG_GEN_EXTRACT_MPLS_1,
+ E_FMAN_KG_GEN_EXTRACT_MPLS_2,
+ E_FMAN_KG_GEN_EXTRACT_MPLS_3,
+ E_FMAN_KG_GEN_EXTRACT_MPLS_N,
+ E_FMAN_KG_GEN_EXTRACT_IPV4_1,
+ E_FMAN_KG_GEN_EXTRACT_IPV6_1,
+ E_FMAN_KG_GEN_EXTRACT_IPV4_2,
+ E_FMAN_KG_GEN_EXTRACT_IPV6_2,
+ E_FMAN_KG_GEN_EXTRACT_MINENCAP,
+ E_FMAN_KG_GEN_EXTRACT_IP_PID,
+ E_FMAN_KG_GEN_EXTRACT_GRE,
+ E_FMAN_KG_GEN_EXTRACT_TCP,
+ E_FMAN_KG_GEN_EXTRACT_UDP,
+ E_FMAN_KG_GEN_EXTRACT_SCTP,
+ E_FMAN_KG_GEN_EXTRACT_DCCP,
+ E_FMAN_KG_GEN_EXTRACT_IPSEC_AH,
+ E_FMAN_KG_GEN_EXTRACT_IPSEC_ESP,
+ E_FMAN_KG_GEN_EXTRACT_SHIM_1,
+ E_FMAN_KG_GEN_EXTRACT_SHIM_2,
+ E_FMAN_KG_GEN_EXTRACT_FROM_DFLT,
+ E_FMAN_KG_GEN_EXTRACT_FROM_FRAME_START,
+ E_FMAN_KG_GEN_EXTRACT_FROM_PARSE_RESULT,
+ E_FMAN_KG_GEN_EXTRACT_FROM_END_OF_PARSE,
+ E_FMAN_KG_GEN_EXTRACT_FROM_FQID
+};
+
+struct fman_kg_ex_ecc_attr {
+ bool valid;
+ bool double_ecc;
+ uint16_t addr;
+ uint8_t single_ecc_count;
+};
+
+enum fman_kg_def_select {
+ E_FMAN_KG_DEF_GLOBAL_0,
+ E_FMAN_KG_DEF_GLOBAL_1,
+ E_FMAN_KG_DEF_SCHEME_0,
+ E_FMAN_KG_DEF_SCHEME_1
+};
+
+struct fman_kg_extract_def {
+ enum fman_kg_def_select mac_addr;
+ enum fman_kg_def_select vlan_tci;
+ enum fman_kg_def_select etype;
+ enum fman_kg_def_select ppp_sid;
+ enum fman_kg_def_select ppp_pid;
+ enum fman_kg_def_select mpls;
+ enum fman_kg_def_select ip_addr;
+ enum fman_kg_def_select ptype;
+ enum fman_kg_def_select ip_tos_tc;
+ enum fman_kg_def_select ipv6_fl;
+ enum fman_kg_def_select ipsec_spi;
+ enum fman_kg_def_select l4_port;
+ enum fman_kg_def_select tcp_flg;
+};
+
+enum fman_kg_gen_extract_type {
+ E_FMAN_KG_HASH_EXTRACT,
+ E_FMAN_KG_OR_EXTRACT
+};
+
+struct fman_kg_gen_extract_params {
+ /* Hash or Or-ed extract */
+ enum fman_kg_gen_extract_type type;
+ enum fman_kg_gen_extract_src src;
+ bool no_validation;
+ /* Extraction offset from the header location specified above */
+ uint8_t offset;
+ /* Size of extraction for FMAN_KG_HASH_EXTRACT,
+ * hash result shift for FMAN_KG_OR_EXTRACT
+ */
+ uint8_t extract;
+ uint8_t mask;
+ /* Default value to use when header specified
+ * by fman_kg_gen_extract_src doesn't present
+ */
+ enum fman_kg_def_select def_val;
+};
+
+struct fman_kg_extract_mask {
+ /* Indication if mask is on known field extraction or
+ * on general extraction; true for known field
+ */
+ bool is_known;
+ /* One of FMAN_KG_EXTRACT_xxx defines for known fields mask and
+ * generic register index for generic extracts mask
+ */
+ uint32_t field_or_gen_idx;
+ /* Byte offset from start of the extracted data specified
+ * by field_or_gen_idx
+ */
+ uint8_t offset;
+ /* Byte mask (selected bits will be used) */
+ uint8_t mask;
+};
+
+struct fman_kg_extract_params {
+ /* Or-ed mask of FMAN_KG_EXTRACT_xxx defines */
+ uint32_t known_fields;
+ struct fman_kg_extract_def known_fields_def;
+ /* Number of entries in gen_extract */
+ uint8_t gen_extract_num;
+ struct fman_kg_gen_extract_params
+ gen_extract[FM_KG_NUM_OF_GENERIC_REGS];
+ /* Number of entries in masks */
+ uint8_t masks_num;
+ struct fman_kg_extract_mask masks[FM_KG_EXTRACT_MASKS_NUM];
+ uint32_t def_scheme_0;
+ uint32_t def_scheme_1;
+};
+
+struct fman_kg_hash_params {
+ bool use_hash;
+ uint8_t shift_r;
+ uint32_t mask; /* 24-bit mask */
+ bool sym; /* Symmetric hash for src and dest pairs */
+};
+
+struct fman_kg_pp_params {
+ uint8_t base;
+ uint8_t shift;
+ uint8_t mask;
+ bool bypass_pp_gen;
+};
+
+struct fman_kg_cc_params {
+ uint8_t base_offset;
+ uint32_t qlcv_bits_sel;
+};
+
+enum fman_pcd_engine {
+ E_FMAN_PCD_INVALID = 0, /* Invalid PCD engine indicated*/
+ E_FMAN_PCD_DONE, /* No PCD Engine indicated */
+ E_FMAN_PCD_KG, /* Keygen indicated */
+ E_FMAN_PCD_CC, /* Coarse classification indicated */
+ E_FMAN_PCD_PLCR, /* Policer indicated */
+ E_FMAN_PCD_PRS /* Parser indicated */
+};
+
+struct fman_kg_cls_plan_params {
+ uint8_t entries_mask;
+ uint32_t mask_vector[FM_KG_NUM_CLS_PLAN_ENTR];
+};
+
+struct fman_kg_scheme_params {
+ uint32_t match_vector;
+ struct fman_kg_extract_params extract_params;
+ struct fman_kg_hash_params hash_params;
+ uint32_t base_fqid;
+ /* What we do w/features supported per FM version ?? */
+ bool bypass_fqid_gen;
+ struct fman_kg_pp_params policer_params;
+ struct fman_kg_cc_params cc_params;
+ bool update_counter;
+ /* counter_value: Set scheme counter to the specified value;
+ * relevant only when update_counter = true.
+ */
+ uint32_t counter_value;
+ enum fman_pcd_engine next_engine;
+ /* Next engine action code */
+ uint32_t next_engine_action;
+};
+
+int fman_kg_write_ar_wait(struct fman_kg_regs __iomem *regs, uint32_t fmkg_ar);
+void fman_kg_write_sp(struct fman_kg_regs __iomem *regs, uint32_t sp, bool add);
+void fman_kg_write_cpp(struct fman_kg_regs __iomem *regs, uint32_t cpp);
+void fman_kg_get_event(struct fman_kg_regs __iomem *regs,
+ uint32_t *event, uint32_t *scheme_idx);
+void fman_kg_init(struct fman_kg_regs __iomem *regs,
+ uint32_t exceptions, uint32_t dflt_nia);
+void fman_kg_enable_scheme_interrupts(struct fman_kg_regs __iomem *regs);
+void fman_kg_enable(struct fman_kg_regs __iomem *regs);
+void fman_kg_disable(struct fman_kg_regs __iomem *regs);
+int fman_kg_write_bind_cls_plans(struct fman_kg_regs __iomem *regs,
+ uint8_t hwport_id, uint32_t bind_cls_plans);
+int fman_kg_build_bind_cls_plans(uint8_t grp_base,
+ uint8_t grp_mask, uint32_t *bind_cls_plans);
+int fman_kg_write_bind_schemes(struct fman_kg_regs __iomem *regs,
+ uint8_t hwport_id, uint32_t schemes);
+int fman_kg_write_cls_plan(struct fman_kg_regs __iomem *regs,
+ uint8_t grp_id,
+ uint8_t entries_mask,
+ uint8_t hwport_id,
+ struct fman_kg_cp_regs __iomem *cls_plan_regs);
+int fman_kg_build_cls_plan(struct fman_kg_cls_plan_params *params,
+ struct fman_kg_cp_regs *cls_plan_regs);
+uint32_t fman_kg_get_schemes_total_counter(struct fman_kg_regs __iomem *regs);
+int fman_kg_set_scheme_counter(struct fman_kg_regs __iomem *regs,
+ uint8_t scheme_id,
+ uint8_t hwport_id, uint32_t counter);
+int fman_kg_get_scheme_counter(struct fman_kg_regs __iomem *regs,
+ uint8_t scheme_id,
+ uint8_t hwport_id, uint32_t *counter);
+int fman_kg_delete_scheme(struct fman_kg_regs __iomem *regs,
+ uint8_t scheme_id, uint8_t hwport_id);
+int fman_kg_write_scheme(struct fman_kg_regs __iomem *regs,
+ uint8_t scheme_id,
+ uint8_t hwport_id,
+ struct fman_kg_scheme_regs *scheme_regs,
+ bool update_counter);
+int fman_kg_build_scheme(struct fman_kg_scheme_params *params,
+ struct fman_kg_scheme_regs *scheme_regs);
+void fman_kg_get_capture(struct fman_kg_regs __iomem *regs,
+ struct fman_kg_ex_ecc_attr *ecc_attr, bool clear);
+void fman_kg_get_exception(struct fman_kg_regs __iomem *regs,
+ uint32_t *events,
+ uint32_t *scheme_ids, bool clear);
+void fman_kg_set_exception(struct fman_kg_regs __iomem *regs,
+ uint32_t exception, bool enable);
+void fman_kg_set_dflt_val(struct fman_kg_regs __iomem *regs,
+ uint8_t def_id, uint32_t val);
+void fman_kg_set_data_after_prs(struct fman_kg_regs __iomem *regs,
+ uint8_t offset);
+
+/* NIA Description */
+#define KG_NIA_ORDER_RESTOR 0x00800000
+#define KG_NIA_ENG_FM_CTL 0x00000000
+#define KG_NIA_ENG_PRS 0x00440000
+#define KG_NIA_ENG_KG 0x00480000
+#define KG_NIA_ENG_PLCR 0x004C0000
+#define KG_NIA_ENG_BMI 0x00500000
+#define KG_NIA_ENG_QMI_ENQ 0x00540000
+#define KG_NIA_ENG_QMI_DEQ 0x00580000
+#define KG_NIA_ENG_MASK 0x007C0000
+
+#define KG_NIA_AC_MASK 0x0003FFFF
+
+#define KG_NIA_INVALID 0xFFFFFFFF
+
+static inline uint32_t fm_kg_build_nia(enum fman_pcd_engine next_engine,
+ uint32_t next_engine_action)
+{
+ uint32_t nia;
+
+ if (next_engine_action & ~KG_NIA_AC_MASK)
+ return KG_NIA_INVALID;
+
+ switch (next_engine) {
+ case E_FMAN_PCD_DONE:
+ nia = KG_NIA_ENG_BMI | next_engine_action;
+ break;
+
+ case E_FMAN_PCD_KG:
+ nia = KG_NIA_ENG_KG | next_engine_action;
+ break;
+
+ case E_FMAN_PCD_CC:
+ nia = KG_NIA_ENG_FM_CTL | next_engine_action;
+ break;
+
+ case E_FMAN_PCD_PLCR:
+ nia = KG_NIA_ENG_PLCR | next_engine_action;
+ break;
+
+ default:
+ nia = KG_NIA_INVALID;
+ }
+
+ return nia;
+}
+
+#endif /* __FSL_FMAN_KG_H */
diff --git a/drivers/soc/fsl/fman/flib/fsl_fman_memac.h b/drivers/soc/fsl/fman/flib/fsl_fman_memac.h
new file mode 100644
index 0000000..bb64103
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fsl_fman_memac.h
@@ -0,0 +1,492 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FMAN_MEMAC_H
+#define __FSL_FMAN_MEMAC_H
+
+#include "common/general.h"
+#include "fsl_enet.h"
+/* Num of additional exact match MAC adr regs */
+#define MEMAC_NUM_OF_PADDRS 7
+
+/* Control and Configuration Register (COMMAND_CONFIG) */
+/* 00 Magic Packet detection */
+#define CMD_CFG_MG 0x80000000
+/* 07 Rx low power indication */
+#define CMD_CFG_REG_LOWP_RXETY 0x01000000
+/* 08 Tx Low Power Idle Enable */
+#define CMD_CFG_TX_LOWP_ENA 0x00800000
+/* 10 Disable SFD check */
+#define CMD_CFG_SFD_ANY 0x00200000
+/* 12 Enable PFC */
+#define CMD_CFG_PFC_MODE 0x00080000
+/* 14 Payload length check disable */
+#define CMD_CFG_NO_LEN_CHK 0x00020000
+/* 15 Force idle generation */
+#define CMD_CFG_SEND_IDLE 0x00010000
+/* 18 Control frame rx enable */
+#define CMD_CFG_CNT_FRM_EN 0x00002000
+/* 19 S/W Reset, self clearing bit */
+#define CMD_CFG_SW_RESET 0x00001000
+/* 20 Enable Tx padding of frames */
+#define CMD_CFG_TX_PAD_EN 0x00000800
+/* 21 XGMII/GMII loopback enable */
+#define CMD_CFG_LOOPBACK_EN 0x00000400
+/* 22 Tx source MAC addr insertion */
+#define CMD_CFG_TX_ADDR_INS 0x00000200
+/* 23 Ignore Pause frame quanta */
+#define CMD_CFG_PAUSE_IGNORE 0x00000100
+/* 24 Terminate/frwd Pause frames */
+#define CMD_CFG_PAUSE_FWD 0x00000080
+/* 25 Terminate/frwd CRC of frames */
+#define CMD_CFG_CRC_FWD 0x00000040
+/* 26 Frame padding removal */
+#define CMD_CFG_PAD_EN 0x00000020
+/* 27 Promiscuous operation enable */
+#define CMD_CFG_PROMIS_EN 0x00000010
+/* 28 WAN mode enable */
+#define CMD_CFG_WAN_MODE 0x00000008
+/* 30 MAC receive path enable */
+#define CMD_CFG_RX_EN 0x00000002
+/* 31 MAC transmit path enable */
+#define CMD_CFG_TX_EN 0x00000001
+
+/* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */
+#define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000
+#define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF
+#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000
+#define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000
+#define TX_FIFO_SECTIONS_TX_EMPTY_PFC_10G 0x00360000
+#define TX_FIFO_SECTIONS_TX_EMPTY_PFC_1G 0x00040000
+#define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019
+#define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020
+
+#define GET_TX_EMPTY_DEFAULT_VALUE(_val) \
+do { \
+ _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \
+ ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \
+ (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\
+ (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\
+} while (0)
+
+#define GET_TX_EMPTY_PFC_VALUE(_val) \
+do { \
+ _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \
+ ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \
+ (_val |= TX_FIFO_SECTIONS_TX_EMPTY_PFC_10G) : \
+ (_val |= TX_FIFO_SECTIONS_TX_EMPTY_PFC_1G)); \
+} while (0)
+
+/* Interface Mode Register (IF_MODE) */
+/* 30-31 Mask on i/f mode bits */
+#define IF_MODE_MASK 0x00000003
+/* 30-31 XGMII (10G) interface */
+#define IF_MODE_XGMII 0x00000000
+/* 30-31 GMII (1G) interface */
+#define IF_MODE_GMII 0x00000002
+#define IF_MODE_RGMII 0x00000004
+#define IF_MODE_RGMII_AUTO 0x00008000
+#define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
+#define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
+#define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */
+#define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */
+#define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */
+#define IF_MODE_HD 0x00000040 /* Half duplex operation */
+
+/* Hash table Control Register (HASHTABLE_CTRL) */
+#define HASH_CTRL_MCAST_SHIFT 26
+/* 23 Mcast frame rx for hash */
+#define HASH_CTRL_MCAST_EN 0x00000100
+/* 26-31 Hash table address code */
+#define HASH_CTRL_ADDR_MASK 0x0000003F
+/* MAC mcast indication */
+#define GROUP_ADDRESS 0x0000010000000000LL
+#define HASH_TABLE_SIZE 64 /* Hash tbl size */
+
+/* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */
+#define MEMAC_TX_IPG_LENGTH_MASK 0x0000003F
+
+/* Statistics Configuration Register (STATN_CONFIG) */
+#define STATS_CFG_CLR 0x00000004 /* 29 Reset all counters */
+#define STATS_CFG_CLR_ON_RD 0x00000002 /* 30 Clear on read */
+/* 31 Saturate at the maximum val */
+#define STATS_CFG_SATURATE 0x00000001
+
+/* Interrupt Mask Register (IMASK) */
+/* 1 Magic pkt detect indication */
+#define MEMAC_IMASK_MGI 0x40000000
+/* 2 Timestamp FIFO ECC error evnt */
+#define MEMAC_IMASK_TSECC_ER 0x20000000
+/* 6 Transmit frame ECC error evnt */
+#define MEMAC_IMASK_TECC_ER 0x02000000
+/* 7 Receive frame ECC error evnt */
+#define MEMAC_IMASK_RECC_ER 0x01000000
+
+#define MEMAC_ALL_ERRS_IMASK \
+ ((uint32_t)(MEMAC_IMASK_TSECC_ER | \
+ MEMAC_IMASK_TECC_ER | \
+ MEMAC_IMASK_RECC_ER | \
+ MEMAC_IMASK_MGI))
+
+/* PCS (XG). Link sync (G) */
+#define MEMAC_IEVNT_PCS 0x80000000
+/* Auto-negotiation */
+#define MEMAC_IEVNT_AN 0x40000000
+/* Link Training/New page */
+#define MEMAC_IEVNT_LT 0x20000000
+/* Magic pkt detection */
+#define MEMAC_IEVNT_MGI 0x00004000
+/* Timestamp FIFO ECC error */
+#define MEMAC_IEVNT_TS_ECC_ER 0x00002000
+/* Rx FIFO overflow */
+#define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000
+/* Tx FIFO underflow */
+#define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800
+/* Tx FIFO overflow */
+#define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400
+/* Tx frame ECC error */
+#define MEMAC_IEVNT_TX_ECC_ER 0x00000200
+/* Rx frame ECC error */
+#define MEMAC_IEVNT_RX_ECC_ER 0x00000100
+/* Link Interruption flt */
+#define MEMAC_IEVNT_LI_FAULT 0x00000080
+/* Rx FIFO empty */
+#define MEMAC_IEVNT_RX_EMPTY 0x00000040
+/* Tx FIFO empty */
+#define MEMAC_IEVNT_TX_EMPTY 0x00000020
+/* Low Power Idle */
+#define MEMAC_IEVNT_RX_LOWP 0x00000010
+/* Phy loss of signal */
+#define MEMAC_IEVNT_PHY_LOS 0x00000004
+/* Remote fault (XGMII) */
+#define MEMAC_IEVNT_REM_FAULT 0x00000002
+/* Local fault (XGMII) */
+#define MEMAC_IEVNT_LOC_FAULT 0x00000001
+
+enum memac_counters {
+ E_MEMAC_COUNTER_R64,
+ E_MEMAC_COUNTER_R127,
+ E_MEMAC_COUNTER_R255,
+ E_MEMAC_COUNTER_R511,
+ E_MEMAC_COUNTER_R1023,
+ E_MEMAC_COUNTER_R1518,
+ E_MEMAC_COUNTER_R1519X,
+ E_MEMAC_COUNTER_RFRG,
+ E_MEMAC_COUNTER_RJBR,
+ E_MEMAC_COUNTER_RDRP,
+ E_MEMAC_COUNTER_RALN,
+ E_MEMAC_COUNTER_TUND,
+ E_MEMAC_COUNTER_ROVR,
+ E_MEMAC_COUNTER_RXPF,
+ E_MEMAC_COUNTER_TXPF,
+ E_MEMAC_COUNTER_ROCT,
+ E_MEMAC_COUNTER_RMCA,
+ E_MEMAC_COUNTER_RBCA,
+ E_MEMAC_COUNTER_RPKT,
+ E_MEMAC_COUNTER_RUCA,
+ E_MEMAC_COUNTER_RERR,
+ E_MEMAC_COUNTER_TOCT,
+ E_MEMAC_COUNTER_TMCA,
+ E_MEMAC_COUNTER_TBCA,
+ E_MEMAC_COUNTER_TUCA,
+ E_MEMAC_COUNTER_TERR
+};
+
+#define DEFAULT_PAUSE_QUANTA 0xf000
+#define DEFAULT_FRAME_LENGTH 0x600
+#define DEFAULT_TX_IPG_LENGTH 12
+
+/**
+ * memory map
+ **/
+
+struct mac_addr {
+ /* Lower 32 bits of 48-bit MAC address */
+ uint32_t mac_addr_l;
+ /* Upper 16 bits of 48-bit MAC address */
+ uint32_t mac_addr_u;
+};
+
+struct memac_regs {
+ /* General Control and Status */
+ uint32_t res0000[2];
+ /* 0x008 Ctrl and cfg */
+ uint32_t command_config;
+ /* 0x00C-0x010 MAC_ADDR_0...1 */
+ struct mac_addr mac_addr0;
+ /* 0x014 Max frame length */
+ uint32_t maxfrm;
+ uint32_t res0018[1];
+ /* Receive FIFO configuration reg */
+ uint32_t rx_fifo_sections;
+ /* Transmit FIFO configuration reg */
+ uint32_t tx_fifo_sections;
+ uint32_t res0024[2];
+ /* 0x02C Hash table control */
+ uint32_t hashtable_ctrl;
+ uint32_t res0030[4];
+ /* 0x040 Interrupt event */
+ uint32_t ievent;
+ /* 0x044 Transmitter inter-packet-gap */
+ uint32_t tx_ipg_length;
+ uint32_t res0048;
+ /* 0x04C Interrupt mask */
+ uint32_t imask;
+ uint32_t res0050;
+ /* 0x054 Pause quanta */
+ uint32_t pause_quanta[4];
+ /* 0x064 Pause quanta threshold */
+ uint32_t pause_thresh[4];
+ /* 0x074 Receive pause status */
+ uint32_t rx_pause_status;
+ uint32_t res0078[2];
+ /* 0x80-0x0B4 mac padr */
+ struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];
+ /* 0x0B8 Low Power Wakeup Timer */
+ uint32_t lpwake_timer;
+ /* 0x0BC Transmit EEE Low Power Timer */
+ uint32_t sleep_timer;
+ uint32_t res00c0[8];
+ /* 0x0E0 Statistics configuration */
+ uint32_t statn_config;
+ uint32_t res00e4[7];
+ /* Rx Statistics Counter */
+ uint32_t reoct_l;
+ uint32_t reoct_u;
+ uint32_t roct_l;
+ uint32_t roct_u;
+ uint32_t raln_l;
+ uint32_t raln_u;
+ uint32_t rxpf_l;
+ uint32_t rxpf_u;
+ uint32_t rfrm_l;
+ uint32_t rfrm_u;
+ uint32_t rfcs_l;
+ uint32_t rfcs_u;
+ uint32_t rvlan_l;
+ uint32_t rvlan_u;
+ uint32_t rerr_l;
+ uint32_t rerr_u;
+ uint32_t ruca_l;
+ uint32_t ruca_u;
+ uint32_t rmca_l;
+ uint32_t rmca_u;
+ uint32_t rbca_l;
+ uint32_t rbca_u;
+ uint32_t rdrp_l;
+ uint32_t rdrp_u;
+ uint32_t rpkt_l;
+ uint32_t rpkt_u;
+ uint32_t rund_l;
+ uint32_t rund_u;
+ uint32_t r64_l;
+ uint32_t r64_u;
+ uint32_t r127_l;
+ uint32_t r127_u;
+ uint32_t r255_l;
+ uint32_t r255_u;
+ uint32_t r511_l;
+ uint32_t r511_u;
+ uint32_t r1023_l;
+ uint32_t r1023_u;
+ uint32_t r1518_l;
+ uint32_t r1518_u;
+ uint32_t r1519x_l;
+ uint32_t r1519x_u;
+ uint32_t rovr_l;
+ uint32_t rovr_u;
+ uint32_t rjbr_l;
+ uint32_t rjbr_u;
+ uint32_t rfrg_l;
+ uint32_t rfrg_u;
+ uint32_t rcnp_l;
+ uint32_t rcnp_u;
+ uint32_t rdrntp_l;
+ uint32_t rdrntp_u;
+ uint32_t res01d0[12];
+ /* Tx Statistics Counter */
+ uint32_t teoct_l;
+ uint32_t teoct_u;
+ uint32_t toct_l;
+ uint32_t toct_u;
+ uint32_t res0210[2];
+ uint32_t txpf_l;
+ uint32_t txpf_u;
+ uint32_t tfrm_l;
+ uint32_t tfrm_u;
+ uint32_t tfcs_l;
+ uint32_t tfcs_u;
+ uint32_t tvlan_l;
+ uint32_t tvlan_u;
+ uint32_t terr_l;
+ uint32_t terr_u;
+ uint32_t tuca_l;
+ uint32_t tuca_u;
+ uint32_t tmca_l;
+ uint32_t tmca_u;
+ uint32_t tbca_l;
+ uint32_t tbca_u;
+ uint32_t res0258[2];
+ uint32_t tpkt_l;
+ uint32_t tpkt_u;
+ uint32_t tund_l;
+ uint32_t tund_u;
+ uint32_t t64_l;
+ uint32_t t64_u;
+ uint32_t t127_l;
+ uint32_t t127_u;
+ uint32_t t255_l;
+ uint32_t t255_u;
+ uint32_t t511_l;
+ uint32_t t511_u;
+ uint32_t t1023_l;
+ uint32_t t1023_u;
+ uint32_t t1518_l;
+ uint32_t t1518_u;
+ uint32_t t1519x_l;
+ uint32_t t1519x_u;
+ uint32_t res02a8[6];
+ uint32_t tcnp_l;
+ uint32_t tcnp_u;
+ uint32_t res02c8[14];
+ /* Line Interface Control */
+ uint32_t if_mode; /* 0x300 Interface Mode Control */
+ uint32_t if_status; /* 0x304 Interface Status */
+ uint32_t res0308[14];
+ /* HiGig/2 */
+ uint32_t hg_config; /* 0x340 Control and cfg */
+ uint32_t res0344[3];
+ uint32_t hg_pause_quanta; /* 0x350 Pause quanta */
+ uint32_t res0354[3];
+ uint32_t hg_pause_thresh; /* 0x360 Pause quanta threshold */
+ uint32_t res0364[3];
+ uint32_t hgrx_pause_status; /* 0x370 Receive pause status */
+ uint32_t hg_fifos_status; /* 0x374 fifos status */
+ uint32_t rhm; /* 0x378 rx messages counter */
+ uint32_t thm; /* 0x37C tx messages counter */
+};
+
+struct memac_cfg {
+ bool reset_on_init;
+ bool rx_error_discard;
+ bool pause_ignore;
+ bool pause_forward_enable;
+ bool no_length_check_enable;
+ bool cmd_frame_enable;
+ bool send_idle_enable;
+ bool wan_mode_enable;
+ bool promiscuous_mode_enable;
+ bool tx_addr_ins_enable;
+ bool loopback_enable;
+ bool lgth_check_nostdr;
+ bool time_stamp_enable;
+ bool pad_enable;
+ bool phy_tx_ena_on;
+ bool rx_sfd_any;
+ bool rx_pbl_fwd;
+ bool tx_pbl_fwd;
+ bool debug_mode;
+ bool wake_on_lan;
+ uint16_t max_frame_length;
+ uint16_t pause_quanta;
+ uint32_t tx_ipg_length;
+};
+
+/**
+*fman_memac_defconfig() - Get default MEMAC configuration
+*@cfg: pointer to configuration structure.
+ *
+*Call this function to obtain a default set of configuration values for
+*initializing MEMAC. The user can overwrite any of the values before calling
+*fman_memac_init(), if specific configuration needs to be applied.
+ */
+void fman_memac_defconfig(struct memac_cfg *cfg);
+
+int fman_memac_init(struct memac_regs __iomem *regs,
+ struct memac_cfg *cfg,
+ enum enet_interface enet_interface,
+ enum enet_speed enet_speed, uint32_t exceptions);
+
+void fman_memac_enable(struct memac_regs __iomem *regs, bool apply_rx,
+ bool apply_tx);
+
+void fman_memac_disable(struct memac_regs __iomem *regs, bool apply_rx,
+ bool apply_tx);
+
+void fman_memac_set_promiscuous(struct memac_regs __iomem *regs, bool val);
+
+void fman_memac_add_addr_in_paddr(struct memac_regs __iomem *regs,
+ uint8_t *adr, uint8_t paddr_num);
+
+void fman_memac_clear_addr_in_paddr(struct memac_regs __iomem *regs,
+ uint8_t paddr_num);
+
+uint64_t fman_memac_get_counter(struct memac_regs __iomem *regs,
+ enum memac_counters reg_name);
+
+void fman_memac_set_tx_pause_frames(struct memac_regs __iomem *regs,
+ uint8_t priority, uint16_t pause_time,
+ uint16_t thresh_time);
+
+uint16_t fman_memac_get_max_frame_len(struct memac_regs __iomem *regs);
+
+void fman_memac_set_exception(struct memac_regs __iomem *regs, uint32_t val,
+ bool enable);
+
+void fman_memac_reset_stat(struct memac_regs __iomem *regs);
+
+void fman_memac_reset(struct memac_regs __iomem *regs);
+
+void fman_memac_reset_filter_table(struct memac_regs __iomem *regs);
+
+void fman_memac_set_hash_table_entry(struct memac_regs __iomem *regs,
+ uint32_t crc);
+
+void fman_memac_set_hash_table(struct memac_regs __iomem *regs, uint32_t val);
+
+void fman_memac_set_rx_ignore_pause_frames(struct memac_regs __iomem *regs,
+ bool enable);
+
+void fman_memac_set_wol(struct memac_regs __iomem *regs, bool enable);
+
+uint32_t fman_memac_get_event(struct memac_regs __iomem *regs,
+ uint32_t ev_mask);
+
+void fman_memac_ack_event(struct memac_regs __iomem *regs, uint32_t ev_mask);
+
+uint32_t fman_memac_get_interrupt_mask(struct memac_regs __iomem *regs);
+
+void fman_memac_adjust_link(struct memac_regs __iomem *regs,
+ enum enet_interface iface_mode,
+ enum enet_speed speed, bool full_dx);
+
+#endif /*__FSL_FMAN_MEMAC_H*/
diff --git a/drivers/soc/fsl/fman/flib/fsl_fman_memac_mii_acc.h b/drivers/soc/fsl/fman/flib/fsl_fman_memac_mii_acc.h
new file mode 100644
index 0000000..2efd2a0
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fsl_fman_memac_mii_acc.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FMAN_MEMAC_MII_ACC_H
+#define __FSL_FMAN_MEMAC_MII_ACC_H
+
+#include "common/general.h"
+#include "fsl_enet.h"
+/* MII Management Registers */
+#define MDIO_CFG_CLK_DIV_MASK 0x0080ff80
+#define MDIO_CFG_HOLD_MASK 0x0000001c
+#define MDIO_CFG_ENC45 0x00000040
+#define MDIO_CFG_READ_ERR 0x00000002
+#define MDIO_CFG_BSY 0x00000001
+
+#define MDIO_CTL_PHY_ADDR_SHIFT 5
+#define MDIO_CTL_READ 0x00008000
+
+#define MDIO_DATA_BSY 0x80000000
+
+/*MEMAC Internal PHY Registers - SGMII */
+#define PHY_SGMII_CR_PHY_RESET 0x8000
+#define PHY_SGMII_CR_RESET_AN 0x0200
+#define PHY_SGMII_CR_DEF_VAL 0x1140
+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
+#define PHY_SGMII_DEV_ABILITY_1000X 0x01A0
+#define PHY_SGMII_IF_MODE_AN 0x0002
+#define PHY_SGMII_IF_MODE_SGMII 0x0001
+#define PHY_SGMII_IF_MODE_1000X 0x0000
+
+/*----------------------------------------------------*/
+/* MII Configuration Control Memory Map Registers */
+/*----------------------------------------------------*/
+struct memac_mii_access_mem_map {
+ uint32_t mdio_cfg; /* 0x030 */
+ uint32_t mdio_ctrl; /* 0x034 */
+ uint32_t mdio_data; /* 0x038 */
+ uint32_t mdio_addr; /* 0x03c */
+};
+
+int fman_memac_mii_read_phy_reg(struct memac_mii_access_mem_map __iomem
+ *mii_regs, uint8_t phy_addr, uint8_t reg,
+ uint16_t *data, enum enet_speed enet_speed);
+int fman_memac_mii_write_phy_reg(struct memac_mii_access_mem_map __iomem
+ *mii_regs, uint8_t phy_addr, uint8_t reg,
+ uint16_t data, enum enet_speed enet_speed);
+
+#endif /* __MAC_API_MEMAC_MII_ACC_H */
diff --git a/drivers/soc/fsl/fman/flib/fsl_fman_port.h b/drivers/soc/fsl/fman/flib/fsl_fman_port.h
new file mode 100644
index 0000000..d9568e0
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fsl_fman_port.h
@@ -0,0 +1,602 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FMAN_PORT_H
+#define __FSL_FMAN_PORT_H
+
+#include "fsl_fman_sp.h"
+
+/* Registers bit fields */
+
+/* BMI defines */
+#define BMI_EBD_EN 0x80000000
+
+#define BMI_PORT_CFG_EN 0x80000000
+#define BMI_PORT_CFG_FDOVR 0x02000000
+#define BMI_PORT_CFG_IM 0x01000000
+
+#define BMI_PORT_STATUS_BSY 0x80000000
+
+#define BMI_DMA_ATTR_SWP_SHIFT FMAN_SP_DMA_ATTR_SWP_SHIFT
+#define BMI_DMA_ATTR_IC_STASH_ON 0x10000000
+#define BMI_DMA_ATTR_HDR_STASH_ON 0x04000000
+#define BMI_DMA_ATTR_SG_STASH_ON 0x01000000
+#define BMI_DMA_ATTR_WRITE_OPTIMIZE FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE
+
+#define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16
+#define BMI_RX_FIFO_THRESHOLD_ETHE 0x80000000
+
+#define BMI_TX_FRAME_END_CS_IGNORE_SHIFT 24
+#define BMI_RX_FRAME_END_CS_IGNORE_SHIFT 24
+#define BMI_RX_FRAME_END_CUT_SHIFT 16
+
+#define BMI_IC_TO_EXT_SHIFT FMAN_SP_IC_TO_EXT_SHIFT
+#define BMI_IC_FROM_INT_SHIFT FMAN_SP_IC_FROM_INT_SHIFT
+
+#define BMI_INT_BUF_MARG_SHIFT 28
+#define BMI_EXT_BUF_MARG_START_SHIFT FMAN_SP_EXT_BUF_MARG_START_SHIFT
+
+#define BMI_CMD_MR_LEAC 0x00200000
+#define BMI_CMD_MR_SLEAC 0x00100000
+#define BMI_CMD_MR_MA 0x00080000
+#define BMI_CMD_MR_DEAS 0x00040000
+#define BMI_CMD_RX_MR_DEF (BMI_CMD_MR_LEAC | \
+ BMI_CMD_MR_SLEAC | \
+ BMI_CMD_MR_MA | \
+ BMI_CMD_MR_DEAS)
+#define BMI_CMD_TX_MR_DEF 0
+#define BMI_CMD_OP_MR_DEF (BMI_CMD_MR_DEAS | \
+ BMI_CMD_MR_MA)
+
+#define BMI_CMD_ATTR_ORDER 0x80000000
+#define BMI_CMD_ATTR_SYNC 0x02000000
+#define BMI_CMD_ATTR_COLOR_SHIFT 26
+
+#define BMI_FIFO_PIPELINE_DEPTH_SHIFT 12
+#define BMI_NEXT_ENG_FD_BITS_SHIFT 24
+#define BMI_FRAME_END_CS_IGNORE_SHIFT 24
+
+#define BMI_COUNTERS_EN 0x80000000
+
+#define BMI_EXT_BUF_POOL_VALID FMAN_SP_EXT_BUF_POOL_VALID
+#define BMI_EXT_BUF_POOL_EN_COUNTER FMAN_SP_EXT_BUF_POOL_EN_COUNTER
+#define BMI_EXT_BUF_POOL_BACKUP FMAN_SP_EXT_BUF_POOL_BACKUP
+#define BMI_EXT_BUF_POOL_ID_SHIFT 16
+#define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000
+#define BMI_POOL_DEP_NUM_OF_POOLS_SHIFT 16
+
+#define BMI_TX_FIFO_MIN_FILL_SHIFT 16
+#define BMI_TX_FIFO_PIPELINE_DEPTH_SHIFT 12
+
+#define MAX_PERFORMANCE_TASK_COMP 64
+#define MAX_PERFORMANCE_RX_QUEUE_COMP 64
+#define MAX_PERFORMANCE_TX_QUEUE_COMP 8
+#define MAX_PERFORMANCE_DMA_COMP 16
+#define MAX_PERFORMANCE_FIFO_COMP 1024
+
+#define BMI_PERFORMANCE_TASK_COMP_SHIFT 24
+#define BMI_PERFORMANCE_QUEUE_COMP_SHIFT 16
+#define BMI_PERFORMANCE_DMA_COMP_SHIFT 12
+
+#define BMI_RATE_LIMIT_GRAN_TX 16000 /* In Kbps */
+#define BMI_RATE_LIMIT_GRAN_OP 10000 /* In frames */
+#define BMI_RATE_LIMIT_MAX_RATE_IN_GRAN_UNITS 1024
+#define BMI_RATE_LIMIT_MAX_BURST_SIZE 1024 /* In KBytes */
+#define BMI_RATE_LIMIT_MAX_BURST_SHIFT 16
+#define BMI_RATE_LIMIT_HIGH_BURST_SIZE_GRAN 0x80000000
+#define BMI_RATE_LIMIT_SCALE_TSBS_SHIFT 16
+#define BMI_RATE_LIMIT_SCALE_EN 0x80000000
+#define BMI_SG_DISABLE FMAN_SP_SG_DISABLE
+
+/* QMI defines */
+#define QMI_PORT_CFG_EN 0x80000000
+#define QMI_PORT_CFG_EN_COUNTERS 0x10000000
+
+#define QMI_PORT_STATUS_DEQ_TNUM_BSY 0x80000000
+#define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000
+
+#define QMI_DEQ_CFG_PRI 0x80000000
+#define QMI_DEQ_CFG_TYPE1 0x10000000
+#define QMI_DEQ_CFG_TYPE2 0x20000000
+#define QMI_DEQ_CFG_TYPE3 0x30000000
+#define QMI_DEQ_CFG_PREFETCH_PARTIAL 0x01000000
+#define QMI_DEQ_CFG_PREFETCH_FULL 0x03000000
+#define QMI_DEQ_CFG_SP_MASK 0xf
+#define QMI_DEQ_CFG_SP_SHIFT 20
+
+/* General port defines */
+#define FMAN_PORT_EXT_POOLS_NUM(fm_rev_maj) \
+ (((fm_rev_maj) == 4) ? 4 : 8)
+#define FMAN_PORT_MAX_EXT_POOLS_NUM 8
+#define FMAN_PORT_OBS_EXT_POOLS_NUM 2
+#define FMAN_PORT_CG_MAP_NUM 8
+#define FMAN_PORT_PRS_RESULT_WORDS_NUM 8
+#define FMAN_PORT_BMI_FIFO_UNITS 0x100
+#define FMAN_PORT_IC_OFFSET_UNITS 0x10
+
+/* FM Port Register Map */
+
+/* BMI Rx port register map */
+struct fman_port_rx_bmi_regs {
+ uint32_t fmbm_rcfg; /* Rx Configuration */
+ uint32_t fmbm_rst; /* Rx Status */
+ uint32_t fmbm_rda; /* Rx DMA attributes*/
+ uint32_t fmbm_rfp; /* Rx FIFO Parameters*/
+ uint32_t fmbm_rfed; /* Rx Frame End Data*/
+ uint32_t fmbm_ricp; /* Rx Internal Context Parameters*/
+ uint32_t fmbm_rim; /* Rx Internal Buffer Margins*/
+ uint32_t fmbm_rebm; /* Rx External Buffer Margins*/
+ uint32_t fmbm_rfne; /* Rx Frame Next Engine*/
+ uint32_t fmbm_rfca; /* Rx Frame Command Attributes.*/
+ uint32_t fmbm_rfpne; /* Rx Frame Parser Next Engine*/
+ uint32_t fmbm_rpso; /* Rx Parse Start Offset*/
+ uint32_t fmbm_rpp; /* Rx Policer Profile */
+ uint32_t fmbm_rccb; /* Rx Coarse Classification Base */
+ uint32_t fmbm_reth; /* Rx Excessive Threshold */
+ uint32_t reserved003c[1]; /* (0x03C 0x03F) */
+ uint32_t fmbm_rprai[FMAN_PORT_PRS_RESULT_WORDS_NUM];
+ /* Rx Parse Results Array Init*/
+ uint32_t fmbm_rfqid; /* Rx Frame Queue ID*/
+ uint32_t fmbm_refqid; /* Rx Error Frame Queue ID*/
+ uint32_t fmbm_rfsdm; /* Rx Frame Status Discard Mask*/
+ uint32_t fmbm_rfsem; /* Rx Frame Status Error Mask*/
+ uint32_t fmbm_rfene; /* Rx Frame Enqueue Next Engine */
+ uint32_t reserved0074[0x2]; /* (0x074-0x07C) */
+ uint32_t fmbm_rcmne; /* Rx Frame Continuous Mode Next Engine */
+ uint32_t reserved0080[0x20];/* (0x080 0x0FF) */
+ uint32_t fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM];
+ /* Buffer Manager pool Information-*/
+ uint32_t fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM];
+ /* Allocate Counter-*/
+ uint32_t reserved0130[8];
+ /* 0x130/0x140 - 0x15F reserved -*/
+ uint32_t fmbm_rcgm[FMAN_PORT_CG_MAP_NUM];
+ /* Congestion Group Map*/
+ uint32_t fmbm_mpd; /* BM Pool Depletion */
+ uint32_t reserved0184[0x1F]; /* (0x184 0x1FF) */
+ uint32_t fmbm_rstc; /* Rx Statistics Counters*/
+ uint32_t fmbm_rfrc; /* Rx Frame Counter*/
+ uint32_t fmbm_rfbc; /* Rx Bad Frames Counter*/
+ uint32_t fmbm_rlfc; /* Rx Large Frames Counter*/
+ uint32_t fmbm_rffc; /* Rx Filter Frames Counter*/
+ uint32_t fmbm_rfdc; /* Rx Frame Discard Counter*/
+ uint32_t fmbm_rfldec; /* Rx Frames List DMA Error Counter*/
+ uint32_t fmbm_rodc; /* Rx Out of Buffers Discard nntr*/
+ uint32_t fmbm_rbdc; /* Rx Buffers Deallocate Counter*/
+ uint32_t reserved0224[0x17]; /* (0x224 0x27F) */
+ uint32_t fmbm_rpc; /* Rx Performance Counters*/
+ uint32_t fmbm_rpcp; /* Rx Performance Count Parameters*/
+ uint32_t fmbm_rccn; /* Rx Cycle Counter*/
+ uint32_t fmbm_rtuc; /* Rx Tasks Utilization Counter*/
+ uint32_t fmbm_rrquc; /* Rx Receive Queue Utilization cntr*/
+ uint32_t fmbm_rduc; /* Rx DMA Utilization Counter*/
+ uint32_t fmbm_rfuc; /* Rx FIFO Utilization Counter*/
+ uint32_t fmbm_rpac; /* Rx Pause Activation Counter*/
+ uint32_t reserved02a0[0x18]; /* (0x2A0 0x2FF) */
+ uint32_t fmbm_rdbg; /* Rx Debug-*/
+};
+
+/* BMI Tx port register map */
+struct fman_port_tx_bmi_regs {
+ uint32_t fmbm_tcfg; /* Tx Configuration */
+ uint32_t fmbm_tst; /* Tx Status */
+ uint32_t fmbm_tda; /* Tx DMA attributes */
+ uint32_t fmbm_tfp; /* Tx FIFO Parameters */
+ uint32_t fmbm_tfed; /* Tx Frame End Data */
+ uint32_t fmbm_ticp; /* Tx Internal Context Parameters */
+ uint32_t fmbm_tfdne; /* Tx Frame Dequeue Next Engine. */
+ uint32_t fmbm_tfca; /* Tx Frame Command attribute. */
+ uint32_t fmbm_tcfqid; /* Tx Confirmation Frame Queue ID. */
+ uint32_t fmbm_tefqid; /* Tx Frame Error Queue ID */
+ uint32_t fmbm_tfene; /* Tx Frame Enqueue Next Engine */
+ uint32_t fmbm_trlmts; /* Tx Rate Limiter Scale */
+ uint32_t fmbm_trlmt; /* Tx Rate Limiter */
+ uint32_t reserved0034[0x0e]; /* (0x034-0x6c) */
+ uint32_t fmbm_tccb; /* Tx Coarse Classification base */
+ uint32_t fmbm_tfne; /* Tx Frame Next Engine */
+ /* Tx Priority based Flow Control (PFC) Mapping */
+ uint32_t fmbm_tpfcm[0x02];
+ /* Tx Frame Continuous Mode Next Engine */
+ uint32_t fmbm_tcmne;
+ uint32_t reserved0080[0x60]; /* (0x080-0x200) */
+ uint32_t fmbm_tstc; /* Tx Statistics Counters */
+ uint32_t fmbm_tfrc; /* Tx Frame Counter */
+ uint32_t fmbm_tfdc; /* Tx Frames Discard Counter */
+ uint32_t fmbm_tfledc; /* Tx Frame len error discard cntr */
+ uint32_t fmbm_tfufdc; /* Tx Frame unsprt frmt discard cntr*/
+ uint32_t fmbm_tbdc; /* Tx Buffers Deallocate Counter */
+ uint32_t reserved0218[0x1A]; /* (0x218-0x280) */
+ uint32_t fmbm_tpc; /* Tx Performance Counters*/
+ uint32_t fmbm_tpcp; /* Tx Performance Count Parameters*/
+ uint32_t fmbm_tccn; /* Tx Cycle Counter*/
+ uint32_t fmbm_ttuc; /* Tx Tasks Utilization Counter*/
+ uint32_t fmbm_ttcquc; /* Tx Transmit conf Q util Counter*/
+ uint32_t fmbm_tduc; /* Tx DMA Utilization Counter*/
+ uint32_t fmbm_tfuc; /* Tx FIFO Utilization Counter*/
+};
+
+/* BMI O/H port register map */
+struct fman_port_oh_bmi_regs {
+ uint32_t fmbm_ocfg; /* O/H Configuration */
+ uint32_t fmbm_ost; /* O/H Status */
+ uint32_t fmbm_oda; /* O/H DMA attributes */
+ uint32_t fmbm_oicp; /* O/H Internal Context Parameters */
+ uint32_t fmbm_ofdne; /* O/H Frame Dequeue Next Engine */
+ uint32_t fmbm_ofne; /* O/H Frame Next Engine */
+ uint32_t fmbm_ofca; /* O/H Frame Command Attributes. */
+ uint32_t fmbm_ofpne; /* O/H Frame Parser Next Engine */
+ uint32_t fmbm_opso; /* O/H Parse Start Offset */
+ uint32_t fmbm_opp; /* O/H Policer Profile */
+ uint32_t fmbm_occb; /* O/H Coarse Classification base */
+ uint32_t fmbm_oim; /* O/H Internal margins*/
+ uint32_t fmbm_ofp; /* O/H Fifo Parameters*/
+ uint32_t fmbm_ofed; /* O/H Frame End Data*/
+ uint32_t reserved0030[2]; /* (0x038 - 0x03F) */
+ uint32_t fmbm_oprai[FMAN_PORT_PRS_RESULT_WORDS_NUM];
+ /* O/H Parse Results Array Initialization */
+ uint32_t fmbm_ofqid; /* O/H Frame Queue ID */
+ uint32_t fmbm_oefqid; /* O/H Error Frame Queue ID */
+ uint32_t fmbm_ofsdm; /* O/H Frame Status Discard Mask */
+ uint32_t fmbm_ofsem; /* O/H Frame Status Error Mask */
+ uint32_t fmbm_ofene; /* O/H Frame Enqueue Next Engine */
+ uint32_t fmbm_orlmts; /* O/H Rate Limiter Scale */
+ uint32_t fmbm_orlmt; /* O/H Rate Limiter */
+ uint32_t fmbm_ocmne; /* O/H Continuous Mode Next Engine */
+ uint32_t reserved0080[0x20]; /* 0x080 - 0x0FF Reserved */
+ uint32_t fmbm_oebmpi[2]; /* Buf Mngr Observed Pool Info */
+ uint32_t reserved0108[0x16]; /* 0x108 - 0x15F Reserved */
+ uint32_t fmbm_ocgm; /* Observed Congestion Group Map */
+ uint32_t reserved0164[0x7]; /* 0x164 - 0x17F Reserved */
+ uint32_t fmbm_ompd; /* Observed BMan Pool Depletion */
+ uint32_t reserved0184[0x1F]; /* 0x184 - 0x1FF Reserved */
+ uint32_t fmbm_ostc; /* O/H Statistics Counters */
+ uint32_t fmbm_ofrc; /* O/H Frame Counter */
+ uint32_t fmbm_ofdc; /* O/H Frames Discard Counter */
+ uint32_t fmbm_ofledc; /* O/H Frames Len Err Discard Cntr */
+ uint32_t fmbm_ofufdc; /* O/H Frames Unsprtd Discard Cutr */
+ uint32_t fmbm_offc; /* O/H Filter Frames Counter */
+ uint32_t fmbm_ofwdc; /* Rx Frames WRED Discard Counter */
+ uint32_t fmbm_ofldec; /* O/H Frames List DMA Error Cntr */
+ uint32_t fmbm_obdc; /* O/H Buffers Deallocate Counter */
+ uint32_t reserved0218[0x17]; /* (0x218 - 0x27F) */
+ uint32_t fmbm_opc; /* O/H Performance Counters */
+ uint32_t fmbm_opcp; /* O/H Performance Count Parameters */
+ uint32_t fmbm_occn; /* O/H Cycle Counter */
+ uint32_t fmbm_otuc; /* O/H Tasks Utilization Counter */
+ uint32_t fmbm_oduc; /* O/H DMA Utilization Counter */
+ uint32_t fmbm_ofuc; /* O/H FIFO Utilization Counter */
+};
+
+/* BMI port register map */
+union fman_port_bmi_regs {
+ struct fman_port_rx_bmi_regs rx;
+ struct fman_port_tx_bmi_regs tx;
+ struct fman_port_oh_bmi_regs oh;
+};
+
+/* QMI port register map */
+struct fman_port_qmi_regs {
+ uint32_t fmqm_pnc; /* PortID n Configuration Register */
+ uint32_t fmqm_pns; /* PortID n Status Register */
+ uint32_t fmqm_pnts; /* PortID n Task Status Register */
+ uint32_t reserved00c[4]; /* 0xn00C - 0xn01B */
+ uint32_t fmqm_pnen; /* PortID n Enqueue NIA Register */
+ uint32_t fmqm_pnetfc; /* PortID n Enq Total Frame Counter */
+ uint32_t reserved024[2]; /* 0xn024 - 0x02B */
+ uint32_t fmqm_pndn; /* PortID n Dequeue NIA Register */
+ uint32_t fmqm_pndc; /* PortID n Dequeue Config Register */
+ uint32_t fmqm_pndtfc; /* PortID n Dequeue tot Frame cntr */
+ uint32_t fmqm_pndfdc; /* PortID n Dequeue FQID Dflt Cntr */
+ uint32_t fmqm_pndcc; /* PortID n Dequeue Confirm Counter */
+};
+
+enum fman_port_dma_swap {
+ E_FMAN_PORT_DMA_NO_SWAP, /* No swap, transfer data as is */
+ E_FMAN_PORT_DMA_SWAP_LE,
+ /* The transferred data should be swapped in PPC Little Endian mode */
+ E_FMAN_PORT_DMA_SWAP_BE
+ /* The transferred data should be swapped in Big Endian mode */
+};
+
+/* Default port color */
+enum fman_port_color {
+ E_FMAN_PORT_COLOR_GREEN, /* Default port color is green */
+ E_FMAN_PORT_COLOR_YELLOW, /* Default port color is yellow */
+ E_FMAN_PORT_COLOR_RED, /* Default port color is red */
+ E_FMAN_PORT_COLOR_OVERRIDE /* Ignore color */
+};
+
+/* QMI dequeue from the SP channel - types */
+enum fman_port_deq_type {
+ E_FMAN_PORT_DEQ_BY_PRI,
+ /* Priority precedence and Intra-Class scheduling */
+ E_FMAN_PORT_DEQ_ACTIVE_FQ,
+ /* Active FQ precedence and Intra-Class scheduling */
+ E_FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS
+ /* Active FQ precedence and override Intra-Class scheduling */
+};
+
+/* QMI dequeue prefetch modes */
+enum fman_port_deq_prefetch {
+ E_FMAN_PORT_DEQ_NO_PREFETCH, /* No prefetch mode */
+ E_FMAN_PORT_DEQ_PART_PREFETCH, /* Partial prefetch mode */
+ E_FMAN_PORT_DEQ_FULL_PREFETCH /* Full prefetch mode */
+};
+
+/* Parameters for defining performance counters behavior */
+struct fman_port_perf_cnt_params {
+ uint8_t task_val; /* Task compare value */
+ uint8_t queue_val;
+ /* Rx or Tx conf queue compare value (unused for O/H ports) */
+ uint8_t dma_val; /* Dma compare value */
+ uint32_t fifo_val; /* Fifo compare value (in bytes) */
+};
+
+/* FM Port configuration structure, used at init */
+struct fman_port_cfg {
+ struct fman_port_perf_cnt_params perf_cnt_params;
+ /* BMI parameters */
+ enum fman_port_dma_swap dma_swap_data;
+ bool dma_ic_stash_on;
+ bool dma_header_stash_on;
+ bool dma_sg_stash_on;
+ bool dma_write_optimize;
+ uint16_t ic_ext_offset;
+ uint8_t ic_int_offset;
+ uint16_t ic_size;
+ enum fman_port_color color;
+ bool sync_req;
+ bool discard_override;
+ uint8_t checksum_bytes_ignore;
+ uint8_t rx_cut_end_bytes;
+ uint32_t rx_pri_elevation;
+ uint32_t rx_fifo_thr;
+ uint8_t rx_fd_bits;
+ uint8_t int_buf_start_margin;
+ uint16_t ext_buf_start_margin;
+ uint16_t ext_buf_end_margin;
+ uint32_t tx_fifo_min_level;
+ uint32_t tx_fifo_low_comf_level;
+ uint8_t tx_fifo_deq_pipeline_depth;
+ bool stats_counters_enable;
+ bool perf_counters_enable;
+ /* QMI parameters */
+ bool deq_high_pri;
+ enum fman_port_deq_type deq_type;
+ enum fman_port_deq_prefetch deq_prefetch_opt;
+ uint16_t deq_byte_cnt;
+ bool queue_counters_enable;
+ bool no_scatter_gather;
+ int errata_A006675;
+ int errata_A006320;
+ int excessive_threshold_register;
+ int fmbm_rebm_has_sgd;
+ int fmbm_tfne_has_features;
+ int qmi_deq_options_support;
+};
+
+enum fman_port_type {
+ E_FMAN_PORT_TYPE_OP = 0,
+ /* Offline parsing port, shares id-s with
+ * host command, so must have exclusive id-s
+ */
+ E_FMAN_PORT_TYPE_RX, /* 1G Rx port */
+ E_FMAN_PORT_TYPE_RX_10G, /* 10G Rx port */
+ E_FMAN_PORT_TYPE_TX, /* 1G Tx port */
+ E_FMAN_PORT_TYPE_TX_10G, /* 10G Tx port */
+ E_FMAN_PORT_TYPE_DUMMY,
+ E_FMAN_PORT_TYPE_HC = E_FMAN_PORT_TYPE_DUMMY
+ /* Host command port, shares id-s with
+ * offline parsing ports, so must have exclusive id-s
+ */
+};
+
+struct fman_port_params {
+ uint32_t discard_mask;
+ uint32_t err_mask;
+ uint32_t dflt_fqid;
+ uint32_t err_fqid;
+ uint8_t deq_sp;
+ bool dont_release_buf;
+};
+
+/* Port context - used by most API functions */
+struct fman_port {
+ enum fman_port_type type;
+ uint8_t fm_rev_maj;
+ uint8_t fm_rev_min;
+ union fman_port_bmi_regs __iomem *bmi_regs;
+ struct fman_port_qmi_regs __iomem *qmi_regs;
+ uint8_t ext_pools_num;
+};
+
+/* External buffer pools configuration */
+struct fman_port_bpools {
+ uint8_t count; /* Num of pools to set up */
+ bool counters_enable; /* Enable allocate counters */
+ uint8_t grp_bp_depleted_num;
+ /* Number of depleted pools - if reached the BMI indicates
+ * the MAC to send a pause frame
+ */
+ struct {
+ uint8_t bpid; /* BM pool ID */
+ uint16_t size;
+ /* Pool's size - must be in ascending order */
+ bool is_backup;
+ /* If this is a backup pool */
+ bool grp_bp_depleted;
+ /* Consider this buffer in multiple pools depletion criteria*/
+ bool single_bp_depleted;
+ /* Consider this buffer in single pool depletion criteria */
+ bool pfc_priorities_en;
+ } bpool[FMAN_PORT_MAX_EXT_POOLS_NUM];
+};
+
+enum fman_port_rate_limiter_scale_down {
+ E_FMAN_PORT_RATE_DOWN_NONE,
+ E_FMAN_PORT_RATE_DOWN_BY_2,
+ E_FMAN_PORT_RATE_DOWN_BY_4,
+ E_FMAN_PORT_RATE_DOWN_BY_8
+};
+
+/* Rate limiter configuration */
+struct fman_port_rate_limiter {
+ uint8_t count_1micro_bit;
+ bool high_burst_size_gran;
+ /* Defines burst_size granularity for OP ports; when true,
+ * burst_size below counts in frames, otherwise in 10^3 frames
+ */
+ uint16_t burst_size;
+ /* Max burst size, in KBytes for Tx port, according to
+ * high_burst_size_gran definition for OP port
+ */
+ uint32_t rate;
+ /* In Kbps for Tx port, in frames/sec for OP port */
+ enum fman_port_rate_limiter_scale_down rate_factor;
+};
+
+/* BMI statistics counters */
+enum fman_port_stats_counters {
+ E_FMAN_PORT_STATS_CNT_FRAME,
+ /* Number of processed frames; valid for all ports */
+ E_FMAN_PORT_STATS_CNT_DISCARD,
+ /* For Rx ports - frames discarded by QMAN, for Tx or O/H ports -
+ * frames discarded due to DMA error; valid for all ports
+ */
+ E_FMAN_PORT_STATS_CNT_DEALLOC_BUF,
+ /* Number of buffer deallocate operations; valid for all ports */
+ E_FMAN_PORT_STATS_CNT_RX_BAD_FRAME,
+ /* Number of bad Rx frames, like CRC error, Rx FIFO overflow etc;
+ * valid for Rx ports only
+ */
+ E_FMAN_PORT_STATS_CNT_RX_LARGE_FRAME,
+ /* Number of Rx oversized frames, that is frames exceeding max frame
+ * size configured for the corresponding ETH controller;
+ * valid for Rx ports only
+ */
+ E_FMAN_PORT_STATS_CNT_RX_OUT_OF_BUF,
+ /* Frames discarded due to lack of external buffers; valid for
+ * Rx ports only
+ */
+ E_FMAN_PORT_STATS_CNT_LEN_ERR,
+ /* Frames discarded due to frame length error; valid for Tx and
+ * O/H ports only
+ */
+ E_FMAN_PORT_STATS_CNT_UNSUPPORTED_FORMAT,
+ /* Frames discarded due to unsupported FD format; valid for Tx
+ * and O/H ports only
+ */
+ E_FMAN_PORT_STATS_CNT_FILTERED_FRAME,
+ /* Number of frames filtered out by PCD module; valid for
+ * Rx and OP ports only
+ */
+ E_FMAN_PORT_STATS_CNT_DMA_ERR,
+ /* Frames rejected by QMAN that were not able to release their
+ * buffers due to DMA error; valid for Rx and O/H ports only
+ */
+ E_FMAN_PORT_STATS_CNT_WRED_DISCARD
+ /* Frames going through O/H port that were not able to to enter the
+ * return queue due to WRED algorithm; valid for O/H ports only
+ */
+};
+
+/* BMI performance counters */
+enum fman_port_perf_counters {
+ E_FMAN_PORT_PERF_CNT_CYCLE, /* Cycle counter */
+ E_FMAN_PORT_PERF_CNT_TASK_UTIL, /* Tasks utilization counter */
+ E_FMAN_PORT_PERF_CNT_QUEUE_UTIL,
+ /* For Rx ports - Rx queue utilization, for Tx ports - Tx conf queue
+ * utilization; not valid for O/H ports
+ */
+ E_FMAN_PORT_PERF_CNT_DMA_UTIL, /* DMA utilization counter */
+ E_FMAN_PORT_PERF_CNT_FIFO_UTIL, /* FIFO utilization counter */
+ E_FMAN_PORT_PERF_CNT_RX_PAUSE
+ /* Number of cycles in which Rx pause activation control is on;
+ * valid for Rx ports only
+ */
+};
+
+/* QMI counters */
+enum fman_port_qmi_counters {
+ E_FMAN_PORT_ENQ_TOTAL, /* EnQ tot frame cntr */
+ E_FMAN_PORT_DEQ_TOTAL, /* DeQ tot frame cntr; invalid for Rx ports*/
+ E_FMAN_PORT_DEQ_FROM_DFLT,
+ /* Dequeue from default FQID counter not valid for Rx ports */
+ E_FMAN_PORT_DEQ_CONFIRM /* DeQ confirm cntr invalid for Rx ports */
+};
+
+/* FM Port API */
+void fman_port_defconfig(struct fman_port_cfg *cfg, enum fman_port_type type);
+int fman_port_init(struct fman_port *port,
+ struct fman_port_cfg *cfg, struct fman_port_params *params);
+int fman_port_enable(struct fman_port *port);
+int fman_port_disable(const struct fman_port *port);
+int fman_port_set_bpools(const struct fman_port *port,
+ const struct fman_port_bpools *bp);
+int fman_port_set_rate_limiter(struct fman_port *port,
+ struct fman_port_rate_limiter *rate_limiter);
+int fman_port_delete_rate_limiter(struct fman_port *port);
+int fman_port_set_err_mask(struct fman_port *port, uint32_t err_mask);
+int fman_port_set_discard_mask(struct fman_port *port, uint32_t discard_mask);
+int fman_port_modify_rx_fd_bits(struct fman_port *port,
+ uint8_t rx_fd_bits, bool add);
+int fman_port_set_perf_cnt_params(struct fman_port *port,
+ struct fman_port_perf_cnt_params *params);
+int fman_port_set_stats_cnt_mode(struct fman_port *port, bool enable);
+int fman_port_set_perf_cnt_mode(struct fman_port *port, bool enable);
+int fman_port_set_queue_cnt_mode(struct fman_port *port, bool enable);
+int fman_port_set_bpool_cnt_mode(struct fman_port *port,
+ uint8_t bpid, bool enable);
+uint32_t fman_port_get_stats_counter(struct fman_port *port,
+ enum fman_port_stats_counters counter);
+void fman_port_set_stats_counter(struct fman_port *port,
+ enum fman_port_stats_counters counter,
+ uint32_t value);
+uint32_t fman_port_get_perf_counter(struct fman_port *port,
+ enum fman_port_perf_counters counter);
+void fman_port_set_perf_counter(struct fman_port *port,
+ enum fman_port_perf_counters counter,
+ uint32_t value);
+uint32_t fman_port_get_qmi_counter(struct fman_port *port,
+ enum fman_port_qmi_counters counter);
+void fman_port_set_qmi_counter(struct fman_port *port,
+ enum fman_port_qmi_counters counter,
+ uint32_t value);
+uint32_t fman_port_get_bpool_counter(struct fman_port *port, uint8_t bpid);
+void fman_port_set_bpool_counter(struct fman_port *port,
+ uint8_t bpid, uint32_t value);
+int fman_port_add_congestion_grps(struct fman_port *port,
+ uint32_t grps_map[FMAN_PORT_CG_MAP_NUM]);
+int fman_port_remove_congestion_grps(struct fman_port *port,
+ uint32_t grps_map[FMAN_PORT_CG_MAP_NUM]);
+
+#endif /* __FSL_FMAN_PORT_H */
diff --git a/drivers/soc/fsl/fman/flib/fsl_fman_prs.h b/drivers/soc/fsl/fman/flib/fsl_fman_prs.h
new file mode 100644
index 0000000..0482b04
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fsl_fman_prs.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FMAN_PRS_H
+#define __FSL_FMAN_PRS_H
+
+#include "common/general.h"
+
+#define FM_PCD_EX_PRS_DOUBLE_ECC 0x02000000
+#define FM_PCD_EX_PRS_SINGLE_ECC 0x01000000
+
+#define FM_PCD_PRS_PPSC_ALL_PORTS 0xffff0000
+#define FM_PCD_PRS_RPIMAC_EN 0x00000001
+#define FM_PCD_PRS_PORT_IDLE_STS 0xffff0000
+#define FM_PCD_PRS_SINGLE_ECC 0x00004000
+#define FM_PCD_PRS_DOUBLE_ECC 0x00004000
+#define PRS_MAX_CYCLE_LIMIT 8191
+
+#define DEFAULT_MAX_PRS_CYC_LIM 0
+
+struct fman_prs_regs {
+ uint32_t fmpr_rpclim;
+ uint32_t fmpr_rpimac;
+ uint32_t pmeec;
+ uint32_t res00c[5];
+ uint32_t fmpr_pevr;
+ uint32_t fmpr_pever;
+ uint32_t res028;
+ uint32_t fmpr_perr;
+ uint32_t fmpr_perer;
+ uint32_t res034;
+ uint32_t res038[10];
+ uint32_t fmpr_ppsc;
+ uint32_t res064;
+ uint32_t fmpr_pds;
+ uint32_t fmpr_l2rrs;
+ uint32_t fmpr_l3rrs;
+ uint32_t fmpr_l4rrs;
+ uint32_t fmpr_srrs;
+ uint32_t fmpr_l2rres;
+ uint32_t fmpr_l3rres;
+ uint32_t fmpr_l4rres;
+ uint32_t fmpr_srres;
+ uint32_t fmpr_spcs;
+ uint32_t fmpr_spscs;
+ uint32_t fmpr_hxscs;
+ uint32_t fmpr_mrcs;
+ uint32_t fmpr_mwcs;
+ uint32_t fmpr_mrscs;
+ uint32_t fmpr_mwscs;
+ uint32_t fmpr_fcscs;
+};
+
+struct fman_prs_cfg {
+ uint32_t port_id_stat;
+ uint16_t max_prs_cyc_lim;
+ uint32_t prs_exceptions;
+};
+
+uint32_t fman_prs_get_err_event(struct fman_prs_regs __iomem *regs,
+ uint32_t ev_mask);
+uint32_t fman_prs_get_err_ev_mask(struct fman_prs_regs __iomem *regs);
+void fman_prs_ack_err_event(struct fman_prs_regs __iomem *regs,
+ uint32_t event);
+uint32_t fman_prs_get_expt_event(struct fman_prs_regs __iomem *regs,
+ uint32_t ev_mask);
+uint32_t fman_prs_get_expt_ev_mask(struct fman_prs_regs __iomem *regs);
+void fman_prs_ack_expt_event(struct fman_prs_regs __iomem *regs,
+ uint32_t event);
+void fman_prs_defconfig(struct fman_prs_cfg *cfg);
+int fman_prs_init(struct fman_prs_regs __iomem *regs, struct fman_prs_cfg *cfg);
+void fman_prs_enable(struct fman_prs_regs __iomem *regs);
+void fman_prs_disable(struct fman_prs_regs __iomem *regs);
+void fman_prs_set_stst_port_msk(struct fman_prs_regs __iomem *regs,
+ uint32_t pid_msk);
+void fman_prs_set_stst(struct fman_prs_regs __iomem *regs, bool enable);
+#endif /* __FSL_FMAN_PRS_H */
diff --git a/drivers/soc/fsl/fman/flib/fsl_fman_rtc.h b/drivers/soc/fsl/fman/flib/fsl_fman_rtc.h
new file mode 100644
index 0000000..c98a526
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fsl_fman_rtc.h
@@ -0,0 +1,415 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FMAN_RTC_H
+#define __FSL_FMAN_RTC_H
+
+#include "common/general.h"
+
+/* FM RTC Registers definitions */
+#define FMAN_RTC_TMR_CTRL_ALMP1 0x80000000
+#define FMAN_RTC_TMR_CTRL_ALMP2 0x40000000
+#define FMAN_RTC_TMR_CTRL_FS 0x10000000
+#define FMAN_RTC_TMR_CTRL_PP1L 0x08000000
+#define FMAN_RTC_TMR_CTRL_PP2L 0x04000000
+#define FMAN_RTC_TMR_CTRL_TCLK_PERIOD_MASK 0x03FF0000
+#define FMAN_RTC_TMR_CTRL_FRD 0x00004000
+#define FMAN_RTC_TMR_CTRL_SLV 0x00002000
+#define FMAN_RTC_TMR_CTRL_ETEP1 0x00000100
+#define FMAN_RTC_TMR_CTRL_COPH 0x00000080
+#define FMAN_RTC_TMR_CTRL_CIPH 0x00000040
+#define FMAN_RTC_TMR_CTRL_TMSR 0x00000020
+#define FMAN_RTC_TMR_CTRL_DBG 0x00000010
+#define FMAN_RTC_TMR_CTRL_BYP 0x00000008
+#define FMAN_RTC_TMR_CTRL_TE 0x00000004
+#define FMAN_RTC_TMR_CTRL_CKSEL_OSC_CLK 0x00000003
+#define FMAN_RTC_TMR_CTRL_CKSEL_MAC_CLK 0x00000001
+#define FMAN_RTC_TMR_CTRL_CKSEL_EXT_CLK 0x00000000
+#define FMAN_RTC_TMR_CTRL_TCLK_PERIOD_SHIFT 16
+
+#define FMAN_RTC_TMR_TEVENT_ETS2 0x02000000
+#define FMAN_RTC_TMR_TEVENT_ETS1 0x01000000
+#define FMAN_RTC_TMR_TEVENT_ALM2 0x00020000
+#define FMAN_RTC_TMR_TEVENT_ALM1 0x00010000
+#define FMAN_RTC_TMR_TEVENT_PP1 0x00000080
+#define FMAN_RTC_TMR_TEVENT_PP2 0x00000040
+#define FMAN_RTC_TMR_TEVENT_PP3 0x00000020
+#define FMAN_RTC_TMR_TEVENT_ALL (FMAN_RTC_TMR_TEVENT_ETS2 |\
+ FMAN_RTC_TMR_TEVENT_ETS1 |\
+ FMAN_RTC_TMR_TEVENT_ALM2 |\
+ FMAN_RTC_TMR_TEVENT_ALM1 |\
+ FMAN_RTC_TMR_TEVENT_PP1 |\
+ FMAN_RTC_TMR_TEVENT_PP2 |\
+ FMAN_RTC_TMR_TEVENT_PP3)
+
+#define FMAN_RTC_TMR_PRSC_OCK_MASK 0x0000FFFF
+
+/* FM RTC Alarm Polarity Options. */
+enum fman_rtc_alarm_polarity {
+ FMAN_RTC_ALARM_POLARITY_ACTIVE_HIGH,
+ /* Active-high output polarity */
+ FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW/* Active-low output polarity */
+};
+
+/* FM RTC Trigger Polarity Options. */
+enum fman_rtc_trigger_polarity {
+ FMAN_RTC_TRIGGER_ON_RISING_EDGE,/* Trigger on rising edge */
+ FMAN_RTC_TRIGGER_ON_FALLING_EDGE/* Trigger on falling edge */
+};
+
+/* IEEE1588 Timer Module FM RTC Optional Clock Sources. */
+enum fman_src_clock {
+ FMAN_RTC_SOURCE_CLOCK_EXTERNAL,
+ /* external high precision timer
+ * reference clock
+ */
+ FMAN_RTC_SOURCE_CLOCK_SYSTEM,/* MAC system clock */
+ FMAN_RTC_SOURCE_CLOCK_OSCILATOR
+ /* RTC clock oscilator */
+};
+
+/* RTC default values */
+#define DEFAULT_SRC_CLOCK FMAN_RTC_SOURCE_CLOCK_SYSTEM
+#define DEFAULT_INVERT_INPUT_CLK_PHASE false
+#define DEFAULT_INVERT_OUTPUT_CLK_PHASE false
+#define DEFAULT_ALARM_POLARITY FMAN_RTC_ALARM_POLARITY_ACTIVE_HIGH
+#define DEFAULT_TRIGGER_POLARITY FMAN_RTC_TRIGGER_ON_FALLING_EDGE
+#define DEFAULT_PULSE_REALIGN false
+
+#define FMAN_RTC_MAX_NUM_OF_ALARMS 3
+#define FMAN_RTC_MAX_NUM_OF_PERIODIC_PULSES 4
+#define FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS 3
+
+/* FM RTC timer alarm */
+struct tmr_alarm_t {
+ uint32_t tmr_alarm_h; /* */
+ uint32_t tmr_alarm_l; /* */
+};
+
+/* FM RTC timer Ex trigger */
+struct tmr_ext_trigger_t {
+ uint32_t tmr_etts_h; /* */
+ uint32_t tmr_etts_l; /* */
+};
+
+struct rtc_regs {
+ uint32_t tmr_id; /* 0x000 Module ID register */
+ uint32_t tmr_id2; /* 0x004 Controller ID register */
+ uint32_t reserved0008[30];
+ uint32_t tmr_ctrl; /* 0x0080 timer control register */
+ uint32_t tmr_tevent; /* 0x0084 timer event register */
+ uint32_t tmr_temask; /* 0x0088 timer event mask register */
+ uint32_t reserved008c[3];
+ uint32_t tmr_cnt_h; /* 0x0098 timer counter high register */
+ uint32_t tmr_cnt_l; /* 0x009c timer counter low register */
+ /* 0x00a0 timer drift compensation addend register */
+ uint32_t tmr_add;
+ uint32_t tmr_acc; /* 0x00a4 timer accumulator register */
+ uint32_t tmr_prsc; /* 0x00a8 timer prescale */
+ uint32_t reserved00ac;
+ uint32_t tmr_off_h; /* 0x00b0 timer offset high */
+ uint32_t tmr_off_l; /* 0x00b4 timer offset low */
+ /* 0x00b8 timer alarm */
+ struct tmr_alarm_t tmr_alarm[FMAN_RTC_MAX_NUM_OF_ALARMS];
+ /* 0x00d0 timer fixed period interval */
+ uint32_t tmr_fiper[FMAN_RTC_MAX_NUM_OF_PERIODIC_PULSES];
+ struct tmr_ext_trigger_t tmr_etts[FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS];
+ /* 0x00e0 time stamp general purpose external */
+ uint32_t reserved00f0[4];
+};
+
+struct rtc_cfg {
+ enum fman_src_clock src_clk;
+ uint32_t ext_src_clk_freq;
+ uint32_t rtc_freq_hz;
+ bool timer_slave_mode;
+ bool invert_input_clk_phase;
+ bool invert_output_clk_phase;
+ uint32_t events_mask;
+ bool bypass; /* Indicates if frequency compensation
+ * is bypassed
+ */
+ bool pulse_realign;
+ enum fman_rtc_alarm_polarity alarm_polarity[FMAN_RTC_MAX_NUM_OF_ALARMS];
+ enum fman_rtc_trigger_polarity trigger_polarity
+ [FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS];
+};
+
+/* fman_rtc_defconfig() - Get default RTC configuration
+ * cfg: pointer to configuration structure.
+ * Call this function to obtain a default set of configuration values for
+ * initializing RTC. The user can overwrite any of the values before calling
+ * fman_rtc_init(), if specific configuration needs to be applied.
+ */
+void fman_rtc_defconfig(struct rtc_cfg *cfg);
+
+/* fman_rtc_get_events() - Get the events
+ * regs: Pointer to RTC register block
+ * Returns: The events
+ */
+uint32_t fman_rtc_get_events(struct rtc_regs __iomem *regs);
+
+/* fman_rtc_get_interrupt_mask() - Get the events mask
+ * regs: Pointer to RTC register block
+ * Returns: The events mask
+ */
+uint32_t fman_rtc_get_interrupt_mask(struct rtc_regs __iomem *regs);
+
+/* fman_rtc_set_interrupt_mask() - Set the events mask
+ * regs: Pointer to RTC register block
+ * mask: The mask to set
+ */
+void fman_rtc_set_interrupt_mask(struct rtc_regs __iomem *regs, uint32_t mask);
+
+/* fman_rtc_get_event() - Check if specific events occurred
+ * regs: Pointer to RTC register block
+ * ev_mask: a mask of the events to check
+ * Returns: 0 if the events did not occur.
+ * Non zero if one of the events occurred
+ */
+uint32_t fman_rtc_get_event(struct rtc_regs __iomem *regs, uint32_t ev_mask);
+
+/* fman_rtc_check_and_clear_event() - Clear events which are on
+ * regs: Pointer to RTC register block
+ * Returns: A mask of the events which were cleared
+ */
+uint32_t fman_rtc_check_and_clear_event(struct rtc_regs __iomem *regs);
+
+/* fman_rtc_ack_event() - Clear events
+ * regs: Pointer to RTC register block
+ * events: The events to disable
+ */
+void fman_rtc_ack_event(struct rtc_regs __iomem *regs, uint32_t events);
+
+/* fman_rtc_enable_interrupt() - Enable events interrupts
+ * regs: Pointer to RTC register block
+ * mask: The events to disable
+ */
+void fman_rtc_enable_interrupt(struct rtc_regs __iomem *regs, uint32_t mask);
+
+/* fman_rtc_disable_interrupt() - Disable events interrupts
+ * regs: Pointer to RTC register block
+ * mask: The events to disable
+ */
+void fman_rtc_disable_interrupt(struct rtc_regs __iomem *regs, uint32_t mask);
+
+/* fman_rtc_get_timer_ctrl() - Get the control register
+ * regs: Pointer to RTC register block
+ * Returns: The control register value
+ */
+uint32_t fman_rtc_get_timer_ctrl(struct rtc_regs __iomem *regs);
+
+/* fman_rtc_set_timer_ctrl() - Set timer control register
+ * regs: Pointer to RTC register block
+ * val: The value to set
+ */
+void fman_rtc_set_timer_ctrl(struct rtc_regs __iomem *regs, uint32_t val);
+
+/* fman_rtc_get_frequency_compensation() - Get the frequency compensation
+ * regs: Pointer to RTC register block
+ *
+ * Returns: The timer counter
+ */
+uint32_t fman_rtc_get_frequency_compensation(struct rtc_regs __iomem *regs);
+
+/* fman_rtc_set_frequency_compensation() - Set frequency compensation
+ * regs: Pointer to RTC register block
+ * val: The value to set
+ */
+void fman_rtc_set_frequency_compensation(struct rtc_regs __iomem *regs,
+ uint32_t val);
+
+/* fman_rtc_get_trigger_stamp() - Get a trigger stamp
+ * regs: Pointer to RTC register block
+ * id: The id of the trigger stamp
+ *
+ * Returns: The time stamp
+ */
+uint64_t fman_rtc_get_trigger_stamp(struct rtc_regs __iomem *regs, int id);
+
+/* fman_rtc_set_timer_alarm_l() - Set timer alarm low register
+ * regs: Pointer to RTC register block
+ * index: The index of alarm to set
+ * val: The value to set
+ */
+void fman_rtc_set_timer_alarm_l(struct rtc_regs __iomem *regs, int index,
+ uint32_t val);
+
+/* fman_rtc_set_timer_alarm() - Set timer alarm
+ * regs: Pointer to RTC register block
+ * index: The index of alarm to set
+ * val: The value to set
+ */
+void fman_rtc_set_timer_alarm(struct rtc_regs __iomem *regs, int index,
+ int64_t val);
+
+/* fman_rtc_set_timer_fiper() - Set timer fiper
+ * regs: Pointer to RTC register block
+ * index: The index of fiper to set
+ * val: The value to set
+ */
+void fman_rtc_set_timer_fiper(struct rtc_regs __iomem *regs, int index,
+ uint32_t val);
+
+/* fman_rtc_set_timer_offset() - Set timer offset
+ * regs: Pointer to RTC register block
+ * val: The value to set
+ */
+void fman_rtc_set_timer_offset(struct rtc_regs __iomem *regs, int64_t val);
+
+/* fman_rtc_get_timer() - Get the timer counter
+ * regs: Pointer to RTC register block
+ * Returns: The timer counter
+ */
+static inline uint64_t fman_rtc_get_timer(struct rtc_regs __iomem *regs)
+{
+ uint64_t time;
+ /* TMR_CNT_L must be read first to get an accurate value */
+ time = (uint64_t)ioread32be(®s->tmr_cnt_l);
+ time |= ((uint64_t)ioread32be(®s->tmr_cnt_h) << 32);
+
+ return time;
+}
+
+/* fman_rtc_set_timer() - Set timer counter
+ * regs: Pointer to RTC register block
+ * val: The value to set
+ */
+static inline void fman_rtc_set_timer(struct rtc_regs __iomem *regs,
+ int64_t val)
+{
+ iowrite32be((uint32_t)val, ®s->tmr_cnt_l);
+ iowrite32be((uint32_t)(val >> 32), ®s->tmr_cnt_h);
+}
+
+/* fman_rtc_timers_soft_reset() - Soft reset
+ * regs: Pointer to RTC register block
+ * Resets all the timer registers and state machines for the 1588 IP and
+ * the attached client 1588
+ */
+void fman_rtc_timers_soft_reset(struct rtc_regs __iomem *regs);
+
+/* fman_rtc_clear_external_trigger() - Clear an external trigger
+ * regs: Pointer to RTC register block
+ * id: The id of the trigger to clear
+ */
+void fman_rtc_clear_external_trigger(struct rtc_regs __iomem *regs, int id);
+
+/* fman_rtc_clear_periodic_pulse() - Clear periodic pulse
+ * regs: Pointer to RTC register block
+ * id: The id of the fiper to clear
+ */
+void fman_rtc_clear_periodic_pulse(struct rtc_regs __iomem *regs, int id);
+
+/* fman_rtc_enable() - Enable RTC hardware block
+ * regs: Pointer to RTC register block
+ */
+void fman_rtc_enable(struct rtc_regs __iomem *regs, bool reset_clock);
+
+/* fman_rtc_is_enabled() - Is RTC hardware block enabled
+ * regs: Pointer to RTC register block
+ * Return: true if enabled
+ */
+bool fman_rtc_is_enabled(struct rtc_regs __iomem *regs);
+
+/* fman_rtc_disable() - Disable RTC hardware block
+ * regs: Pointer to RTC register block
+ */
+void fman_rtc_disable(struct rtc_regs __iomem *regs);
+
+/* fman_rtc_init() - Init RTC hardware block
+ * cfg: RTC configuration data
+ * regs: Pointer to RTC register block
+ * num_alarms: Number of alarms in RTC
+ * num_fipers: Number of fipers in RTC
+ * num_ext_triggers: Number of external triggers in RTC
+ * freq_compensation: Frequency compensation
+ * output_clock_divisor: Output clock divisor
+ * This function initializes RTC and applies basic configuration.
+ */
+void fman_rtc_init(struct rtc_cfg *cfg, struct rtc_regs __iomem *regs,
+ int num_alarms, int num_fipers, int num_ext_triggers,
+ bool init_freq_comp, uint32_t freq_compensation,
+ uint32_t output_clock_divisor);
+
+/* fman_rtc_set_alarm() - Set an alarm
+ * regs: Pointer to RTC register block
+ * id: id of alarm
+ * val: value to write
+ * enable: should interrupt be enabled
+ */
+void fman_rtc_set_alarm(struct rtc_regs __iomem *regs, int id, uint32_t val,
+ bool enable);
+
+/* fman_rtc_set_periodic_pulse() - Set an alarm
+ * regs: Pointer to RTC register block
+ * id: id of fiper
+ * val: value to write
+ * enable: should interrupt be enabled
+ */
+void fman_rtc_set_periodic_pulse(struct rtc_regs __iomem *regs, int id,
+ uint32_t val, bool enable);
+
+/* fman_rtc_set_ext_trigger() - Set an external trigger
+ * regs: Pointer to RTC register block
+ * id: id of trigger
+ * enable: should interrupt be enabled
+ * use_pulse_as_input: use the pulse as input
+ */
+void fman_rtc_set_ext_trigger(struct rtc_regs __iomem *regs, int id,
+ bool enable, bool use_pulse_as_input);
+
+struct fm_rtc_alarm_params {
+ uint8_t alarm_id; /* 0 or 1 */
+ uint64_t alarm_time; /* In nanoseconds, the time when the
+ * alarm should go off - must be a
+ * multiple of the RTC period
+ */
+ void (*f_alarm_callback)(void *app, uint8_t id);/* This routine will
+ * be called when RTC
+ * reaches alarm_time
+ */
+ bool clear_on_expiration; /* true to turn off the alarm once
+ * expired.
+ */
+};
+
+struct fm_rtc_periodic_pulse_params {
+ uint8_t periodic_pulse_id; /* 0 or 1 */
+ uint64_t periodic_pulse_period; /* In Nanoseconds. Must be a multiple
+ * of the RTC period
+ */
+ /* This routine will be called every periodic_pulse_period. */
+ void (*f_periodic_pulse_callback)(void *app, uint8_t id);
+};
+
+#endif /* __FSL_FMAN_RTC_H */
diff --git a/drivers/soc/fsl/fman/flib/fsl_fman_sp.h b/drivers/soc/fsl/fman/flib/fsl_fman_sp.h
new file mode 100644
index 0000000..e3e6888
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fsl_fman_sp.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FMAN_SP_H
+#define __FSL_FMAN_SP_H
+
+#include "common/general.h"
+#include "fsl_fman.h"
+
+struct fm_pcd_storage_profile_regs {
+ uint32_t fm_sp_ebmpi[8];
+ /*offset 0 - 0xc */
+ /* Buffer Manager pool Information */
+
+ uint32_t fm_sp_acnt; /*offset 0x20 */
+ uint32_t fm_sp_ebm; /*offset 0x24 */
+ uint32_t fm_sp_da; /*offset 0x28 */
+ uint32_t fm_sp_icp; /*offset 0x2c */
+ uint32_t fm_sp_mpd; /*offset 0x30 */
+ uint32_t res1[2]; /*offset 0x34 - 0x38 */
+ uint32_t fm_sp_spliodn; /*offset 0x3c */
+};
+
+/* structure for defining internal context copying */
+struct fman_sp_int_context_data_copy {
+ uint16_t ext_buf_offset; /* Offset in External buffer to which
+ * internal context is copied to (Rx)
+ * or taken from (Tx, Op).
+ */
+ uint8_t int_context_offset; /* Offset within internal context to copy
+ * from (Rx) or to copy to (Tx, Op).
+ */
+ uint16_t size; /* Internal offset size to be copied */
+};
+
+/*struct for defining external buffer margins */
+struct fman_sp_buf_margins {
+ uint16_t start_margins; /* Number of bytes to be left at the
+ * beginning of the external buffer (must be
+ * divisible by 16)
+ */
+ uint16_t end_margins; /* number of bytes to be left at the end of
+ * the external buffer(must be divisible by 16)
+ */
+};
+
+struct fm_storage_profile_params {
+ struct fman_ext_pools fm_ext_pools;
+ struct fman_backup_bm_pools backup_pools;
+ struct fman_sp_int_context_data_copy *int_context;
+ struct fman_sp_buf_margins *buf_margins;
+ enum fman_dma_swap_option dma_swap_data;
+ enum fman_dma_cache_option int_context_cache_attr;
+ enum fman_dma_cache_option header_cache_attr;
+ enum fman_dma_cache_option scatter_gather_cache_attr;
+ bool dma_write_optimize;
+ uint16_t liodn_offset;
+ bool no_scather_gather;
+ struct fman_buf_pool_depletion buf_pool_depletion;
+};
+
+/* Registers bit fields */
+#define FMAN_SP_EXT_BUF_POOL_EN_COUNTER 0x40000000
+#define FMAN_SP_EXT_BUF_POOL_VALID 0x80000000
+#define FMAN_SP_EXT_BUF_POOL_BACKUP 0x20000000
+#define FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE 0x00100000
+#define FMAN_SP_SG_DISABLE 0x80000000
+
+/* shifts */
+#define FMAN_SP_EXT_BUF_POOL_ID_SHIFT 16
+#define FMAN_SP_POOL_DEP_NUM_OF_POOLS_SHIFT 16
+#define FMAN_SP_EXT_BUF_MARG_START_SHIFT 16
+#define FMAN_SP_EXT_BUF_MARG_END_SHIFT 0
+#define FMAN_SP_DMA_ATTR_SWP_SHIFT 30
+#define FMAN_SP_DMA_ATTR_IC_CACHE_SHIFT 28
+#define FMAN_SP_DMA_ATTR_HDR_CACHE_SHIFT 26
+#define FMAN_SP_DMA_ATTR_SG_CACHE_SHIFT 24
+#define FMAN_SP_IC_TO_EXT_SHIFT 16
+#define FMAN_SP_IC_FROM_INT_SHIFT 8
+#define FMAN_SP_IC_SIZE_SHIFT 0
+
+/* defaults */
+#define DEFAULT_FMAN_SP_DMA_SWAP_DATA FMAN_DMA_NO_SWP
+#define DEFAULT_FMAN_SP_DMA_INT_CONTEXT_CACHE_ATTR FMAN_DMA_NO_STASH
+#define DEFAULT_FMAN_SP_DMA_HEADER_CACHE_ATTR FMAN_DMA_NO_STASH
+#define DEFAULT_FMAN_SP_DMA_SCATTER_GATHER_CACHE_ATTR FMAN_DMA_NO_STASH
+#define DEFAULT_FMAN_SP_DMA_WRITE_OPTIMIZE true
+#define DEFAULT_FMAN_SP_NO_SCATTER_GATHER false
+
+void fman_vsp_defconfig(struct fm_storage_profile_params *cfg);
+
+void fman_vsp_init(struct fm_pcd_storage_profile_regs *regs,
+ uint16_t index,
+ struct fm_storage_profile_params *fm_vsp_params,
+ int port_max_num_of_ext_pools, int bm_max_num_of_pools,
+ int max_num_of_pfc_priorities);
+
+uint32_t fman_vsp_get_statistics(struct fm_pcd_storage_profile_regs *regs,
+ uint16_t index);
+
+void fman_vsp_set_statistics(struct fm_pcd_storage_profile_regs *regs,
+ uint16_t index, uint32_t value);
+
+#endif /* __FSL_FMAN_SP_H */
diff --git a/drivers/soc/fsl/fman/flib/fsl_fman_tgec.h b/drivers/soc/fsl/fman/flib/fsl_fman_tgec.h
new file mode 100644
index 0000000..e7b3c4f
--- /dev/null
+++ b/drivers/soc/fsl/fman/flib/fsl_fman_tgec.h
@@ -0,0 +1,484 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSL_FMAN_TGEC_H
+#define __FSL_FMAN_TGEC_H
+
+#include "common/general.h"
+#include "fsl_enet.h"
+
+/* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */
+#define TGEC_TX_IPG_LENGTH_MASK 0x000003ff
+
+enum tgec_counters {
+ E_TGEC_COUNTER_R64,
+ E_TGEC_COUNTER_R127,
+ E_TGEC_COUNTER_R255,
+ E_TGEC_COUNTER_R511,
+ E_TGEC_COUNTER_R1023,
+ E_TGEC_COUNTER_R1518,
+ E_TGEC_COUNTER_R1519X,
+ E_TGEC_COUNTER_TRFRG,
+ E_TGEC_COUNTER_TRJBR,
+ E_TGEC_COUNTER_RDRP,
+ E_TGEC_COUNTER_RALN,
+ E_TGEC_COUNTER_TRUND,
+ E_TGEC_COUNTER_TROVR,
+ E_TGEC_COUNTER_RXPF,
+ E_TGEC_COUNTER_TXPF,
+ E_TGEC_COUNTER_ROCT,
+ E_TGEC_COUNTER_RMCA,
+ E_TGEC_COUNTER_RBCA,
+ E_TGEC_COUNTER_RPKT,
+ E_TGEC_COUNTER_RUCA,
+ E_TGEC_COUNTER_RERR,
+ E_TGEC_COUNTER_TOCT,
+ E_TGEC_COUNTER_TMCA,
+ E_TGEC_COUNTER_TBCA,
+ E_TGEC_COUNTER_TUCA,
+ E_TGEC_COUNTER_TERR
+};
+
+/* Command and Configuration Register (COMMAND_CONFIG) */
+#define CMD_CFG_EN_TIMESTAMP 0x00100000
+#define CMD_CFG_TX_ADDR_INS_SEL 0x00080000
+#define CMD_CFG_NO_LEN_CHK 0x00020000
+#define CMD_CFG_SEND_IDLE 0x00010000
+#define CMD_CFG_RX_ER_DISC 0x00004000
+#define CMD_CFG_CMD_FRM_EN 0x00002000
+#define CMD_CFG_STAT_CLR 0x00001000
+#define CMD_CFG_LOOPBACK_EN 0x00000400
+#define CMD_CFG_TX_ADDR_INS 0x00000200
+#define CMD_CFG_PAUSE_IGNORE 0x00000100
+#define CMD_CFG_PAUSE_FWD 0x00000080
+#define CMD_CFG_PROMIS_EN 0x00000010
+#define CMD_CFG_WAN_MODE 0x00000008
+#define CMD_CFG_RX_EN 0x00000002
+#define CMD_CFG_TX_EN 0x00000001
+
+/* Interrupt Mask Register (IMASK) */
+#define TGEC_IMASK_MDIO_SCAN_EVENT 0x00010000
+#define TGEC_IMASK_MDIO_CMD_CMPL 0x00008000
+#define TGEC_IMASK_REM_FAULT 0x00004000
+#define TGEC_IMASK_LOC_FAULT 0x00002000
+#define TGEC_IMASK_TX_ECC_ER 0x00001000
+#define TGEC_IMASK_TX_FIFO_UNFL 0x00000800
+#define TGEC_IMASK_TX_FIFO_OVFL 0x00000400
+#define TGEC_IMASK_TX_ER 0x00000200
+#define TGEC_IMASK_RX_FIFO_OVFL 0x00000100
+#define TGEC_IMASK_RX_ECC_ER 0x00000080
+#define TGEC_IMASK_RX_JAB_FRM 0x00000040
+#define TGEC_IMASK_RX_OVRSZ_FRM 0x00000020
+#define TGEC_IMASK_RX_RUNT_FRM 0x00000010
+#define TGEC_IMASK_RX_FRAG_FRM 0x00000008
+#define TGEC_IMASK_RX_LEN_ER 0x00000004
+#define TGEC_IMASK_RX_CRC_ER 0x00000002
+#define TGEC_IMASK_RX_ALIGN_ER 0x00000001
+
+#define TGEC_EVENTS_MASK \
+ ((uint32_t)(TGEC_IMASK_MDIO_SCAN_EVENT | \
+ TGEC_IMASK_MDIO_CMD_CMPL | \
+ TGEC_IMASK_REM_FAULT | \
+ TGEC_IMASK_LOC_FAULT | \
+ TGEC_IMASK_TX_ECC_ER | \
+ TGEC_IMASK_TX_FIFO_UNFL | \
+ TGEC_IMASK_TX_FIFO_OVFL | \
+ TGEC_IMASK_TX_ER | \
+ TGEC_IMASK_RX_FIFO_OVFL | \
+ TGEC_IMASK_RX_ECC_ER | \
+ TGEC_IMASK_RX_JAB_FRM | \
+ TGEC_IMASK_RX_OVRSZ_FRM | \
+ TGEC_IMASK_RX_RUNT_FRM | \
+ TGEC_IMASK_RX_FRAG_FRM | \
+ TGEC_IMASK_RX_LEN_ER | \
+ TGEC_IMASK_RX_CRC_ER | \
+ TGEC_IMASK_RX_ALIGN_ER))
+
+/* Hashtable Control Register (HASHTABLE_CTRL) */
+#define TGEC_HASH_MCAST_SHIFT 23
+#define TGEC_HASH_MCAST_EN 0x00000200
+#define TGEC_HASH_ADR_MSK 0x000001ff
+
+#define DEFAULT_WAN_MODE_ENABLE false
+#define DEFAULT_PROMISCUOUS_MODE_ENABLE false
+#define DEFAULT_PAUSE_FORWARD_ENABLE false
+#define DEFAULT_PAUSE_IGNORE false
+#define DEFAULT_TX_ADDR_INS_ENABLE false
+#define DEFAULT_LOOPBACK_ENABLE false
+#define DEFAULT_CMD_FRAME_ENABLE false
+#define DEFAULT_RX_ERROR_DISCARD false
+#define DEFAULT_SEND_IDLE_ENABLE false
+#define DEFAULT_NO_LENGTH_CHECK_ENABLE true
+#define DEFAULT_LGTH_CHECK_NOSTDR false
+#define DEFAULT_TIME_STAMP_ENABLE false
+#define DEFAULT_TX_IPG_LENGTH 12
+#define DEFAULT_MAX_FRAME_LENGTH 0x600
+#define DEFAULT_PAUSE_QUANT 0xf000
+
+/**
+ * 10G memory map
+ **/
+struct tgec_regs {
+ uint32_t tgec_id; /* 0x000 Controller ID */
+ uint32_t reserved001[1]; /* 0x004 */
+ uint32_t command_config; /* 0x008 Control and configuration */
+ uint32_t mac_addr_0; /* 0x00c Lower 32 bits of the MAC adr */
+ uint32_t mac_addr_1; /* 0x010 Upper 16 bits of the MAC adr */
+ uint32_t maxfrm; /* 0x014 Maximum frame length */
+ uint32_t pause_quant; /* 0x018 Pause quanta */
+ uint32_t rx_fifo_sections; /* 0x01c */
+ uint32_t tx_fifo_sections; /* 0x020 */
+ uint32_t rx_fifo_almost_f_e; /* 0x024 */
+ uint32_t tx_fifo_almost_f_e; /* 0x028 */
+ uint32_t hashtable_ctrl; /* 0x02c Hash table control */
+ uint32_t mdio_cfg_status; /* 0x030 */
+ uint32_t mdio_command; /* 0x034 */
+ uint32_t mdio_data; /* 0x038 */
+ uint32_t mdio_regaddr; /* 0x03c */
+ uint32_t status; /* 0x040 */
+ uint32_t tx_ipg_len; /* 0x044 Transmitter inter-packet-gap */
+ uint32_t mac_addr_2; /* 0x048 Lower 32 bits of 2nd MAC adr */
+ uint32_t mac_addr_3; /* 0x04c Upper 16 bits of 2nd MAC adr */
+ uint32_t rx_fifo_ptr_rd; /* 0x050 */
+ uint32_t rx_fifo_ptr_wr; /* 0x054 */
+ uint32_t tx_fifo_ptr_rd; /* 0x058 */
+ uint32_t tx_fifo_ptr_wr; /* 0x05c */
+ uint32_t imask; /* 0x060 Interrupt mask */
+ uint32_t ievent; /* 0x064 Interrupt event */
+ uint32_t udp_port; /* 0x068 Defines a UDP Port number */
+ uint32_t type_1588v2; /* 0x06c Type field for 1588v2 */
+ uint32_t reserved070[4]; /* 0x070 */
+ /*10Ge Statistics Counter */
+ uint32_t tfrm_u; /* 80 aFramesTransmittedOK */
+ uint32_t tfrm_l; /* 84 aFramesTransmittedOK */
+ uint32_t rfrm_u; /* 88 aFramesReceivedOK */
+ uint32_t rfrm_l; /* 8c aFramesReceivedOK */
+ uint32_t rfcs_u; /* 90 aFrameCheckSequenceErrors */
+ uint32_t rfcs_l; /* 94 aFrameCheckSequenceErrors */
+ uint32_t raln_u; /* 98 aAlignmentErrors */
+ uint32_t raln_l; /* 9c aAlignmentErrors */
+ uint32_t txpf_u; /* A0 aPAUSEMACCtrlFramesTransmitted */
+ uint32_t txpf_l; /* A4 aPAUSEMACCtrlFramesTransmitted */
+ uint32_t rxpf_u; /* A8 aPAUSEMACCtrlFramesReceived */
+ uint32_t rxpf_l; /* Ac aPAUSEMACCtrlFramesReceived */
+ uint32_t rlong_u; /* B0 aFrameTooLongErrors */
+ uint32_t rlong_l; /* B4 aFrameTooLongErrors */
+ uint32_t rflr_u; /* B8 aInRangeLengthErrors */
+ uint32_t rflr_l; /* Bc aInRangeLengthErrors */
+ uint32_t tvlan_u; /* C0 VLANTransmittedOK */
+ uint32_t tvlan_l; /* C4 VLANTransmittedOK */
+ uint32_t rvlan_u; /* C8 VLANReceivedOK */
+ uint32_t rvlan_l; /* Cc VLANReceivedOK */
+ uint32_t toct_u; /* D0 if_out_octets */
+ uint32_t toct_l; /* D4 if_out_octets */
+ uint32_t roct_u; /* D8 if_in_octets */
+ uint32_t roct_l; /* Dc if_in_octets */
+ uint32_t ruca_u; /* E0 if_in_ucast_pkts */
+ uint32_t ruca_l; /* E4 if_in_ucast_pkts */
+ uint32_t rmca_u; /* E8 ifInMulticastPkts */
+ uint32_t rmca_l; /* Ec ifInMulticastPkts */
+ uint32_t rbca_u; /* F0 ifInBroadcastPkts */
+ uint32_t rbca_l; /* F4 ifInBroadcastPkts */
+ uint32_t terr_u; /* F8 if_out_errors */
+ uint32_t terr_l; /* Fc if_out_errors */
+ uint32_t reserved100[2]; /* 100-108 */
+ uint32_t tuca_u; /* 108 if_out_ucast_pkts */
+ uint32_t tuca_l; /* 10c if_out_ucast_pkts */
+ uint32_t tmca_u; /* 110 ifOutMulticastPkts */
+ uint32_t tmca_l; /* 114 ifOutMulticastPkts */
+ uint32_t tbca_u; /* 118 ifOutBroadcastPkts */
+ uint32_t tbca_l; /* 11c ifOutBroadcastPkts */
+ uint32_t rdrp_u; /* 120 etherStatsDropEvents */
+ uint32_t rdrp_l; /* 124 etherStatsDropEvents */
+ uint32_t reoct_u; /* 128 etherStatsOctets */
+ uint32_t reoct_l; /* 12c etherStatsOctets */
+ uint32_t rpkt_u; /* 130 etherStatsPkts */
+ uint32_t rpkt_l; /* 134 etherStatsPkts */
+ uint32_t trund_u; /* 138 etherStatsUndersizePkts */
+ uint32_t trund_l; /* 13c etherStatsUndersizePkts */
+ uint32_t r64_u; /* 140 etherStatsPkts64Octets */
+ uint32_t r64_l; /* 144 etherStatsPkts64Octets */
+ uint32_t r127_u; /* 148 etherStatsPkts65to127Octets */
+ uint32_t r127_l; /* 14c etherStatsPkts65to127Octets */
+ uint32_t r255_u; /* 150 etherStatsPkts128to255Octets */
+ uint32_t r255_l; /* 154 etherStatsPkts128to255Octets */
+ uint32_t r511_u; /* 158 etherStatsPkts256to511Octets */
+ uint32_t r511_l; /* 15c etherStatsPkts256to511Octets */
+ uint32_t r1023_u; /* 160 etherStatsPkts512to1023Octets */
+ uint32_t r1023_l; /* 164 etherStatsPkts512to1023Octets */
+ uint32_t r1518_u; /* 168 etherStatsPkts1024to1518Octets */
+ uint32_t r1518_l; /* 16c etherStatsPkts1024to1518Octets */
+ uint32_t r1519x_u; /* 170 etherStatsPkts1519toX */
+ uint32_t r1519x_l; /* 174 etherStatsPkts1519toX */
+ uint32_t trovr_u; /* 178 etherStatsOversizePkts */
+ uint32_t trovr_l; /* 17c etherStatsOversizePkts */
+ uint32_t trjbr_u; /* 180 etherStatsJabbers */
+ uint32_t trjbr_l; /* 184 etherStatsJabbers */
+ uint32_t trfrg_u; /* 188 etherStatsFragments */
+ uint32_t trfrg_l; /* 18C etherStatsFragments */
+ uint32_t rerr_u; /* 190 if_in_errors */
+ uint32_t rerr_l; /* 194 if_in_errors */
+};
+
+/**
+*struct tgec_cfg - TGEC configuration
+ *
+*@rx_error_discard: Receive Erroneous Frame Discard Enable. When set to 1
+* any frame received with an error is discarded in the
+* Core and not forwarded to the Client interface.
+* When set to 0 (Reset value), erroneous Frames are
+* forwarded to the Client interface with ff_rx_err
+* asserted.
+*@pause_ignore: Ignore Pause Frame Quanta. If set to 1 received pause
+* frames are ignored by the MAC. When set to 0
+* (Reset value) the transmit process is stopped for the
+* amount of time specified in the pause quanta received
+* within a pause frame.
+*@pause_forward_enable:
+* Terminate / Forward Pause Frames. If set to 1 pause
+* frames are forwarded to the user application. When set
+* to 0 (Reset value) pause frames are terminated and
+* discarded within the MAC.
+*@no_length_check_enable:
+* Payload Length Check Disable. When set to 0
+* (Reset value), the Core checks the frame's payload
+* length with the Frame Length/Type field, when set to 1
+* the payload length check is disabled.
+*@cmd_frame_enable: Enables reception of all command frames. When set to 1
+* all Command Frames are accepted, when set to 0
+* (Reset Value) only Pause Frames are accepted and all
+* other Command Frames are rejected.
+*@send_idle_enable: Force Idle Generation. When set to 1, the MAC
+* permanently sends XGMII Idle sequences even when faults
+* are received.
+*@wan_mode_enable: WAN Mode Enable. Sets WAN mode (1) or LAN mode
+* (0, default) of operation.
+*@promiscuous_mode_enable:
+* Enables MAC promiscuous operation. When set to 1, all
+* frames are received without any MAC address filtering,
+* when set to 0 (Reset value) Unicast Frames with a
+* destination address not matching the Core MAC Address
+* (MAC Address programmed in Registers MAC_ADDR_0 and
+* MAC_ADDR_1 or the MAC address programmed in Registers
+* MAC_ADDR_2 and MAC_ADDR_3) are rejected.
+*@tx_addr_ins_enable: Set Source MAC Address on Transmit. If set to 1 the
+* MAC overwrites the source MAC address received from the
+* Client Interface with one of the MAC addresses. If set
+* to 0 (Reset value), the source MAC address from the
+* Client Interface is transmitted unmodified to the line.
+*@loopback_enable: PHY Interface Loopback. When set to 1, the signal
+* loop_ena is set to '1', when set to 0 (Reset value)
+* the signal loop_ena is set to 0.
+*@lgth_check_nostdr: The Core interprets the Length/Type field differently
+* depending on the value of this Bit
+*@time_stamp_enable: This bit selects between enabling and disabling the
+* IEEE 1588 functionality. 1: IEEE 1588 is enabled
+* 0: IEEE 1588 is disabled
+*@max_frame_length: Maximum supported received frame length.
+* The 10GEC MAC supports reception of any frame size up
+* to 16,352 bytes (0x3FE0). Typical settings are
+* 0x05EE (1,518 bytes) for standard frames.
+* Default setting is 0x0600 (1,536 bytes).
+* Received frames that exceed this stated maximum
+* are truncated.
+*@pause_quant: Pause quanta value used with transmitted pause frames.
+* Each quanta represents a 512 bit-times.
+*@tx_ipg_length: Transmit Inter-Packet-Gap (IPG) value. A 6-bit value:
+* Depending on LAN or WAN mode of operation the value has
+* the following meaning: - LAN Mode: Number of octets in
+* steps of 4. Valid values are 8, 12, 16, ... 100. DIC is
+* fully supported (see 10.6.1 page 49) for any setting. A
+* default of 12 (reset value) must be set to conform to
+* IEEE802.3ae. Warning: When set to 8, PCS layers may not
+* be able to perform clock rate compensation. - WAN Mode:
+* Stretch factor. Valid values are 4..15. The stretch
+* factor is calculated as (value+1)*8. A default of 12
+* (reset value) must be set to conform to IEEE 802.3ae
+* (i.e. 13*8=104). A larger value shrinks the IPG
+* (increasing bandwidth).
+ *
+*This structure contains basic TGEC configuration and must be passed to
+*fman_tgec_init() function. A default set of configuration values can be
+*obtained by calling fman_tgec_defconfig().
+ */
+struct tgec_cfg {
+ bool rx_error_discard;
+ bool pause_ignore;
+ bool pause_forward_enable;
+ bool no_length_check_enable;
+ bool cmd_frame_enable;
+ bool send_idle_enable;
+ bool wan_mode_enable;
+ bool promiscuous_mode_enable;
+ bool tx_addr_ins_enable;
+ bool loopback_enable;
+ bool lgth_check_nostdr;
+ bool time_stamp_enable;
+ uint16_t max_frame_length;
+ uint16_t pause_quant;
+ uint32_t tx_ipg_length;
+ bool skip_fman11_workaround;
+};
+
+void fman_tgec_defconfig(struct tgec_cfg *cfg);
+
+/**
+*fman_tgec_init() - Init tgec hardware block
+*@regs: Pointer to tgec register block
+*@cfg: tgec configuration data
+*@exceptions_mask: initial exceptions mask
+ *
+*This function initializes the tgec controller and applies its
+*basic configuration.
+ *
+*Returns: 0 if successful, an error code otherwise.
+ */
+
+int fman_tgec_init(struct tgec_regs __iomem *regs, struct tgec_cfg *cfg,
+ uint32_t exception_mask);
+
+void fman_tgec_enable(struct tgec_regs __iomem *regs, bool apply_rx,
+ bool apply_tx);
+
+void fman_tgec_disable(struct tgec_regs __iomem *regs, bool apply_rx,
+ bool apply_tx);
+
+uint32_t fman_tgec_get_revision(struct tgec_regs __iomem *regs);
+
+void fman_tgec_set_mac_address(struct tgec_regs __iomem *regs,
+ uint8_t *macaddr);
+
+void fman_tgec_set_promiscuous(struct tgec_regs __iomem *regs, bool val);
+
+/**
+*fman_tgec_reset_stat() - Completely resets all TGEC HW counters
+*@regs: Pointer to TGEC register block
+ */
+void fman_tgec_reset_stat(struct tgec_regs __iomem *regs);
+
+/**
+*fman_tgec_get_counter() - Reads TGEC HW counters
+*@regs: Pointer to TGEC register block
+*@reg_name: Counter name according to the appropriate enum
+ *
+*Returns: Required counter value
+ */
+uint64_t fman_tgec_get_counter(struct tgec_regs __iomem *regs,
+ enum tgec_counters reg_name);
+
+/**
+*fman_tgec_set_hash_table() - Sets the Hashtable Control Register
+*@regs: Pointer to TGEC register block
+*@value: Value to be written in Hashtable Control Register
+ */
+void fman_tgec_set_hash_table(struct tgec_regs __iomem *regs, uint32_t value);
+
+/**
+*fman_tgec_set_tx_pause_frames() - Sets the Pause Quanta Register
+*@regs: Pointer to TGEC register block
+*@pause_time: Pause quanta value used with transmitted pause frames.
+* Each quanta represents a 512 bit-times
+ */
+void fman_tgec_set_tx_pause_frames(struct tgec_regs __iomem *regs,
+ uint16_t pause_time);
+
+/**
+*fman_tgec_set_rx_ignore_pause_frames() - Changes the policy WRT pause frames
+*@regs: Pointer to TGEC register block
+*@en: Ignore/Respond to pause frame quanta
+ *
+*Sets the value of PAUSE_IGNORE field in the COMMAND_CONFIG Register
+*0 - MAC stops transmit process for the duration specified
+*in the Pause frame quanta of a received Pause frame.
+*1 - MAC ignores received Pause frames.
+ */
+void fman_tgec_set_rx_ignore_pause_frames(struct tgec_regs __iomem *regs,
+ bool en);
+
+/**
+*fman_tgec_enable_1588_time_stamp() - change timestamp functionality
+*@regs: Pointer to TGEC register block
+*@en: enable/disable timestamp functionality
+ *
+*Sets the value of EN_TIMESTAMP field in the COMMAND_CONFIG Register
+*IEEE 1588 timestamp functionality control:
+*0 disabled, 1 enabled
+ */
+
+void fman_tgec_enable_1588_time_stamp(struct tgec_regs __iomem *regs, bool en);
+
+uint32_t fman_tgec_get_event(struct tgec_regs __iomem *regs, uint32_t ev_mask);
+
+void fman_tgec_ack_event(struct tgec_regs __iomem *regs, uint32_t ev_mask);
+
+uint32_t fman_tgec_get_interrupt_mask(struct tgec_regs __iomem *regs);
+
+/**
+*fman_tgec_add_addr_in_paddr() - Sets additional exact match MAC address
+*@regs: Pointer to TGEC register block
+*@addr_ptr: Pointer to 6-byte array containing the MAC address
+ *
+*Sets the additional station MAC address
+ */
+void fman_tgec_add_addr_in_paddr(struct tgec_regs __iomem *regs,
+ uint8_t *addr_ptr);
+
+void fman_tgec_clear_addr_in_paddr(struct tgec_regs __iomem *regs);
+
+void fman_tgec_enable_interrupt(struct tgec_regs __iomem *regs,
+ uint32_t ev_mask);
+
+void fman_tgec_disable_interrupt(struct tgec_regs __iomem *regs,
+ uint32_t ev_mask);
+
+void fman_tgec_reset_filter_table(struct tgec_regs __iomem *regs);
+
+void fman_tgec_set_hash_table_entry(struct tgec_regs __iomem *regs,
+ uint32_t crc);
+
+/**
+*fman_tgec_get_max_frame_len() - Returns the maximum frame length value
+*@regs: Pointer to TGEC register block
+ */
+uint16_t fman_tgec_get_max_frame_len(struct tgec_regs __iomem *regs);
+
+/**
+*fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007() - Initialize the
+*main tgec configuration parameters
+*@regs: Pointer to TGEC register block
+ *
+*TODO
+ */
+void fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(struct tgec_regs
+ __iomem *regs);
+
+#endif /* __FSL_FMAN_TGEC_H */
--
2.3.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 1/7] soc/fman: Add the FMan FLIB headers
2015-03-05 5:45 ` [PATCH 1/7] soc/fman: Add the FMan FLIB headers Emil Medve
@ 2015-03-06 16:32 ` Kumar Gala
0 siblings, 0 replies; 15+ messages in thread
From: Kumar Gala @ 2015-03-06 16:32 UTC (permalink / raw)
To: Emil Medve; +Cc: netdev, linuxppc-dev, linux-kernel, Igal Liberman
On Mar 4, 2015, at 11:45 PM, Emil Medve <Emilian.Medve@freescale.com> =
wrote:
> From: Igal Liberman <Igal.Liberman@freescale.com>
>=20
> The Freescale Data Path Acceleration Architecture (DPAA) is a set of
> hardware components on specific QorIQ P and T series multicore =
processors.
> This architecture provides the infrastructure to support simplified
> sharing of networking interfaces and accelerators by multiple CPU =
cores,
> and the accelerators themselves.
>=20
> One of the DPAA accelerators is the Frame Manager (FMan), which
> combines the Ethernet network interfaces with packet distribution
> logic to provide intelligent distribution and queuing decisions for
> incoming traffic at line rate.
>=20
> This patch presents the FMan Foundation Libraries (FLIB) headers.
> The FMan FLIB suite adds basic support for the DPAA FMan hardware =
register access.
> The FMan FLIB suite is used in Freescale's SDK Releases.
>=20
> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
> ---
> drivers/soc/fsl/fman/flib/common/general.h | 45 +
> drivers/soc/fsl/fman/flib/fman_common.h | 74 ++
> drivers/soc/fsl/fman/flib/fsl_enet.h | 276 ++++++
> drivers/soc/fsl/fman/flib/fsl_fman.h | 801 =
+++++++++++++++
> drivers/soc/fsl/fman/flib/fsl_fman_dtsec.h | 1017 =
++++++++++++++++++++
> drivers/soc/fsl/fman/flib/fsl_fman_dtsec_mii_acc.h | 104 ++
> drivers/soc/fsl/fman/flib/fsl_fman_kg.h | 506 ++++++++++
> drivers/soc/fsl/fman/flib/fsl_fman_memac.h | 492 ++++++++++
> drivers/soc/fsl/fman/flib/fsl_fman_memac_mii_acc.h | 77 ++
> drivers/soc/fsl/fman/flib/fsl_fman_port.h | 602 ++++++++++++
> drivers/soc/fsl/fman/flib/fsl_fman_prs.h | 106 ++
> drivers/soc/fsl/fman/flib/fsl_fman_rtc.h | 415 ++++++++
> drivers/soc/fsl/fman/flib/fsl_fman_sp.h | 133 +++
> drivers/soc/fsl/fman/flib/fsl_fman_tgec.h | 484 ++++++++++
> 14 files changed, 5132 insertions(+)
> create mode 100644 drivers/soc/fsl/fman/flib/common/general.h
> create mode 100644 drivers/soc/fsl/fman/flib/fman_common.h
> create mode 100644 drivers/soc/fsl/fman/flib/fsl_enet.h
> create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman.h
> create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_dtsec.h
> create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_dtsec_mii_acc.h
> create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_kg.h
> create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_memac.h
> create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_memac_mii_acc.h
> create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_port.h
> create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_prs.h
> create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_rtc.h
> create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_sp.h
> create mode 100644 drivers/soc/fsl/fman/flib/fsl_fman_tgec.h
1. this is way to big of patch to reasonable review
2. can some of these headers be associated with the code patches that =
use them instead
>=20
> diff --git a/drivers/soc/fsl/fman/flib/common/general.h =
b/drivers/soc/fsl/fman/flib/common/general.h
> new file mode 100644
> index 0000000..e5f56af
> --- /dev/null
> +++ b/drivers/soc/fsl/fman/flib/common/general.h
> @@ -0,0 +1,45 @@
> +/*
> + * Copyright 2008-2015 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions =
are met:
> + * * Redistributions of source code must retain the above =
copyright
> + * notice, this list of conditions and the following =
disclaimer.
> + * * Redistributions in binary form must reproduce the above =
copyright
> + * notice, this list of conditions and the following disclaimer =
in the
> + * documentation and/or other materials provided with the =
distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote =
products
> + * derived from this software without specific prior written =
permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of =
the
> + * GNU General Public License ("GPL") as published by the Free =
Software
> + * Foundation, either version 2 of that License or (at your option) =
any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND =
ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE =
IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE =
ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE =
FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL =
DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR =
SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER =
CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, =
OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE =
USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +#ifndef __GENERAL_H
> +#define __GENERAL_H
> +
> +#include <linux/types.h>
> +#include <linux/io.h>
> +
> +#define UNUSED(X) (X =3D X)
Don=92t we already have a kernel mechanism to mark something unused for =
gcc to be quiet?
> +#define KILOBYTE 0x400UL /* 1024 */
Really? I saw one usage, in which you could easily do (5 * 1024).
> +
> +#define iowrite32be(val, addr) out_be32(&(*addr), val)
> +#define ioread32be(addr) in_be32(&(*addr))
> +
> +#endif /* __GENERAL_H */
- k=
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/7] soc/fman: Add the FMan FLIB
2015-03-05 5:45 [PATCH 0/7] Freescale DPAA FMan FLIB(s) Emil Medve
2015-03-05 5:45 ` [PATCH 1/7] soc/fman: Add the FMan FLIB headers Emil Medve
@ 2015-03-05 5:45 ` Emil Medve
2015-03-07 0:57 ` Scott Wood
2015-03-05 5:45 ` [PATCH 3/7] soc/fman: Add the FMan port FLIB Emil Medve
` (5 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Emil Medve @ 2015-03-05 5:45 UTC (permalink / raw)
To: linuxppc-dev, netdev, linux-kernel; +Cc: Igal Liberman
From: Igal Liberman <Igal.Liberman@freescale.com>
Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/fsl/Kconfig | 1 +
drivers/soc/fsl/Makefile | 1 +
drivers/soc/fsl/fman/Kconfig | 7 +
drivers/soc/fsl/fman/Makefile | 13 +
drivers/soc/fsl/fman/fman.c | 1396 +++++++++++++++++++++++++++++++++++++++++
7 files changed, 1420 insertions(+)
create mode 100644 drivers/soc/fsl/Kconfig
create mode 100644 drivers/soc/fsl/Makefile
create mode 100644 drivers/soc/fsl/fman/Kconfig
create mode 100644 drivers/soc/fsl/fman/Makefile
create mode 100644 drivers/soc/fsl/fman/fman.c
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 76d6bd4..674a6e6 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -1,5 +1,6 @@
menu "SOC (System On Chip) specific Drivers"
+source "drivers/soc/fsl/Kconfig"
source "drivers/soc/qcom/Kconfig"
source "drivers/soc/ti/Kconfig"
source "drivers/soc/versatile/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 063113d..42836ee 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
# Makefile for the Linux Kernel SOC specific device drivers.
#
+obj-$(CONFIG_FSL_SOC) += fsl/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_SOC_TI) += ti/
diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig
new file mode 100644
index 0000000..38c08ae
--- /dev/null
+++ b/drivers/soc/fsl/Kconfig
@@ -0,0 +1 @@
+source "drivers/soc/fsl/fman/Kconfig"
diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile
new file mode 100644
index 0000000..97d715c
--- /dev/null
+++ b/drivers/soc/fsl/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_FSL_FMAN) += fman/
diff --git a/drivers/soc/fsl/fman/Kconfig b/drivers/soc/fsl/fman/Kconfig
new file mode 100644
index 0000000..e5009a9
--- /dev/null
+++ b/drivers/soc/fsl/fman/Kconfig
@@ -0,0 +1,7 @@
+menuconfig FSL_FMAN
+ tristate "Freescale DPAA Frame Manager"
+ depends on FSL_SOC || COMPILE_TEST
+ default n
+ help
+ Freescale Data-Path Acceleration Architecture Frame Manager
+ (FMan) support
diff --git a/drivers/soc/fsl/fman/Makefile b/drivers/soc/fsl/fman/Makefile
new file mode 100644
index 0000000..d7fbecb
--- /dev/null
+++ b/drivers/soc/fsl/fman/Makefile
@@ -0,0 +1,13 @@
+ccflags-y += -DVERSION=\"\"
+
+ifeq ($(CONFIG_FSL_FMAN),y)
+
+FMAN = $(srctree)/drivers/soc/fsl/fman
+
+ccflags-y += -I$(FMAN)/flib
+
+obj-$(CONFIG_FSL_FMAN) += fsl_fman.o
+
+fsl_fman-objs := fman.o
+
+endif
diff --git a/drivers/soc/fsl/fman/fman.c b/drivers/soc/fsl/fman/fman.c
new file mode 100644
index 0000000..dbf2cd3
--- /dev/null
+++ b/drivers/soc/fsl/fman/fman.c
@@ -0,0 +1,1396 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fman.h"
+
+uint32_t fman_get_bmi_err_event(struct fman_bmi_regs __iomem *bmi_rg)
+{
+ uint32_t event, mask, force;
+
+ event = ioread32be(&bmi_rg->fmbm_ievr);
+ mask = ioread32be(&bmi_rg->fmbm_ier);
+ event &= mask;
+ /* clear the forced events */
+ force = ioread32be(&bmi_rg->fmbm_ifr);
+ if (force & event)
+ iowrite32be(force & ~event, &bmi_rg->fmbm_ifr);
+ /* clear the acknowledged events */
+ iowrite32be(event, &bmi_rg->fmbm_ievr);
+ return event;
+}
+
+uint32_t fman_get_qmi_err_event(struct fman_qmi_regs __iomem *qmi_rg)
+{
+ uint32_t event, mask, force;
+
+ event = ioread32be(&qmi_rg->fmqm_eie);
+ mask = ioread32be(&qmi_rg->fmqm_eien);
+ event &= mask;
+
+ /* clear the forced events */
+ force = ioread32be(&qmi_rg->fmqm_eif);
+ if (force & event)
+ iowrite32be(force & ~event, &qmi_rg->fmqm_eif);
+ /* clear the acknowledged events */
+ iowrite32be(event, &qmi_rg->fmqm_eie);
+ return event;
+}
+
+uint32_t fman_get_dma_com_id(struct fman_dma_regs __iomem *dma_rg)
+{
+ return ioread32be(&dma_rg->fmdmtcid);
+}
+
+uint64_t fman_get_dma_addr(struct fman_dma_regs __iomem *dma_rg)
+{
+ uint64_t addr;
+
+ addr = (uint64_t)ioread32be(&dma_rg->fmdmtal);
+ addr |= ((uint64_t)(ioread32be(&dma_rg->fmdmtah)) << 32);
+
+ return addr;
+}
+
+uint32_t fman_get_dma_err_event(struct fman_dma_regs __iomem *dma_rg)
+{
+ uint32_t status, mask;
+
+ status = ioread32be(&dma_rg->fmdmsr);
+ mask = ioread32be(&dma_rg->fmdmmr);
+
+ /* clear DMA_STATUS_BUS_ERR if mask has no DMA_MODE_BER */
+ if ((mask & DMA_MODE_BER) != DMA_MODE_BER)
+ status &= ~DMA_STATUS_BUS_ERR;
+
+ /* clear relevant bits if mask has no DMA_MODE_ECC */
+ if ((mask & DMA_MODE_ECC) != DMA_MODE_ECC)
+ status &= ~(DMA_STATUS_FM_SPDAT_ECC |
+ DMA_STATUS_READ_ECC |
+ DMA_STATUS_SYSTEM_WRITE_ECC |
+ DMA_STATUS_FM_WRITE_ECC);
+
+ /* clear set events */
+ iowrite32be(status, &dma_rg->fmdmsr);
+
+ return status;
+}
+
+uint32_t fman_get_fpm_err_event(struct fman_fpm_regs __iomem *fpm_rg)
+{
+ uint32_t event;
+
+ event = ioread32be(&fpm_rg->fmfp_ee);
+ /* clear the all occurred events */
+ iowrite32be(event, &fpm_rg->fmfp_ee);
+ return event;
+}
+
+uint32_t fman_get_muram_err_event(struct fman_fpm_regs __iomem *fpm_rg)
+{
+ uint32_t event, mask;
+
+ event = ioread32be(&fpm_rg->fm_rcr);
+ mask = ioread32be(&fpm_rg->fm_rie);
+
+ /* clear MURAM event bit (do not clear IRAM event) */
+ iowrite32be(event & ~FPM_RAM_IRAM_ECC, &fpm_rg->fm_rcr);
+
+ if ((mask & FPM_MURAM_ECC_ERR_EX_EN))
+ return event;
+ else
+ return 0;
+}
+
+uint32_t fman_get_iram_err_event(struct fman_fpm_regs __iomem *fpm_rg)
+{
+ uint32_t event, mask;
+
+ event = ioread32be(&fpm_rg->fm_rcr);
+ mask = ioread32be(&fpm_rg->fm_rie);
+ /* clear IRAM event bit (do not clear MURAM event) */
+ iowrite32be(event & ~FPM_RAM_MURAM_ECC, &fpm_rg->fm_rcr);
+
+ if ((mask & FPM_IRAM_ECC_ERR_EX_EN))
+ return event;
+ else
+ return 0;
+}
+
+uint32_t fman_get_qmi_event(struct fman_qmi_regs __iomem *qmi_rg)
+{
+ uint32_t event, mask, force;
+
+ event = ioread32be(&qmi_rg->fmqm_ie);
+ mask = ioread32be(&qmi_rg->fmqm_ien);
+ event &= mask;
+ /* clear the forced events */
+ force = ioread32be(&qmi_rg->fmqm_if);
+ if (force & event)
+ iowrite32be(force & ~event, &qmi_rg->fmqm_if);
+ /* clear the acknowledged events */
+ iowrite32be(event, &qmi_rg->fmqm_ie);
+ return event;
+}
+
+void fman_enable_time_stamp(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t count1ubit, uint16_t fm_clk_freq)
+{
+ uint32_t tmp;
+ uint64_t frac;
+ uint32_t intgr;
+ uint32_t ts_freq = (uint32_t)(1 << count1ubit); /* in Mhz */
+
+ /* configure timestamp so that bit 8 will count 1 microsecond
+ * Find effective count rate at TIMESTAMP least significant bits:
+ * Effective_Count_Rate = 1MHz x 2^8 = 256MHz
+ * Find frequency ratio between effective count rate and the clock:
+ * Effective_Count_Rate / CLK e.g. for 600 MHz clock:
+ * 256/600 = 0.4266666...
+ */
+
+ intgr = ts_freq / fm_clk_freq;
+ /* we multiply by 2^16 to keep the fraction of the division
+ * we do not div back, since we write this value as a fraction
+ * see spec
+ */
+
+ frac = ((ts_freq << 16) - (intgr << 16) * fm_clk_freq) / fm_clk_freq;
+ /* we check remainder of the division in order to round up if not int */
+ if (((ts_freq << 16) - (intgr << 16) * fm_clk_freq) % fm_clk_freq)
+ frac++;
+
+ tmp = (intgr << FPM_TS_INT_SHIFT) | (uint16_t)frac;
+ iowrite32be(tmp, &fpm_rg->fmfp_tsc2);
+
+ /* enable timestamp with original clock */
+ iowrite32be(FPM_TS_CTL_EN, &fpm_rg->fmfp_tsc1);
+}
+
+uint32_t fman_get_fpm_error_interrupts(struct fman_fpm_regs __iomem *fpm_rg)
+{
+ return ioread32be(&fpm_rg->fm_epi);
+}
+
+int fman_set_erratum_10gmac_a004_wa(struct fman_fpm_regs __iomem *fpm_rg)
+{
+ int timeout = 100;
+
+ iowrite32be(0x40000000, &fpm_rg->fmfp_extc);
+
+ while ((ioread32be(&fpm_rg->fmfp_extc) & 0x40000000) && --timeout)
+ usleep_range(10, 11);
+
+ if (!timeout)
+ return -EBUSY;
+ return 0;
+}
+
+void fman_set_ctrl_intr(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t event_reg_id, uint32_t enable_events)
+{
+ iowrite32be(enable_events, &fpm_rg->fmfp_cee[event_reg_id]);
+}
+
+uint32_t fman_get_ctrl_intr(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t event_reg_id)
+{
+ return ioread32be(&fpm_rg->fmfp_cee[event_reg_id]);
+}
+
+void fman_set_num_of_riscs_per_port(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t port_id,
+ uint8_t num_fman_ctrls,
+ uint32_t or_fman_ctrl)
+{
+ uint32_t tmp = 0;
+
+ tmp = (uint32_t)(port_id << FPM_PORT_FM_CTL_PORTID_SHIFT);
+ /*TODO - maybe to put CTL# according to another criteria */
+ if (num_fman_ctrls == 2)
+ tmp = FPM_PRT_FM_CTL2 | FPM_PRT_FM_CTL1;
+ /* order restoration */
+ tmp |= (or_fman_ctrl << FPM_PRC_ORA_FM_CTL_SEL_SHIFT) | or_fman_ctrl;
+
+ iowrite32be(tmp, &fpm_rg->fmfp_prc);
+}
+
+void fman_set_order_restoration_per_port(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t port_id, bool is_rx_port)
+{
+ uint32_t tmp = 0;
+
+ tmp = (uint32_t)(port_id << FPM_PORT_FM_CTL_PORTID_SHIFT);
+
+ tmp |= (FPM_PRT_FM_CTL2 | FPM_PRT_FM_CTL1);
+
+ /* order restoration */
+ if (port_id % 2)
+ tmp |= (FPM_PRT_FM_CTL1 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT);
+ else
+ tmp |= (FPM_PRT_FM_CTL2 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT);
+
+ iowrite32be(tmp, &fpm_rg->fmfp_prc);
+}
+
+uint8_t fman_get_qmi_deq_th(struct fman_qmi_regs __iomem *qmi_rg)
+{
+ return (uint8_t)ioread32be(&qmi_rg->fmqm_gc);
+}
+
+uint8_t fman_get_qmi_enq_th(struct fman_qmi_regs __iomem *qmi_rg)
+{
+ return (uint8_t)(ioread32be(&qmi_rg->fmqm_gc) >> 8);
+}
+
+void fman_set_qmi_enq_th(struct fman_qmi_regs __iomem *qmi_rg, uint8_t val)
+{
+ uint32_t tmp_reg;
+
+ tmp_reg = ioread32be(&qmi_rg->fmqm_gc);
+ tmp_reg &= ~QMI_CFG_ENQ_MASK;
+ tmp_reg |= ((uint32_t)val << 8);
+ iowrite32be(tmp_reg, &qmi_rg->fmqm_gc);
+}
+
+void fman_set_qmi_deq_th(struct fman_qmi_regs __iomem *qmi_rg, uint8_t val)
+{
+ uint32_t tmp_reg;
+
+ tmp_reg = ioread32be(&qmi_rg->fmqm_gc);
+ tmp_reg &= ~QMI_CFG_DEQ_MASK;
+ tmp_reg |= (uint32_t)val;
+ iowrite32be(tmp_reg, &qmi_rg->fmqm_gc);
+}
+
+void fman_qmi_disable_dispatch_limit(struct fman_fpm_regs __iomem *fpm_rg)
+{
+ iowrite32be(0, &fpm_rg->fmfp_mxd);
+}
+
+void fman_set_liodn_per_port(struct fman_rg *fman_rg, uint8_t port_id,
+ uint16_t liodn_base, uint16_t liodn_ofst)
+{
+ uint32_t tmp;
+
+ if ((port_id > 63) || (port_id < 1))
+ return;
+
+ /* set LIODN base for this port */
+ tmp = ioread32be(&fman_rg->dma_rg->fmdmplr[port_id / 2]);
+ if (port_id % 2) {
+ tmp &= ~FM_LIODN_BASE_MASK;
+ tmp |= (uint32_t)liodn_base;
+ } else {
+ tmp &= ~(FM_LIODN_BASE_MASK << DMA_LIODN_SHIFT);
+ tmp |= (uint32_t)liodn_base << DMA_LIODN_SHIFT;
+ }
+ iowrite32be(tmp, &fman_rg->dma_rg->fmdmplr[port_id / 2]);
+ iowrite32be((uint32_t)liodn_ofst,
+ &fman_rg->bmi_rg->fmbm_spliodn[port_id - 1]);
+}
+
+bool fman_is_port_stalled(struct fman_fpm_regs __iomem *fpm_rg, uint8_t port_id)
+{
+ return (bool)!!(ioread32be(&fpm_rg->fmfp_ps[port_id]) &
+ FPM_PS_STALLED);
+}
+
+void fman_resume_stalled_port(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t port_id)
+{
+ uint32_t tmp;
+
+ tmp = (uint32_t)((port_id << FPM_PORT_FM_CTL_PORTID_SHIFT) |
+ FPM_PRC_REALSE_STALLED);
+ iowrite32be(tmp, &fpm_rg->fmfp_prc);
+}
+
+int fman_reset_mac(struct fman_fpm_regs __iomem *fpm_rg, uint8_t mac_id)
+{
+ uint32_t msk, timeout = 100;
+
+ /* Get the relevant bit mask */
+ switch (mac_id) {
+ case (0):
+ msk = FPM_RSTC_MAC0_RESET;
+ break;
+ case (1):
+ msk = FPM_RSTC_MAC1_RESET;
+ break;
+ case (2):
+ msk = FPM_RSTC_MAC2_RESET;
+ break;
+ case (3):
+ msk = FPM_RSTC_MAC3_RESET;
+ break;
+ case (4):
+ msk = FPM_RSTC_MAC4_RESET;
+ break;
+ case (5):
+ msk = FPM_RSTC_MAC5_RESET;
+ break;
+ case (6):
+ msk = FPM_RSTC_MAC6_RESET;
+ break;
+ case (7):
+ msk = FPM_RSTC_MAC7_RESET;
+ break;
+ case (8):
+ msk = FPM_RSTC_MAC8_RESET;
+ break;
+ case (9):
+ msk = FPM_RSTC_MAC9_RESET;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* reset */
+ iowrite32be(msk, &fpm_rg->fm_rstc);
+ while ((ioread32be(&fpm_rg->fm_rstc) & msk) && --timeout)
+ usleep_range(10, 11);
+
+ if (!timeout)
+ return -EBUSY;
+ return 0;
+}
+
+uint16_t fman_get_size_of_fifo(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id)
+{
+ uint32_t tmp_reg;
+
+ if ((port_id > 63) || (port_id < 1))
+ return 0;
+
+ tmp_reg = ioread32be(&bmi_rg->fmbm_pfs[port_id - 1]);
+ return (uint16_t)((tmp_reg & BMI_FIFO_SIZE_MASK) + 1);
+}
+
+uint32_t fman_get_total_fifo_size(struct fman_bmi_regs __iomem *bmi_rg)
+{
+ uint32_t reg, res;
+
+ reg = ioread32be(&bmi_rg->fmbm_cfg1);
+ res = (reg >> BMI_CFG1_FIFO_SIZE_SHIFT) & 0x3ff;
+ return res * FMAN_BMI_FIFO_UNITS;
+}
+
+uint16_t fman_get_size_of_extra_fifo(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id)
+{
+ uint32_t tmp_reg;
+
+ if ((port_id > 63) || (port_id < 1))
+ return 0;
+
+ tmp_reg = ioread32be(&bmi_rg->fmbm_pfs[port_id - 1]);
+ return (uint16_t)((tmp_reg & BMI_EXTRA_FIFO_SIZE_MASK) >>
+ BMI_EXTRA_FIFO_SIZE_SHIFT);
+}
+
+void fman_set_size_of_fifo(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id, uint32_t sz_fifo,
+ uint32_t extra_sz_fifo)
+{
+ uint32_t tmp;
+
+ if ((port_id > 63) || (port_id < 1))
+ return;
+
+ /* calculate reg */
+ tmp = (uint32_t)((sz_fifo / FMAN_BMI_FIFO_UNITS - 1) |
+ ((extra_sz_fifo / FMAN_BMI_FIFO_UNITS) <<
+ BMI_EXTRA_FIFO_SIZE_SHIFT));
+ iowrite32be(tmp, &bmi_rg->fmbm_pfs[port_id - 1]);
+}
+
+uint8_t fman_get_num_of_tasks(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id)
+{
+ uint32_t tmp;
+
+ if ((port_id > 63) || (port_id < 1))
+ return 0;
+
+ tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
+ return (uint8_t)(((tmp & BMI_NUM_OF_TASKS_MASK) >>
+ BMI_NUM_OF_TASKS_SHIFT) + 1);
+}
+
+uint8_t fman_get_num_extra_tasks(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id)
+{
+ uint32_t tmp;
+
+ if ((port_id > 63) || (port_id < 1))
+ return 0;
+
+ tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
+ return (uint8_t)((tmp & BMI_NUM_OF_EXTRA_TASKS_MASK) >>
+ BMI_EXTRA_NUM_OF_TASKS_SHIFT);
+}
+
+void fman_set_num_of_tasks(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id, uint8_t num_tasks,
+ uint8_t num_extra_tasks)
+{
+ uint32_t tmp;
+
+ if ((port_id > 63) || (port_id < 1))
+ return;
+
+ /* calculate reg */
+ tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
+ ~(BMI_NUM_OF_TASKS_MASK | BMI_NUM_OF_EXTRA_TASKS_MASK);
+ tmp |= (uint32_t)(((num_tasks - 1) << BMI_NUM_OF_TASKS_SHIFT) |
+ (num_extra_tasks << BMI_EXTRA_NUM_OF_TASKS_SHIFT));
+ iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
+}
+
+uint8_t fman_get_num_of_dmas(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id)
+{
+ uint32_t tmp;
+
+ if ((port_id > 63) || (port_id < 1))
+ return 0;
+
+ tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
+ return (uint8_t)(((tmp & BMI_NUM_OF_DMAS_MASK) >>
+ BMI_NUM_OF_DMAS_SHIFT) + 1);
+}
+
+uint8_t fman_get_num_extra_dmas(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id)
+{
+ uint32_t tmp;
+
+ if ((port_id > 63) || (port_id < 1))
+ return 0;
+
+ tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
+ return (uint8_t)((tmp & BMI_NUM_OF_EXTRA_DMAS_MASK) >>
+ BMI_EXTRA_NUM_OF_DMAS_SHIFT);
+}
+
+void fman_set_num_of_open_dmas(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id, uint8_t num_open_dmas,
+ uint8_t num_extra_open_dmas,
+ uint8_t total_num_dmas)
+{
+ uint32_t tmp = 0;
+
+ if ((port_id > 63) || (port_id < 1))
+ return;
+
+ /* calculate reg */
+ tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
+ ~(BMI_NUM_OF_DMAS_MASK | BMI_NUM_OF_EXTRA_DMAS_MASK);
+ tmp |= (uint32_t)(((num_open_dmas - 1) << BMI_NUM_OF_DMAS_SHIFT) |
+ (num_extra_open_dmas <<
+ BMI_EXTRA_NUM_OF_DMAS_SHIFT));
+ iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
+
+ /* update total num of DMA's with committed number of open DMAS,
+ * and max uncommitted pool.
+ */
+ if (total_num_dmas) {
+ tmp = ioread32be(&bmi_rg->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK;
+ tmp |= (uint32_t)(total_num_dmas - 1) << BMI_CFG2_DMAS_SHIFT;
+ iowrite32be(tmp, &bmi_rg->fmbm_cfg2);
+ }
+}
+
+void fman_set_vsp_window(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t port_id,
+ uint8_t base_storage_profile,
+ uint8_t log2_num_of_profiles)
+{
+ uint32_t tmp = 0;
+
+ if ((port_id > 63) || (port_id < 1))
+ return;
+
+ tmp = ioread32be(&bmi_rg->fmbm_spliodn[port_id - 1]);
+ tmp |= (uint32_t)((uint32_t)base_storage_profile & 0x3f) << 16;
+ tmp |= (uint32_t)log2_num_of_profiles << 28;
+ iowrite32be(tmp, &bmi_rg->fmbm_spliodn[port_id - 1]);
+}
+
+void fman_set_congestion_group_pfc_priority(uint32_t __iomem *cpg_rg,
+ uint32_t congestion_group_id,
+ uint8_t priority_bit_map,
+ uint32_t reg_num)
+{
+ uint32_t offset, tmp = 0;
+
+ offset = (congestion_group_id % 4) * 8;
+
+ tmp = ioread32be(&cpg_rg[reg_num]);
+ tmp &= ~(0xFF << offset);
+ tmp |= (uint32_t)priority_bit_map << offset;
+
+ iowrite32be(tmp, &cpg_rg[reg_num]);
+}
+
+/* API Init unit functions */
+
+void fman_defconfig(struct fman_cfg *cfg)
+{
+ memset(cfg, 0, sizeof(struct fman_cfg));
+
+ cfg->catastrophic_err = DEFAULT_CATASTROPHIC_ERR;
+ cfg->dma_err = DEFAULT_DMA_ERR;
+ cfg->halt_on_external_activ = DEFAULT_HALT_ON_EXTERNAL_ACTIVATION;
+ cfg->halt_on_unrecov_ecc_err = DEFAULT_HALT_ON_UNRECOVERABLE_ECC_ERROR;
+ cfg->en_iram_test_mode = false;
+ cfg->en_muram_test_mode = false;
+ cfg->external_ecc_rams_enable = DEFAULT_EXTERNAL_ECC_RAMS_ENABLE;
+
+ cfg->dma_aid_override = DEFAULT_AID_OVERRIDE;
+ cfg->dma_aid_mode = DEFAULT_AID_MODE;
+ cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW;
+ cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH;
+ cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE;
+ cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES;
+ cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE;
+ cfg->dma_en_emergency = DEFAULT_DMA_EN_EMERGENCY;
+ cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY;
+ cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG;
+ cfg->dma_en_emergency_smoother = DEFAULT_DMA_EN_EMERGENCY_SMOOTHER;
+ cfg->dma_emergency_switch_counter =
+ DEFAULT_DMA_EMERGENCY_SWITCH_COUNTER;
+ cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT;
+ cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH;
+ cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH;
+ cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH;
+ cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH;
+ cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH;
+ cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH;
+ cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH;
+ cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH;
+
+ cfg->pedantic_dma = false;
+ cfg->tnum_aging_period = DEFAULT_TNUM_AGING_PERIOD;
+ cfg->dma_stop_on_bus_error = false;
+ cfg->qmi_deq_option_support = false;
+}
+
+void fman_regconfig(struct fman_rg *fman_rg, struct fman_cfg *cfg)
+{
+ uint32_t tmp_reg;
+
+ /* read the values from the registers as they
+ * are initialized by the HW with
+ * the required values.
+ */
+ tmp_reg = ioread32be(&fman_rg->bmi_rg->fmbm_cfg1);
+ cfg->total_fifo_size =
+ (((tmp_reg & BMI_TOTAL_FIFO_SIZE_MASK) >>
+ BMI_CFG1_FIFO_SIZE_SHIFT) + 1) * FMAN_BMI_FIFO_UNITS;
+
+ tmp_reg = ioread32be(&fman_rg->bmi_rg->fmbm_cfg2);
+ cfg->total_num_of_tasks =
+ (uint8_t)(((tmp_reg & BMI_TOTAL_NUM_OF_TASKS_MASK) >>
+ BMI_CFG2_TASKS_SHIFT) + 1);
+
+ tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmtr);
+ cfg->dma_comm_qtsh_asrt_emer =
+ (uint8_t)(tmp_reg >> DMA_THRESH_COMMQ_SHIFT);
+
+ tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmhy);
+ cfg->dma_comm_qtsh_clr_emer =
+ (uint8_t)(tmp_reg >> DMA_THRESH_COMMQ_SHIFT);
+
+ tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmmr);
+ cfg->dma_cache_override = (enum fman_dma_cache_override)
+ ((tmp_reg & DMA_MODE_CACHE_OR_MASK) >> DMA_MODE_CACHE_OR_SHIFT);
+ cfg->dma_cam_num_of_entries =
+ (uint8_t)((((tmp_reg & DMA_MODE_CEN_MASK) >>
+ DMA_MODE_CEN_SHIFT) + 1) * DMA_CAM_UNITS);
+ cfg->dma_aid_override =
+ (bool)((tmp_reg & DMA_MODE_AID_OR) ? true : false);
+ cfg->dma_dbg_cnt_mode =
+ (enum fman_dma_dbg_cnt_mode)((tmp_reg & DMA_MODE_DBG_MASK) >>
+ DMA_MODE_DBG_SHIFT);
+ cfg->dma_en_emergency = (bool)((tmp_reg & DMA_MODE_EB) ? true : false);
+
+ tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_mxd);
+ cfg->disp_limit_tsh =
+ (uint8_t)((tmp_reg & FPM_DISP_LIMIT_MASK) >> FPM_DISP_LIMIT_SHIFT);
+
+ tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_dist1);
+ cfg->prs_disp_tsh =
+ (uint8_t)((tmp_reg & FPM_THR1_PRS_MASK) >> FPM_THR1_PRS_SHIFT);
+ cfg->plcr_disp_tsh =
+ (uint8_t)((tmp_reg & FPM_THR1_KG_MASK) >> FPM_THR1_KG_SHIFT);
+ cfg->kg_disp_tsh =
+ (uint8_t)((tmp_reg & FPM_THR1_PLCR_MASK) >> FPM_THR1_PLCR_SHIFT);
+ cfg->bmi_disp_tsh =
+ (uint8_t)((tmp_reg & FPM_THR1_BMI_MASK) >> FPM_THR1_BMI_SHIFT);
+
+ tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_dist2);
+ cfg->qmi_enq_disp_tsh =
+ (uint8_t)((tmp_reg & FPM_THR2_QMI_ENQ_MASK) >>
+ FPM_THR2_QMI_ENQ_SHIFT);
+ cfg->qmi_deq_disp_tsh =
+ (uint8_t)((tmp_reg & FPM_THR2_QMI_DEQ_MASK) >>
+ FPM_THR2_QMI_DEQ_SHIFT);
+ cfg->fm_ctl1_disp_tsh =
+ (uint8_t)((tmp_reg & FPM_THR2_FM_CTL1_MASK) >>
+ FPM_THR2_FM_CTL1_SHIFT);
+ cfg->fm_ctl2_disp_tsh =
+ (uint8_t)((tmp_reg & FPM_THR2_FM_CTL2_MASK) >>
+ FPM_THR2_FM_CTL2_SHIFT);
+
+ tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmsetr);
+ cfg->dma_sos_emergency = tmp_reg;
+
+ tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmwcr);
+ cfg->dma_watchdog = tmp_reg / cfg->clk_freq;
+
+ tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmemsr);
+ cfg->dma_en_emergency_smoother =
+ (bool)((tmp_reg & DMA_EMSR_EMSTR_MASK) ? true : false);
+ cfg->dma_emergency_switch_counter = (tmp_reg & DMA_EMSR_EMSTR_MASK);
+}
+
+void fman_reset(struct fman_fpm_regs __iomem *fpm_rg)
+{
+ iowrite32be(FPM_RSTC_FM_RESET, &fpm_rg->fm_rstc);
+}
+
+/* fm_init
+ * Initializes the FM module
+ * h_fm - FM module descriptor
+ * Return 0 on success; Error code otherwise.
+ */
+int fman_dma_init(struct fman_dma_regs __iomem *dma_rg, struct fman_cfg *cfg)
+{
+ uint32_t tmp_reg;
+
+ /* Init DMA Registers */
+
+ /* clear status reg events */
+ /* oren - check!!! */
+ tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC |
+ DMA_STATUS_SYSTEM_WRITE_ECC | DMA_STATUS_FM_WRITE_ECC);
+ iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, &dma_rg->fmdmsr);
+
+ /* configure mode register */
+ tmp_reg = 0;
+ tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT;
+ if (cfg->dma_aid_override)
+ tmp_reg |= DMA_MODE_AID_OR;
+ if (cfg->exceptions & FMAN_EX_DMA_BUS_ERROR)
+ tmp_reg |= DMA_MODE_BER;
+ if ((cfg->exceptions & FMAN_EX_DMA_SYSTEM_WRITE_ECC) |
+ (cfg->exceptions & FMAN_EX_DMA_READ_ECC) |
+ (cfg->exceptions & FMAN_EX_DMA_FM_WRITE_ECC))
+ tmp_reg |= DMA_MODE_ECC;
+ if (cfg->dma_stop_on_bus_error)
+ tmp_reg |= DMA_MODE_SBER;
+ if (cfg->dma_axi_dbg_num_of_beats)
+ tmp_reg |= (uint32_t)(DMA_MODE_AXI_DBG_MASK &
+ ((cfg->dma_axi_dbg_num_of_beats -
+ 1) << DMA_MODE_AXI_DBG_SHIFT));
+
+ if (cfg->dma_en_emergency) {
+ tmp_reg |= cfg->dma_emergency_bus_select;
+ tmp_reg |= cfg->dma_emergency_level << DMA_MODE_EMER_LVL_SHIFT;
+ if (cfg->dma_en_emergency_smoother)
+ iowrite32be(cfg->dma_emergency_switch_counter,
+ &dma_rg->fmdmemsr);
+ }
+ tmp_reg |= ((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) <<
+ DMA_MODE_CEN_SHIFT;
+ tmp_reg |= DMA_MODE_SECURE_PROT;
+ tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT;
+ tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT;
+
+ if (cfg->pedantic_dma)
+ tmp_reg |= DMA_MODE_EMER_READ;
+
+ iowrite32be(tmp_reg, &dma_rg->fmdmmr);
+
+ /* configure thresholds register */
+ tmp_reg = ((uint32_t)cfg->dma_comm_qtsh_asrt_emer <<
+ DMA_THRESH_COMMQ_SHIFT) |
+ ((uint32_t)cfg->dma_read_buf_tsh_asrt_emer <<
+ DMA_THRESH_READ_INT_BUF_SHIFT) |
+ ((uint32_t)cfg->dma_write_buf_tsh_asrt_emer);
+
+ iowrite32be(tmp_reg, &dma_rg->fmdmtr);
+
+ /* configure hysteresis register */
+ tmp_reg = ((uint32_t)cfg->dma_comm_qtsh_clr_emer <<
+ DMA_THRESH_COMMQ_SHIFT) |
+ ((uint32_t)cfg->dma_read_buf_tsh_clr_emer <<
+ DMA_THRESH_READ_INT_BUF_SHIFT) |
+ ((uint32_t)cfg->dma_write_buf_tsh_clr_emer);
+
+ iowrite32be(tmp_reg, &dma_rg->fmdmhy);
+
+ /* configure emergency threshold */
+ iowrite32be(cfg->dma_sos_emergency, &dma_rg->fmdmsetr);
+
+ /* configure Watchdog */
+ iowrite32be((cfg->dma_watchdog * cfg->clk_freq), &dma_rg->fmdmwcr);
+
+ iowrite32be(cfg->cam_base_addr, &dma_rg->fmdmebcr);
+
+ return 0;
+}
+
+int fman_fpm_init(struct fman_fpm_regs __iomem *fpm_rg, struct fman_cfg *cfg)
+{
+ uint32_t tmp_reg;
+ int i;
+
+ /* Init FPM Registers */
+
+ tmp_reg = (uint32_t)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT);
+ iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd);
+
+ tmp_reg = (((uint32_t)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) |
+ ((uint32_t)cfg->kg_disp_tsh << FPM_THR1_KG_SHIFT) |
+ ((uint32_t)cfg->plcr_disp_tsh << FPM_THR1_PLCR_SHIFT) |
+ ((uint32_t)cfg->bmi_disp_tsh << FPM_THR1_BMI_SHIFT));
+ iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1);
+
+ tmp_reg =
+ (((uint32_t)cfg->
+ qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) |
+ ((uint32_t)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT)
+ | ((uint32_t)cfg->
+ fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) |
+ ((uint32_t)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT));
+ iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2);
+
+ /* define exceptions and error behavior */
+ tmp_reg = 0;
+ /* Clear events */
+ tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC |
+ FPM_EV_MASK_SINGLE_ECC);
+ /* enable interrupts */
+ if (cfg->exceptions & FMAN_EX_FPM_STALL_ON_TASKS)
+ tmp_reg |= FPM_EV_MASK_STALL_EN;
+ if (cfg->exceptions & FMAN_EX_FPM_SINGLE_ECC)
+ tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN;
+ if (cfg->exceptions & FMAN_EX_FPM_DOUBLE_ECC)
+ tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN;
+ tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT);
+ tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT);
+ if (!cfg->halt_on_external_activ)
+ tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT;
+ if (!cfg->halt_on_unrecov_ecc_err)
+ tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT;
+ iowrite32be(tmp_reg, &fpm_rg->fmfp_ee);
+
+ /* clear all fmCtls event registers */
+ for (i = 0; i < cfg->num_of_fman_ctrl_evnt_regs; i++)
+ iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]);
+
+ /* RAM ECC - enable and clear events */
+ /* first we need to clear all parser memory,
+ * as it is uninitialized and may cause ECC errors
+ */
+ /* event bits */
+ tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC);
+ /* Rams enable not effected by RCR bit,
+ * but by a COP configuration
+ */
+ if (cfg->external_ecc_rams_enable)
+ tmp_reg |= FPM_RAM_RAMS_ECC_EN_SRC_SEL;
+
+ /* enable test mode */
+ if (cfg->en_muram_test_mode)
+ tmp_reg |= FPM_RAM_MURAM_TEST_ECC;
+ if (cfg->en_iram_test_mode)
+ tmp_reg |= FPM_RAM_IRAM_TEST_ECC;
+ iowrite32be(tmp_reg, &fpm_rg->fm_rcr);
+
+ tmp_reg = 0;
+ if (cfg->exceptions & FMAN_EX_IRAM_ECC) {
+ tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN;
+ fman_enable_rams_ecc(fpm_rg);
+ }
+ if (cfg->exceptions & FMAN_EX_NURAM_ECC) {
+ tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN;
+ fman_enable_rams_ecc(fpm_rg);
+ }
+ iowrite32be(tmp_reg, &fpm_rg->fm_rie);
+
+ return 0;
+}
+
+int fman_bmi_init(struct fman_bmi_regs __iomem *bmi_rg, struct fman_cfg *cfg)
+{
+ uint32_t tmp_reg;
+
+ /* Init BMI Registers */
+
+ /* define common resources */
+ tmp_reg = cfg->fifo_base_addr;
+ tmp_reg = tmp_reg / BMI_FIFO_ALIGN;
+
+ tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) <<
+ BMI_CFG1_FIFO_SIZE_SHIFT);
+ iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1);
+
+ tmp_reg = ((uint32_t)(cfg->total_num_of_tasks - 1) <<
+ BMI_CFG2_TASKS_SHIFT);
+ /* num of DMA's will be dynamically updated when each port is set */
+ iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2);
+
+ /* define unmaskable exceptions, enable and clear events */
+ tmp_reg = 0;
+ iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC |
+ BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC |
+ BMI_ERR_INTR_EN_STATISTICS_RAM_ECC |
+ BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, &bmi_rg->fmbm_ievr);
+
+ if (cfg->exceptions & FMAN_EX_BMI_LIST_RAM_ECC)
+ tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
+ if (cfg->exceptions & FMAN_EX_BMI_PIPELINE_ECC)
+ tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
+ if (cfg->exceptions & FMAN_EX_BMI_STATISTICS_RAM_ECC)
+ tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
+ if (cfg->exceptions & FMAN_EX_BMI_DISPATCH_RAM_ECC)
+ tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
+ iowrite32be(tmp_reg, &bmi_rg->fmbm_ier);
+
+ return 0;
+}
+
+int fman_qmi_init(struct fman_qmi_regs __iomem *qmi_rg, struct fman_cfg *cfg)
+{
+ uint32_t tmp_reg;
+ uint16_t period_in_fm_clocks;
+ uint8_t remainder;
+
+ /* Init QMI Registers */
+
+ /* Clear error interrupt events */
+
+ iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC | QMI_ERR_INTR_EN_DEQ_FROM_DEF,
+ &qmi_rg->fmqm_eie);
+ tmp_reg = 0;
+ if (cfg->exceptions & FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID)
+ tmp_reg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
+ if (cfg->exceptions & FMAN_EX_QMI_DOUBLE_ECC)
+ tmp_reg |= QMI_ERR_INTR_EN_DOUBLE_ECC;
+ /* enable events */
+ iowrite32be(tmp_reg, &qmi_rg->fmqm_eien);
+
+ if (cfg->tnum_aging_period) {
+ /* tnum_aging_period is in units of usec,
+ * p_fmClockFreq in Mhz
+ */
+ period_in_fm_clocks = (uint16_t)
+ (cfg->tnum_aging_period * cfg->clk_freq);
+ /* periodInFmClocks must be a 64 multiply */
+ remainder = (uint8_t)(period_in_fm_clocks % 64);
+ if (remainder) {
+ tmp_reg = (uint32_t)((period_in_fm_clocks / 64) + 1);
+ } else {
+ tmp_reg = (uint32_t)(period_in_fm_clocks / 64);
+ if (!tmp_reg)
+ tmp_reg = 1;
+ }
+ tmp_reg <<= QMI_TAPC_TAP;
+ iowrite32be(tmp_reg, &qmi_rg->fmqm_tapc);
+ }
+ tmp_reg = 0;
+ /* Clear interrupt events */
+ iowrite32be(QMI_INTR_EN_SINGLE_ECC, &qmi_rg->fmqm_ie);
+ if (cfg->exceptions & FMAN_EX_QMI_SINGLE_ECC)
+ tmp_reg |= QMI_INTR_EN_SINGLE_ECC;
+ /* enable events */
+ iowrite32be(tmp_reg, &qmi_rg->fmqm_ien);
+
+ return 0;
+}
+
+int fman_enable(struct fman_rg *fman_rg, struct fman_cfg *cfg)
+{
+ uint32_t cfg_reg = 0;
+
+ /* Enable all modules */
+
+ /* clear&enable global counters - calculate reg and save for later,
+ * because it's the same reg for QMI enable
+ */
+ cfg_reg = QMI_CFG_EN_COUNTERS;
+ if (cfg->qmi_deq_option_support)
+ cfg_reg |= (uint32_t)(((cfg->qmi_def_tnums_thresh) << 8) |
+ (uint32_t)cfg->qmi_def_tnums_thresh);
+
+ iowrite32be(BMI_INIT_START, &fman_rg->bmi_rg->fmbm_init);
+ iowrite32be(cfg_reg | QMI_CFG_ENQ_EN | QMI_CFG_DEQ_EN,
+ &fman_rg->qmi_rg->fmqm_gc);
+
+ return 0;
+}
+
+void fman_free_resources(struct fman_rg *fman_rg)
+{
+ /* disable BMI and QMI */
+ iowrite32be(0, &fman_rg->bmi_rg->fmbm_init);
+ iowrite32be(0, &fman_rg->qmi_rg->fmqm_gc);
+
+ /* release BMI resources */
+ iowrite32be(0, &fman_rg->bmi_rg->fmbm_cfg2);
+ iowrite32be(0, &fman_rg->bmi_rg->fmbm_cfg1);
+
+ /* disable ECC */
+ iowrite32be(0, &fman_rg->fpm_rg->fm_rcr);
+}
+
+/* API Run-time Control uint functions */
+
+uint32_t fman_get_normal_pending(struct fman_fpm_regs __iomem *fpm_rg)
+{
+ return ioread32be(&fpm_rg->fm_npi);
+}
+
+uint32_t fman_get_controller_event(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t reg_id)
+{
+ uint32_t event;
+
+ event = ioread32be(&fpm_rg->fmfp_fcev[reg_id]) &
+ ioread32be(&fpm_rg->fmfp_cee[reg_id]);
+ iowrite32be(event, &fpm_rg->fmfp_cev[reg_id]);
+
+ return event;
+}
+
+uint32_t fman_get_error_pending(struct fman_fpm_regs __iomem *fpm_rg)
+{
+ return ioread32be(&fpm_rg->fm_epi);
+}
+
+void fman_set_ports_bandwidth(struct fman_bmi_regs __iomem *bmi_rg,
+ uint8_t *weights)
+{
+ int i;
+ uint8_t shift;
+ uint32_t tmp = 0;
+
+ for (i = 0; i < 64; i++) {
+ if (weights[i] > 1) { /* no need to write 1 since it is 0 */
+ /* Add this port to tmp_reg */
+ /* (each 8 ports result in one register) */
+ shift = (uint8_t)(32 - 4 * ((i % 8) + 1));
+ tmp |= ((weights[i] - 1) << shift);
+ }
+ if (i % 8 == 7) { /* last in this set */
+ iowrite32be(tmp, &bmi_rg->fmbm_arb[i / 8]);
+ tmp = 0;
+ }
+ }
+}
+
+void fman_enable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(&fpm_rg->fm_rcr);
+ if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
+ iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
+ else
+ iowrite32be(tmp | FPM_RAM_RAMS_ECC_EN |
+ FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
+}
+
+void fman_disable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(&fpm_rg->fm_rcr);
+ if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
+ iowrite32be(tmp & ~FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
+ else
+ iowrite32be(tmp & ~(FPM_RAM_RAMS_ECC_EN | FPM_RAM_IRAM_ECC_EN),
+ &fpm_rg->fm_rcr);
+}
+
+int fman_set_exception(struct fman_rg *fman_rg,
+ enum fman_exceptions exception, bool enable)
+{
+ uint32_t tmp;
+
+ switch (exception) {
+ case (E_FMAN_EX_DMA_BUS_ERROR):
+ tmp = ioread32be(&fman_rg->dma_rg->fmdmmr);
+ if (enable)
+ tmp |= DMA_MODE_BER;
+ else
+ tmp &= ~DMA_MODE_BER;
+ /* disable bus error */
+ iowrite32be(tmp, &fman_rg->dma_rg->fmdmmr);
+ break;
+ case (E_FMAN_EX_DMA_READ_ECC):
+ case (E_FMAN_EX_DMA_SYSTEM_WRITE_ECC):
+ case (E_FMAN_EX_DMA_FM_WRITE_ECC):
+ tmp = ioread32be(&fman_rg->dma_rg->fmdmmr);
+ if (enable)
+ tmp |= DMA_MODE_ECC;
+ else
+ tmp &= ~DMA_MODE_ECC;
+ iowrite32be(tmp, &fman_rg->dma_rg->fmdmmr);
+ break;
+ case (E_FMAN_EX_FPM_STALL_ON_TASKS):
+ tmp = ioread32be(&fman_rg->fpm_rg->fmfp_ee);
+ if (enable)
+ tmp |= FPM_EV_MASK_STALL_EN;
+ else
+ tmp &= ~FPM_EV_MASK_STALL_EN;
+ iowrite32be(tmp, &fman_rg->fpm_rg->fmfp_ee);
+ break;
+ case (E_FMAN_EX_FPM_SINGLE_ECC):
+ tmp = ioread32be(&fman_rg->fpm_rg->fmfp_ee);
+ if (enable)
+ tmp |= FPM_EV_MASK_SINGLE_ECC_EN;
+ else
+ tmp &= ~FPM_EV_MASK_SINGLE_ECC_EN;
+ iowrite32be(tmp, &fman_rg->fpm_rg->fmfp_ee);
+ break;
+ case (E_FMAN_EX_FPM_DOUBLE_ECC):
+ tmp = ioread32be(&fman_rg->fpm_rg->fmfp_ee);
+ if (enable)
+ tmp |= FPM_EV_MASK_DOUBLE_ECC_EN;
+ else
+ tmp &= ~FPM_EV_MASK_DOUBLE_ECC_EN;
+ iowrite32be(tmp, &fman_rg->fpm_rg->fmfp_ee);
+ break;
+ case (E_FMAN_EX_QMI_SINGLE_ECC):
+ tmp = ioread32be(&fman_rg->qmi_rg->fmqm_ien);
+ if (enable)
+ tmp |= QMI_INTR_EN_SINGLE_ECC;
+ else
+ tmp &= ~QMI_INTR_EN_SINGLE_ECC;
+ iowrite32be(tmp, &fman_rg->qmi_rg->fmqm_ien);
+ break;
+ case (E_FMAN_EX_QMI_DOUBLE_ECC):
+ tmp = ioread32be(&fman_rg->qmi_rg->fmqm_eien);
+ if (enable)
+ tmp |= QMI_ERR_INTR_EN_DOUBLE_ECC;
+ else
+ tmp &= ~QMI_ERR_INTR_EN_DOUBLE_ECC;
+ iowrite32be(tmp, &fman_rg->qmi_rg->fmqm_eien);
+ break;
+ case (E_FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID):
+ tmp = ioread32be(&fman_rg->qmi_rg->fmqm_eien);
+ if (enable)
+ tmp |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
+ else
+ tmp &= ~QMI_ERR_INTR_EN_DEQ_FROM_DEF;
+ iowrite32be(tmp, &fman_rg->qmi_rg->fmqm_eien);
+ break;
+ case (E_FMAN_EX_BMI_LIST_RAM_ECC):
+ tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier);
+ if (enable)
+ tmp |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
+ else
+ tmp &= ~BMI_ERR_INTR_EN_LIST_RAM_ECC;
+ iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier);
+ break;
+ case (E_FMAN_EX_BMI_STORAGE_PROFILE_ECC):
+ tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier);
+ if (enable)
+ tmp |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
+ else
+ tmp &= ~BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
+ iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier);
+ break;
+ case (E_FMAN_EX_BMI_STATISTICS_RAM_ECC):
+ tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier);
+ if (enable)
+ tmp |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
+ else
+ tmp &= ~BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
+ iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier);
+ break;
+ case (E_FMAN_EX_BMI_DISPATCH_RAM_ECC):
+ tmp = ioread32be(&fman_rg->bmi_rg->fmbm_ier);
+ if (enable)
+ tmp |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
+ else
+ tmp &= ~BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
+ iowrite32be(tmp, &fman_rg->bmi_rg->fmbm_ier);
+ break;
+ case (E_FMAN_EX_IRAM_ECC):
+ tmp = ioread32be(&fman_rg->fpm_rg->fm_rie);
+ if (enable) {
+ /* enable ECC if not enabled */
+ fman_enable_rams_ecc(fman_rg->fpm_rg);
+ /* enable ECC interrupts */
+ tmp |= FPM_IRAM_ECC_ERR_EX_EN;
+ } else {
+ /* ECC mechanism may be disabled,
+ * depending on driver status
+ */
+ fman_disable_rams_ecc(fman_rg->fpm_rg);
+ tmp &= ~FPM_IRAM_ECC_ERR_EX_EN;
+ }
+ iowrite32be(tmp, &fman_rg->fpm_rg->fm_rie);
+ break;
+ case (E_FMAN_EX_MURAM_ECC):
+ tmp = ioread32be(&fman_rg->fpm_rg->fm_rie);
+ if (enable) {
+ /* enable ECC if not enabled */
+ fman_enable_rams_ecc(fman_rg->fpm_rg);
+ /* enable ECC interrupts */
+ tmp |= FPM_MURAM_ECC_ERR_EX_EN;
+ } else {
+ /* ECC mechanism may be disabled,
+ * depending on driver status
+ */
+ fman_disable_rams_ecc(fman_rg->fpm_rg);
+ tmp &= ~FPM_MURAM_ECC_ERR_EX_EN;
+ }
+ iowrite32be(tmp, &fman_rg->fpm_rg->fm_rie);
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+void fman_get_revision(struct fman_fpm_regs __iomem *fpm_rg,
+ uint8_t *major, uint8_t *minor)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(&fpm_rg->fm_ip_rev_1);
+ *major =
+ (uint8_t)((tmp & FPM_REV1_MAJOR_MASK) >> FPM_REV1_MAJOR_SHIFT);
+ *minor =
+ (uint8_t)((tmp & FPM_REV1_MINOR_MASK) >> FPM_REV1_MINOR_SHIFT);
+}
+
+uint32_t fman_get_counter(struct fman_rg *fman_rg, enum fman_counters reg_name)
+{
+ uint32_t ret_val;
+
+ switch (reg_name) {
+ case (E_FMAN_COUNTERS_ENQ_TOTAL_FRAME):
+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_etfc);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_TOTAL_FRAME):
+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dtfc);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_0):
+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dc0);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_1):
+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dc1);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_2):
+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dc2);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_3):
+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dc3);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_FROM_DEFAULT):
+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dfdc);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_FROM_CONTEXT):
+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dfcc);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_FROM_FD):
+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dffc);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_CONFIRM):
+ ret_val = ioread32be(&fman_rg->qmi_rg->fmqm_dcc);
+ break;
+ default:
+ ret_val = 0;
+ }
+ return ret_val;
+}
+
+int fman_modify_counter(struct fman_rg *fman_rg,
+ enum fman_counters reg_name, uint32_t val)
+{
+ /* When applicable (when there is an 'enable counters' bit,
+ * check that counters are enabled
+ */
+ switch (reg_name) {
+ case (E_FMAN_COUNTERS_ENQ_TOTAL_FRAME):
+ case (E_FMAN_COUNTERS_DEQ_TOTAL_FRAME):
+ case (E_FMAN_COUNTERS_DEQ_0):
+ case (E_FMAN_COUNTERS_DEQ_1):
+ case (E_FMAN_COUNTERS_DEQ_2):
+ case (E_FMAN_COUNTERS_DEQ_3):
+ case (E_FMAN_COUNTERS_DEQ_FROM_DEFAULT):
+ case (E_FMAN_COUNTERS_DEQ_FROM_CONTEXT):
+ case (E_FMAN_COUNTERS_DEQ_FROM_FD):
+ case (E_FMAN_COUNTERS_DEQ_CONFIRM):
+ if (!(ioread32be(&fman_rg->qmi_rg->fmqm_gc) &
+ QMI_CFG_EN_COUNTERS))
+ return -EINVAL;
+ break;
+ default:
+ break;
+ }
+ /* Set counter */
+ switch (reg_name) {
+ case (E_FMAN_COUNTERS_ENQ_TOTAL_FRAME):
+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_etfc);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_TOTAL_FRAME):
+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dtfc);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_0):
+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dc0);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_1):
+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dc1);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_2):
+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dc2);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_3):
+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dc3);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_FROM_DEFAULT):
+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dfdc);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_FROM_CONTEXT):
+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dfcc);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_FROM_FD):
+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dffc);
+ break;
+ case (E_FMAN_COUNTERS_DEQ_CONFIRM):
+ iowrite32be(val, &fman_rg->qmi_rg->fmqm_dcc);
+ break;
+ case (E_FMAN_COUNTERS_SEMAPHOR_ENTRY_FULL_REJECT):
+ iowrite32be(val, &fman_rg->dma_rg->fmdmsefrc);
+ break;
+ case (E_FMAN_COUNTERS_SEMAPHOR_QUEUE_FULL_REJECT):
+ iowrite32be(val, &fman_rg->dma_rg->fmdmsqfrc);
+ break;
+ case (E_FMAN_COUNTERS_SEMAPHOR_SYNC_REJECT):
+ iowrite32be(val, &fman_rg->dma_rg->fmdmssrc);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+void fman_set_dma_emergency(struct fman_dma_regs __iomem *dma_rg,
+ bool is_write, bool enable)
+{
+ uint32_t msk;
+
+ msk = (uint32_t)(is_write ? DMA_MODE_EMER_WRITE : DMA_MODE_EMER_READ);
+
+ if (enable)
+ iowrite32be(ioread32be(&dma_rg->fmdmmr) | msk, &dma_rg->fmdmmr);
+ else /* disable */
+ iowrite32be(ioread32be(&dma_rg->fmdmmr) & ~msk,
+ &dma_rg->fmdmmr);
+}
+
+void fman_set_dma_ext_bus_pri(struct fman_dma_regs __iomem *dma_rg,
+ uint32_t pri)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(&dma_rg->fmdmmr) | (pri << DMA_MODE_BUS_PRI_SHIFT);
+
+ iowrite32be(tmp, &dma_rg->fmdmmr);
+}
+
+uint32_t fman_get_dma_status(struct fman_dma_regs __iomem *dma_rg)
+{
+ return ioread32be(&dma_rg->fmdmsr);
+}
+
+void fman_force_intr(struct fman_rg *fman_rg, enum fman_exceptions exception)
+{
+ switch (exception) {
+ case E_FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:
+ iowrite32be(QMI_ERR_INTR_EN_DEQ_FROM_DEF,
+ &fman_rg->qmi_rg->fmqm_eif);
+ break;
+ case E_FMAN_EX_QMI_SINGLE_ECC:
+ iowrite32be(QMI_INTR_EN_SINGLE_ECC, &fman_rg->qmi_rg->fmqm_if);
+ break;
+ case E_FMAN_EX_QMI_DOUBLE_ECC:
+ iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC,
+ &fman_rg->qmi_rg->fmqm_eif);
+ break;
+ case E_FMAN_EX_BMI_LIST_RAM_ECC:
+ iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC,
+ &fman_rg->bmi_rg->fmbm_ifr);
+ break;
+ case E_FMAN_EX_BMI_STORAGE_PROFILE_ECC:
+ iowrite32be(BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC,
+ &fman_rg->bmi_rg->fmbm_ifr);
+ break;
+ case E_FMAN_EX_BMI_STATISTICS_RAM_ECC:
+ iowrite32be(BMI_ERR_INTR_EN_STATISTICS_RAM_ECC,
+ &fman_rg->bmi_rg->fmbm_ifr);
+ break;
+ case E_FMAN_EX_BMI_DISPATCH_RAM_ECC:
+ iowrite32be(BMI_ERR_INTR_EN_DISPATCH_RAM_ECC,
+ &fman_rg->bmi_rg->fmbm_ifr);
+ break;
+ default:
+ break;
+ }
+}
+
+bool fman_is_qmi_halt_not_busy_state(struct fman_qmi_regs __iomem *qmi_rg)
+{
+ return (bool)!!(ioread32be(&qmi_rg->fmqm_gs) & QMI_GS_HALT_NOT_BUSY);
+}
+
+void fman_resume(struct fman_fpm_regs __iomem *fpm_rg)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(&fpm_rg->fmfp_ee);
+ /* clear tmp_reg event bits in order not to clear standing events */
+ tmp &= ~(FPM_EV_MASK_DOUBLE_ECC |
+ FPM_EV_MASK_STALL | FPM_EV_MASK_SINGLE_ECC);
+ tmp |= FPM_EV_MASK_RELEASE_FM;
+
+ iowrite32be(tmp, &fpm_rg->fmfp_ee);
+}
--
2.3.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 2/7] soc/fman: Add the FMan FLIB
2015-03-05 5:45 ` [PATCH 2/7] soc/fman: Add the FMan FLIB Emil Medve
@ 2015-03-07 0:57 ` Scott Wood
0 siblings, 0 replies; 15+ messages in thread
From: Scott Wood @ 2015-03-07 0:57 UTC (permalink / raw)
To: Emil Medve; +Cc: netdev, linuxppc-dev, linux-kernel, Igal Liberman
On Wed, 2015-03-04 at 23:45 -0600, Emil Medve wrote:
> From: Igal Liberman <Igal.Liberman@freescale.com>
>
> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
> ---
> drivers/soc/Kconfig | 1 +
> drivers/soc/Makefile | 1 +
> drivers/soc/fsl/Kconfig | 1 +
> drivers/soc/fsl/Makefile | 1 +
> drivers/soc/fsl/fman/Kconfig | 7 +
> drivers/soc/fsl/fman/Makefile | 13 +
> drivers/soc/fsl/fman/fman.c | 1396 +++++++++++++++++++++++++++++++++++++++++
> 7 files changed, 1420 insertions(+)
> create mode 100644 drivers/soc/fsl/Kconfig
> create mode 100644 drivers/soc/fsl/Makefile
> create mode 100644 drivers/soc/fsl/fman/Kconfig
> create mode 100644 drivers/soc/fsl/fman/Makefile
> create mode 100644 drivers/soc/fsl/fman/fman.c
>
> diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
> index 76d6bd4..674a6e6 100644
> --- a/drivers/soc/Kconfig
> +++ b/drivers/soc/Kconfig
> @@ -1,5 +1,6 @@
> menu "SOC (System On Chip) specific Drivers"
>
> +source "drivers/soc/fsl/Kconfig"
> source "drivers/soc/qcom/Kconfig"
> source "drivers/soc/ti/Kconfig"
> source "drivers/soc/versatile/Kconfig"
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 063113d..42836ee 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -2,6 +2,7 @@
> # Makefile for the Linux Kernel SOC specific device drivers.
> #
>
> +obj-$(CONFIG_FSL_SOC) += fsl/
> obj-$(CONFIG_ARCH_QCOM) += qcom/
> obj-$(CONFIG_ARCH_TEGRA) += tegra/
> obj-$(CONFIG_SOC_TI) += ti/
> diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig
> new file mode 100644
> index 0000000..38c08ae
> --- /dev/null
> +++ b/drivers/soc/fsl/Kconfig
> @@ -0,0 +1 @@
> +source "drivers/soc/fsl/fman/Kconfig"
> diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile
> new file mode 100644
> index 0000000..97d715c
> --- /dev/null
> +++ b/drivers/soc/fsl/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_FSL_FMAN) += fman/
> diff --git a/drivers/soc/fsl/fman/Kconfig b/drivers/soc/fsl/fman/Kconfig
> new file mode 100644
> index 0000000..e5009a9
> --- /dev/null
> +++ b/drivers/soc/fsl/fman/Kconfig
> @@ -0,0 +1,7 @@
> +menuconfig FSL_FMAN
> + tristate "Freescale DPAA Frame Manager"
> + depends on FSL_SOC || COMPILE_TEST
> + default n
> + help
> + Freescale Data-Path Acceleration Architecture Frame Manager
> + (FMan) support
As this doesn't appear to be a complete driver, why is it
user-selectable? Likewise for the other flib patches.
Why are you adding the flibs in a big batch, rather than bundling the
code with the driver patches that use it?
Is there a minimal core of fman functionality (complete functionality,
not flibs) that you could start with, rather than trying to get the
entire thing reviewed at once? In other words, break it up vertically,
not horizontally.
Note that the lack of caller context is especially harmful given that
the functions are not documented.
> diff --git a/drivers/soc/fsl/fman/Makefile b/drivers/soc/fsl/fman/Makefile
> new file mode 100644
> index 0000000..d7fbecb
> --- /dev/null
> +++ b/drivers/soc/fsl/fman/Makefile
> @@ -0,0 +1,13 @@
> +ccflags-y += -DVERSION=\"\"
> +
> +ifeq ($(CONFIG_FSL_FMAN),y)
> +
> +FMAN = $(srctree)/drivers/soc/fsl/fman
> +
> +ccflags-y += -I$(FMAN)/flib
> +
> +obj-$(CONFIG_FSL_FMAN) += fsl_fman.o
> +
> +fsl_fman-objs := fman.o
> +
> +endif
You won't even get into this makefile if CONFIG_FSL_FMAN=n... Did you
really mean to exclude this stuff when CONFIG_FSL_FMAN=m?
> +int fman_reset_mac(struct fman_fpm_regs __iomem *fpm_rg, uint8_t mac_id)
> +{
> + uint32_t msk, timeout = 100;
> +
> + /* Get the relevant bit mask */
> + switch (mac_id) {
> + case (0):
> + msk = FPM_RSTC_MAC0_RESET;
> + break;
> + case (1):
> + msk = FPM_RSTC_MAC1_RESET;
> + break;
> + case (2):
> + msk = FPM_RSTC_MAC2_RESET;
> + break;
> + case (3):
> + msk = FPM_RSTC_MAC3_RESET;
> + break;
> + case (4):
> + msk = FPM_RSTC_MAC4_RESET;
> + break;
> + case (5):
> + msk = FPM_RSTC_MAC5_RESET;
> + break;
> + case (6):
> + msk = FPM_RSTC_MAC6_RESET;
> + break;
> + case (7):
> + msk = FPM_RSTC_MAC7_RESET;
> + break;
> + case (8):
> + msk = FPM_RSTC_MAC8_RESET;
> + break;
> + case (9):
> + msk = FPM_RSTC_MAC9_RESET;
> + break;
> + default:
> + return -EINVAL;
> + }
Without seeing the caller, I can't judge whether there's a good reason
for passing this in by number rather than passing in FPM_RSTC_MACn_RESET
directly and avoiding the switch.
> + /* reset */
> + iowrite32be(msk, &fpm_rg->fm_rstc);
> + while ((ioread32be(&fpm_rg->fm_rstc) & msk) && --timeout)
> + usleep_range(10, 11);
> +
> + if (!timeout)
> + return -EBUSY;
> + return 0;
> +}
-EBUSY generally means that the caller is expected to try again. I
think this should be -EIO.
> +uint32_t fman_get_total_fifo_size(struct fman_bmi_regs __iomem *bmi_rg)
> +{
> + uint32_t reg, res;
> +
> + reg = ioread32be(&bmi_rg->fmbm_cfg1);
> + res = (reg >> BMI_CFG1_FIFO_SIZE_SHIFT) & 0x3ff;
> + return res * FMAN_BMI_FIFO_UNITS;
> +}
Where did 0x3ff come from?
> +void fman_set_num_of_tasks(struct fman_bmi_regs __iomem *bmi_rg,
> + uint8_t port_id, uint8_t num_tasks,
> + uint8_t num_extra_tasks)
> +{
> + uint32_t tmp;
> +
> + if ((port_id > 63) || (port_id < 1))
> + return;
> +
> + /* calculate reg */
> + tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
> + ~(BMI_NUM_OF_TASKS_MASK | BMI_NUM_OF_EXTRA_TASKS_MASK);
> + tmp |= (uint32_t)(((num_tasks - 1) << BMI_NUM_OF_TASKS_SHIFT) |
> + (num_extra_tasks << BMI_EXTRA_NUM_OF_TASKS_SHIFT));
> + iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
> +}
That cast needs to be inside each shift -- doing it at the end is
useless. Or rather, you don't need any cast at all for 32-bit results
(which is why it works despite being misplaced) because of C type
promotion rules, as long as you don't rely on whether the result is
signed or not. Still, it would be nice to not rely on that due to
always using the smallest type you can get away with.
> +void fman_set_vsp_window(struct fman_bmi_regs __iomem *bmi_rg,
> + uint8_t port_id,
> + uint8_t base_storage_profile,
> + uint8_t log2_num_of_profiles)
> +{
> + uint32_t tmp = 0;
> +
> + if ((port_id > 63) || (port_id < 1))
> + return;
Where does 63 come from? And shouldn't there be some sort of WARN,
especially if you're not going to pass back an error code? Don't
silently eat errors.
Oh, and unnecessary parentheses.
> +/* API Init unit functions */
> +
> +void fman_defconfig(struct fman_cfg *cfg)
> +{
> + memset(cfg, 0, sizeof(struct fman_cfg));
> +
> + cfg->catastrophic_err = DEFAULT_CATASTROPHIC_ERR;
> + cfg->dma_err = DEFAULT_DMA_ERR;
> + cfg->halt_on_external_activ = DEFAULT_HALT_ON_EXTERNAL_ACTIVATION;
> + cfg->halt_on_unrecov_ecc_err = DEFAULT_HALT_ON_UNRECOVERABLE_ECC_ERROR;
> + cfg->en_iram_test_mode = false;
> + cfg->en_muram_test_mode = false;
> + cfg->external_ecc_rams_enable = DEFAULT_EXTERNAL_ECC_RAMS_ENABLE;
> +
> + cfg->dma_aid_override = DEFAULT_AID_OVERRIDE;
> + cfg->dma_aid_mode = DEFAULT_AID_MODE;
> + cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW;
> + cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH;
> + cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE;
> + cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES;
> + cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE;
> + cfg->dma_en_emergency = DEFAULT_DMA_EN_EMERGENCY;
> + cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY;
> + cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG;
> + cfg->dma_en_emergency_smoother = DEFAULT_DMA_EN_EMERGENCY_SMOOTHER;
> + cfg->dma_emergency_switch_counter =
> + DEFAULT_DMA_EMERGENCY_SWITCH_COUNTER;
> + cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT;
> + cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH;
> + cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH;
> + cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH;
> + cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH;
> + cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH;
> + cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH;
> + cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH;
> + cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH;
> +
> + cfg->pedantic_dma = false;
> + cfg->tnum_aging_period = DEFAULT_TNUM_AGING_PERIOD;
> + cfg->dma_stop_on_bus_error = false;
> + cfg->qmi_deq_option_support = false;
> +}
Couldn't you do this as a struct initializer?
> +/* fm_init
> + * Initializes the FM module
> + * h_fm - FM module descriptor
> + * Return 0 on success; Error code otherwise.
> + */
> +int fman_dma_init(struct fman_dma_regs __iomem *dma_rg, struct fman_cfg *cfg)
> +{
> + uint32_t tmp_reg;
> +
> + /* Init DMA Registers */
> +
> + /* clear status reg events */
> + /* oren - check!!! */
> + tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC |
> + DMA_STATUS_SYSTEM_WRITE_ECC | DMA_STATUS_FM_WRITE_ECC);
> + iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, &dma_rg->fmdmsr);
Either get Oren to check this, or remove the comment. :-)
> + tmp_reg =
> + (((uint32_t)cfg->
> + qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) |
> + ((uint32_t)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT)
> + | ((uint32_t)cfg->
> + fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) |
> + ((uint32_t)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT));
Yikes.
> + iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2);
> +
> + /* define exceptions and error behavior */
> + tmp_reg = 0;
> + /* Clear events */
> + tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC |
> + FPM_EV_MASK_SINGLE_ECC);
> + /* enable interrupts */
> + if (cfg->exceptions & FMAN_EX_FPM_STALL_ON_TASKS)
> + tmp_reg |= FPM_EV_MASK_STALL_EN;
> + if (cfg->exceptions & FMAN_EX_FPM_SINGLE_ECC)
> + tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN;
> + if (cfg->exceptions & FMAN_EX_FPM_DOUBLE_ECC)
> + tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN;
> + tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT);
> + tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT);
> + if (!cfg->halt_on_external_activ)
> + tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT;
> + if (!cfg->halt_on_unrecov_ecc_err)
> + tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT;
> + iowrite32be(tmp_reg, &fpm_rg->fmfp_ee);
> +
> + /* clear all fmCtls event registers */
> + for (i = 0; i < cfg->num_of_fman_ctrl_evnt_regs; i++)
> + iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]);
> +
> + /* RAM ECC - enable and clear events */
> + /* first we need to clear all parser memory,
> + * as it is uninitialized and may cause ECC errors
> + */
> + /* event bits */
> + tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC);
> + /* Rams enable not effected by RCR bit,
> + * but by a COP configuration
> + */
> + if (cfg->external_ecc_rams_enable)
> + tmp_reg |= FPM_RAM_RAMS_ECC_EN_SRC_SEL;
> +
> + /* enable test mode */
> + if (cfg->en_muram_test_mode)
> + tmp_reg |= FPM_RAM_MURAM_TEST_ECC;
> + if (cfg->en_iram_test_mode)
> + tmp_reg |= FPM_RAM_IRAM_TEST_ECC;
> + iowrite32be(tmp_reg, &fpm_rg->fm_rcr);
> +
> + tmp_reg = 0;
> + if (cfg->exceptions & FMAN_EX_IRAM_ECC) {
> + tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN;
> + fman_enable_rams_ecc(fpm_rg);
> + }
> + if (cfg->exceptions & FMAN_EX_NURAM_ECC) {
> + tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN;
> + fman_enable_rams_ecc(fpm_rg);
> + }
> + iowrite32be(tmp_reg, &fpm_rg->fm_rie);
> +
> + return 0;
> +}
> +
> +int fman_bmi_init(struct fman_bmi_regs __iomem *bmi_rg, struct fman_cfg *cfg)
> +{
> + uint32_t tmp_reg;
> +
> + /* Init BMI Registers */
> +
> + /* define common resources */
> + tmp_reg = cfg->fifo_base_addr;
> + tmp_reg = tmp_reg / BMI_FIFO_ALIGN;
> +
> + tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) <<
> + BMI_CFG1_FIFO_SIZE_SHIFT);
> + iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1);
> +
> + tmp_reg = ((uint32_t)(cfg->total_num_of_tasks - 1) <<
> + BMI_CFG2_TASKS_SHIFT);
> + /* num of DMA's will be dynamically updated when each port is set */
> + iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2);
> +
> + /* define unmaskable exceptions, enable and clear events */
> + tmp_reg = 0;
> + iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC |
> + BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC |
> + BMI_ERR_INTR_EN_STATISTICS_RAM_ECC |
> + BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, &bmi_rg->fmbm_ievr);
> +
> + if (cfg->exceptions & FMAN_EX_BMI_LIST_RAM_ECC)
> + tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
> + if (cfg->exceptions & FMAN_EX_BMI_PIPELINE_ECC)
> + tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
> + if (cfg->exceptions & FMAN_EX_BMI_STATISTICS_RAM_ECC)
> + tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
> + if (cfg->exceptions & FMAN_EX_BMI_DISPATCH_RAM_ECC)
> + tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
> + iowrite32be(tmp_reg, &bmi_rg->fmbm_ier);
> +
> + return 0;
> +}
> +
> +int fman_qmi_init(struct fman_qmi_regs __iomem *qmi_rg, struct fman_cfg *cfg)
> +{
> + uint32_t tmp_reg;
> + uint16_t period_in_fm_clocks;
> + uint8_t remainder;
> +
> + /* Init QMI Registers */
> +
> + /* Clear error interrupt events */
> +
> + iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC | QMI_ERR_INTR_EN_DEQ_FROM_DEF,
> + &qmi_rg->fmqm_eie);
> + tmp_reg = 0;
> + if (cfg->exceptions & FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID)
> + tmp_reg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
> + if (cfg->exceptions & FMAN_EX_QMI_DOUBLE_ECC)
> + tmp_reg |= QMI_ERR_INTR_EN_DOUBLE_ECC;
> + /* enable events */
> + iowrite32be(tmp_reg, &qmi_rg->fmqm_eien);
> +
> + if (cfg->tnum_aging_period) {
> + /* tnum_aging_period is in units of usec,
> + * p_fmClockFreq in Mhz
> + */
> + period_in_fm_clocks = (uint16_t)
> + (cfg->tnum_aging_period * cfg->clk_freq);
> + /* periodInFmClocks must be a 64 multiply */
> + remainder = (uint8_t)(period_in_fm_clocks % 64);
Name in comment doesn't match code (and unnecessary cast).
s/multiply/multiple/
> + if (remainder) {
> + tmp_reg = (uint32_t)((period_in_fm_clocks / 64) + 1);
> + } else {
> + tmp_reg = (uint32_t)(period_in_fm_clocks / 64);
> + if (!tmp_reg)
> + tmp_reg = 1;
> + }
> + tmp_reg <<= QMI_TAPC_TAP;
> + iowrite32be(tmp_reg, &qmi_rg->fmqm_tapc);
> + }
> + tmp_reg = 0;
> + /* Clear interrupt events */
> + iowrite32be(QMI_INTR_EN_SINGLE_ECC, &qmi_rg->fmqm_ie);
> + if (cfg->exceptions & FMAN_EX_QMI_SINGLE_ECC)
> + tmp_reg |= QMI_INTR_EN_SINGLE_ECC;
> + /* enable events */
> + iowrite32be(tmp_reg, &qmi_rg->fmqm_ien);
> +
> + return 0;
> +}
> +
> +int fman_enable(struct fman_rg *fman_rg, struct fman_cfg *cfg)
> +{
> + uint32_t cfg_reg = 0;
> +
> + /* Enable all modules */
> +
> + /* clear&enable global counters - calculate reg and save for later,
> + * because it's the same reg for QMI enable
> + */
> + cfg_reg = QMI_CFG_EN_COUNTERS;
> + if (cfg->qmi_deq_option_support)
> + cfg_reg |= (uint32_t)(((cfg->qmi_def_tnums_thresh) << 8) |
> + (uint32_t)cfg->qmi_def_tnums_thresh);
Unnecessary casts.
> +
> + iowrite32be(BMI_INIT_START, &fman_rg->bmi_rg->fmbm_init);
> + iowrite32be(cfg_reg | QMI_CFG_ENQ_EN | QMI_CFG_DEQ_EN,
> + &fman_rg->qmi_rg->fmqm_gc);
> +
> + return 0;
> +}
> +void fman_set_ports_bandwidth(struct fman_bmi_regs __iomem *bmi_rg,
> + uint8_t *weights)
> +{
> + int i;
> + uint8_t shift;
> + uint32_t tmp = 0;
> +
> + for (i = 0; i < 64; i++) {
> + if (weights[i] > 1) { /* no need to write 1 since it is 0 */
If you have an API requirement that weights is of size 64, then use
"uint8_t weights[64]". What does 64 represent? Can it be symbolic?
Can it be supplied by the caller instead of hardcoded?
> + /* Add this port to tmp_reg */
> + /* (each 8 ports result in one register) */
> + shift = (uint8_t)(32 - 4 * ((i % 8) + 1));
> + tmp |= ((weights[i] - 1) << shift);
> + }
> + if (i % 8 == 7) { /* last in this set */
> + iowrite32be(tmp, &bmi_rg->fmbm_arb[i / 8]);
> + tmp = 0;
> + }
> + }
> +}
for (i = 0; i < nreg; i++) {
u32 tmp = 0;
for (j = 0; j < 8; j++) {
uint8_t weight = weights[i * 8 + j];
WARN_ON(weight > 0xf);
tmp |= weight;
tmp <<= 4;
}
iowrite32be(tmp, &bmi_rg->fmbm_arb[i]);
}
> +
> +void fman_enable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
> +{
> + uint32_t tmp;
> +
> + tmp = ioread32be(&fpm_rg->fm_rcr);
> + if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
> + iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
> + else
> + iowrite32be(tmp | FPM_RAM_RAMS_ECC_EN |
> + FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
> +}
tmp = ioread32be(&fpm_rg->fm_rcr);
if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
tmp |= FPM_RAM_RAMS_ECC_EN;
iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
> +int fman_modify_counter(struct fman_rg *fman_rg,
> + enum fman_counters reg_name, uint32_t val)
> +{
> + /* When applicable (when there is an 'enable counters' bit,
> + * check that counters are enabled
> + */
> + switch (reg_name) {
> + case (E_FMAN_COUNTERS_ENQ_TOTAL_FRAME):
> + case (E_FMAN_COUNTERS_DEQ_TOTAL_FRAME):
> + case (E_FMAN_COUNTERS_DEQ_0):
> + case (E_FMAN_COUNTERS_DEQ_1):
> + case (E_FMAN_COUNTERS_DEQ_2):
> + case (E_FMAN_COUNTERS_DEQ_3):
> + case (E_FMAN_COUNTERS_DEQ_FROM_DEFAULT):
> + case (E_FMAN_COUNTERS_DEQ_FROM_CONTEXT):
> + case (E_FMAN_COUNTERS_DEQ_FROM_FD):
> + case (E_FMAN_COUNTERS_DEQ_CONFIRM):
Why the parentheses?
> +void fman_set_dma_emergency(struct fman_dma_regs __iomem *dma_rg,
> + bool is_write, bool enable)
> +{
> + uint32_t msk;
> +
> + msk = (uint32_t)(is_write ? DMA_MODE_EMER_WRITE : DMA_MODE_EMER_READ);
Unnecessary cast.
Why doesn't the caller just pass in
DMA_MODE_EMER_WRITE/DMA_MODE_EMER_READ?
> +void fman_force_intr(struct fman_rg *fman_rg, enum fman_exceptions exception)
> +{
> + switch (exception) {
> + case E_FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:
> + iowrite32be(QMI_ERR_INTR_EN_DEQ_FROM_DEF,
> + &fman_rg->qmi_rg->fmqm_eif);
> + break;
> + case E_FMAN_EX_QMI_SINGLE_ECC:
> + iowrite32be(QMI_INTR_EN_SINGLE_ECC, &fman_rg->qmi_rg->fmqm_if);
> + break;
> + case E_FMAN_EX_QMI_DOUBLE_ECC:
> + iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC,
> + &fman_rg->qmi_rg->fmqm_eif);
> + break;
> + case E_FMAN_EX_BMI_LIST_RAM_ECC:
> + iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC,
> + &fman_rg->bmi_rg->fmbm_ifr);
> + break;
> + case E_FMAN_EX_BMI_STORAGE_PROFILE_ECC:
> + iowrite32be(BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC,
> + &fman_rg->bmi_rg->fmbm_ifr);
> + break;
> + case E_FMAN_EX_BMI_STATISTICS_RAM_ECC:
> + iowrite32be(BMI_ERR_INTR_EN_STATISTICS_RAM_ECC,
> + &fman_rg->bmi_rg->fmbm_ifr);
> + break;
> + case E_FMAN_EX_BMI_DISPATCH_RAM_ECC:
> + iowrite32be(BMI_ERR_INTR_EN_DISPATCH_RAM_ECC,
> + &fman_rg->bmi_rg->fmbm_ifr);
> + break;
How does this abstraction improve on simply writing the bit directly?
Likewise elsewhere.
> + default:
> + break;
Unnecessary.
> + }
> +}
> +
> +bool fman_is_qmi_halt_not_busy_state(struct fman_qmi_regs __iomem *qmi_rg)
> +{
> + return (bool)!!(ioread32be(&qmi_rg->fmqm_gs) & QMI_GS_HALT_NOT_BUSY);
Unnecessary cast.
-Scott
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/7] soc/fman: Add the FMan port FLIB
2015-03-05 5:45 [PATCH 0/7] Freescale DPAA FMan FLIB(s) Emil Medve
2015-03-05 5:45 ` [PATCH 1/7] soc/fman: Add the FMan FLIB headers Emil Medve
2015-03-05 5:45 ` [PATCH 2/7] soc/fman: Add the FMan FLIB Emil Medve
@ 2015-03-05 5:45 ` Emil Medve
2015-03-05 5:45 ` [PATCH 4/7] soc/fman: Add the FMan MAC FLIB Emil Medve
` (4 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Emil Medve @ 2015-03-05 5:45 UTC (permalink / raw)
To: linuxppc-dev, netdev, linux-kernel; +Cc: Igal Liberman
From: Igal Liberman <Igal.Liberman@freescale.com>
Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
---
drivers/soc/fsl/fman/Kconfig | 10 +
drivers/soc/fsl/fman/Makefile | 2 +
drivers/soc/fsl/fman/port/Makefile | 13 +
drivers/soc/fsl/fman/port/fman_port.c | 1536 +++++++++++++++++++++++++++++++++
4 files changed, 1561 insertions(+)
create mode 100644 drivers/soc/fsl/fman/port/Makefile
create mode 100644 drivers/soc/fsl/fman/port/fman_port.c
diff --git a/drivers/soc/fsl/fman/Kconfig b/drivers/soc/fsl/fman/Kconfig
index e5009a9..a5f981f 100644
--- a/drivers/soc/fsl/fman/Kconfig
+++ b/drivers/soc/fsl/fman/Kconfig
@@ -5,3 +5,13 @@ menuconfig FSL_FMAN
help
Freescale Data-Path Acceleration Architecture Frame Manager
(FMan) support
+
+if FSL_FMAN
+
+config FSL_FMAN_PORT
+ bool "FMan port"
+ default n
+ help
+ Freescale DPAA FMan port support
+
+endif # FSL_FMAN
diff --git a/drivers/soc/fsl/fman/Makefile b/drivers/soc/fsl/fman/Makefile
index d7fbecb..a0132cc 100644
--- a/drivers/soc/fsl/fman/Makefile
+++ b/drivers/soc/fsl/fman/Makefile
@@ -10,4 +10,6 @@ obj-$(CONFIG_FSL_FMAN) += fsl_fman.o
fsl_fman-objs := fman.o
+obj-$(CONFIG_FSL_FMAN_PORT) += port/
+
endif
diff --git a/drivers/soc/fsl/fman/port/Makefile b/drivers/soc/fsl/fman/port/Makefile
new file mode 100644
index 0000000..3e79c3f
--- /dev/null
+++ b/drivers/soc/fsl/fman/port/Makefile
@@ -0,0 +1,13 @@
+ccflags-y += -DVERSION=\"\"
+
+ifeq ($(CONFIG_FSL_FMAN_PORT),y)
+
+FMAN = $(srctree)/drivers/soc/fsl/fman
+
+ccflags-y += -I$(FMAN)/flib
+
+obj-$(CONFIG_FSL_FMAN_PORT) += fsl_fman_port.o
+
+fsl_fman_port-objs := fman_port.o
+
+endif
diff --git a/drivers/soc/fsl/fman/port/fman_port.c b/drivers/soc/fsl/fman/port/fman_port.c
new file mode 100644
index 0000000..cc9ebb0
--- /dev/null
+++ b/drivers/soc/fsl/fman/port/fman_port.c
@@ -0,0 +1,1536 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "common/general.h"
+
+#include "fman_common.h"
+#include "fsl_fman_port.h"
+
+/* problem Eyal: the following should not be here*/
+#define NIA_FM_CTL_AC_NO_IPACC_PRE_BMI_ENQ_FRAME 0x00000028
+
+static uint32_t get_no_pcd_nia_bmi_ac_enc_frame(struct fman_port_cfg *cfg)
+{
+ if (cfg->errata_A006675)
+ return NIA_ENG_FM_CTL |
+ NIA_FM_CTL_AC_NO_IPACC_PRE_BMI_ENQ_FRAME;
+ else
+ return NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME;
+}
+
+static int init_bmi_rx(struct fman_port *port,
+ struct fman_port_cfg *cfg,
+ struct fman_port_params *params)
+{
+ struct fman_port_rx_bmi_regs __iomem *regs = &port->bmi_regs->rx;
+ uint32_t tmp;
+
+ /* Rx Configuration register */
+ tmp = 0;
+ if (cfg->discard_override)
+ tmp |= BMI_PORT_CFG_FDOVR;
+ iowrite32be(tmp, ®s->fmbm_rcfg);
+
+ /* DMA attributes */
+ tmp = (uint32_t)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT;
+ if (cfg->dma_ic_stash_on)
+ tmp |= BMI_DMA_ATTR_IC_STASH_ON;
+ if (cfg->dma_header_stash_on)
+ tmp |= BMI_DMA_ATTR_HDR_STASH_ON;
+ if (cfg->dma_sg_stash_on)
+ tmp |= BMI_DMA_ATTR_SG_STASH_ON;
+ if (cfg->dma_write_optimize)
+ tmp |= BMI_DMA_ATTR_WRITE_OPTIMIZE;
+ iowrite32be(tmp, ®s->fmbm_rda);
+
+ /* Rx FIFO parameters */
+ tmp = (cfg->rx_pri_elevation / FMAN_PORT_BMI_FIFO_UNITS - 1) <<
+ BMI_RX_FIFO_PRI_ELEVATION_SHIFT;
+ tmp |= cfg->rx_fifo_thr / FMAN_PORT_BMI_FIFO_UNITS - 1;
+ iowrite32be(tmp, ®s->fmbm_rfp);
+
+ if (cfg->excessive_threshold_register)
+ /* always allow access to the extra resources */
+ iowrite32be(BMI_RX_FIFO_THRESHOLD_ETHE, ®s->fmbm_reth);
+
+ /* Frame end data */
+ tmp = (uint32_t)cfg->checksum_bytes_ignore <<
+ BMI_RX_FRAME_END_CS_IGNORE_SHIFT;
+ tmp |= (uint32_t)cfg->rx_cut_end_bytes << BMI_RX_FRAME_END_CUT_SHIFT;
+ if (cfg->errata_A006320)
+ tmp &= 0xffe0ffff;
+ iowrite32be(tmp, ®s->fmbm_rfed);
+
+ /* Internal context parameters */
+ tmp = ((uint32_t)cfg->ic_ext_offset / FMAN_PORT_IC_OFFSET_UNITS) <<
+ BMI_IC_TO_EXT_SHIFT;
+ tmp |= ((uint32_t)cfg->ic_int_offset / FMAN_PORT_IC_OFFSET_UNITS) <<
+ BMI_IC_FROM_INT_SHIFT;
+ tmp |= cfg->ic_size / FMAN_PORT_IC_OFFSET_UNITS;
+ iowrite32be(tmp, ®s->fmbm_ricp);
+
+ /* Internal buffer offset */
+ tmp = ((uint32_t)cfg->int_buf_start_margin / FMAN_PORT_IC_OFFSET_UNITS)
+ << BMI_INT_BUF_MARG_SHIFT;
+ iowrite32be(tmp, ®s->fmbm_rim);
+
+ /* External buffer margins */
+ tmp = (uint32_t)cfg->ext_buf_start_margin <<
+ BMI_EXT_BUF_MARG_START_SHIFT;
+ tmp |= (uint32_t)cfg->ext_buf_end_margin;
+ if (cfg->fmbm_rebm_has_sgd && cfg->no_scatter_gather)
+ tmp |= BMI_SG_DISABLE;
+ iowrite32be(tmp, ®s->fmbm_rebm);
+
+ /* Frame attributes */
+ tmp = BMI_CMD_RX_MR_DEF;
+ tmp |= BMI_CMD_ATTR_ORDER;
+ tmp |= (uint32_t)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT;
+ if (cfg->sync_req)
+ tmp |= BMI_CMD_ATTR_SYNC;
+
+ iowrite32be(tmp, ®s->fmbm_rfca);
+
+ /* NIA */
+ tmp = (uint32_t)cfg->rx_fd_bits << BMI_NEXT_ENG_FD_BITS_SHIFT;
+ tmp |= get_no_pcd_nia_bmi_ac_enc_frame(cfg);
+
+ iowrite32be(tmp, ®s->fmbm_rfne);
+
+ /* Enqueue NIA */
+ iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, ®s->fmbm_rfene);
+
+ /* Default/error queues */
+ iowrite32be((params->dflt_fqid & 0x00FFFFFF), ®s->fmbm_rfqid);
+ iowrite32be((params->err_fqid & 0x00FFFFFF), ®s->fmbm_refqid);
+
+ /* Discard/error masks */
+ iowrite32be(params->discard_mask, ®s->fmbm_rfsdm);
+ iowrite32be(params->err_mask, ®s->fmbm_rfsem);
+
+ /* Statistics counters */
+ tmp = 0;
+ if (cfg->stats_counters_enable)
+ tmp = BMI_COUNTERS_EN;
+ iowrite32be(tmp, ®s->fmbm_rstc);
+
+ /* Performance counters */
+ fman_port_set_perf_cnt_params(port, &cfg->perf_cnt_params);
+ tmp = 0;
+ if (cfg->perf_counters_enable)
+ tmp = BMI_COUNTERS_EN;
+ iowrite32be(tmp, ®s->fmbm_rpc);
+
+ return 0;
+}
+
+static int init_bmi_tx(struct fman_port *port,
+ struct fman_port_cfg *cfg,
+ struct fman_port_params *params)
+{
+ struct fman_port_tx_bmi_regs __iomem *regs = &port->bmi_regs->tx;
+ uint32_t tmp;
+
+ /* Tx Configuration register */
+ tmp = 0;
+ iowrite32be(tmp, ®s->fmbm_tcfg);
+
+ /* DMA attributes */
+ tmp = (uint32_t)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT;
+ if (cfg->dma_ic_stash_on)
+ tmp |= BMI_DMA_ATTR_IC_STASH_ON;
+ if (cfg->dma_header_stash_on)
+ tmp |= BMI_DMA_ATTR_HDR_STASH_ON;
+ if (cfg->dma_sg_stash_on)
+ tmp |= BMI_DMA_ATTR_SG_STASH_ON;
+ iowrite32be(tmp, ®s->fmbm_tda);
+
+ /* Tx FIFO parameters */
+ tmp = (cfg->tx_fifo_min_level / FMAN_PORT_BMI_FIFO_UNITS) <<
+ BMI_TX_FIFO_MIN_FILL_SHIFT;
+ tmp |= ((uint32_t)cfg->tx_fifo_deq_pipeline_depth - 1) <<
+ BMI_FIFO_PIPELINE_DEPTH_SHIFT;
+ tmp |= (uint32_t)(cfg->tx_fifo_low_comf_level /
+ FMAN_PORT_BMI_FIFO_UNITS - 1);
+ iowrite32be(tmp, ®s->fmbm_tfp);
+
+ /* Frame end data */
+ tmp = (uint32_t)cfg->checksum_bytes_ignore <<
+ BMI_FRAME_END_CS_IGNORE_SHIFT;
+ iowrite32be(tmp, ®s->fmbm_tfed);
+
+ /* Internal context parameters */
+ tmp = ((uint32_t)cfg->ic_ext_offset / FMAN_PORT_IC_OFFSET_UNITS) <<
+ BMI_IC_TO_EXT_SHIFT;
+ tmp |= ((uint32_t)cfg->ic_int_offset / FMAN_PORT_IC_OFFSET_UNITS) <<
+ BMI_IC_FROM_INT_SHIFT;
+ tmp |= cfg->ic_size / FMAN_PORT_IC_OFFSET_UNITS;
+ iowrite32be(tmp, ®s->fmbm_ticp);
+
+ /* Frame attributes */
+ tmp = BMI_CMD_TX_MR_DEF;
+ tmp |= BMI_CMD_ATTR_ORDER;
+ tmp |= (uint32_t)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT;
+ iowrite32be(tmp, ®s->fmbm_tfca);
+
+ /* Dequeue NIA + enqueue NIA */
+ iowrite32be(NIA_ENG_QMI_DEQ, ®s->fmbm_tfdne);
+ iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR, ®s->fmbm_tfene);
+ if (cfg->fmbm_tfne_has_features)
+ iowrite32be(!params->dflt_fqid ?
+ BMI_EBD_EN | NIA_BMI_AC_FETCH_ALL_FRAME :
+ NIA_BMI_AC_FETCH_ALL_FRAME, ®s->fmbm_tfne);
+ if (!params->dflt_fqid && params->dont_release_buf) {
+ iowrite32be(0x00FFFFFF, ®s->fmbm_tcfqid);
+ iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE,
+ ®s->fmbm_tfene);
+ if (cfg->fmbm_tfne_has_features)
+ iowrite32be(ioread32be(®s->fmbm_tfne) & ~BMI_EBD_EN,
+ ®s->fmbm_tfne);
+ }
+
+ /* Confirmation/error queues */
+ if (params->dflt_fqid || !params->dont_release_buf)
+ iowrite32be(params->dflt_fqid & 0x00FFFFFF, ®s->fmbm_tcfqid);
+ iowrite32be((params->err_fqid & 0x00FFFFFF), ®s->fmbm_tefqid);
+
+ /* Statistics counters */
+ tmp = 0;
+ if (cfg->stats_counters_enable)
+ tmp = BMI_COUNTERS_EN;
+ iowrite32be(tmp, ®s->fmbm_tstc);
+
+ /* Performance counters */
+ fman_port_set_perf_cnt_params(port, &cfg->perf_cnt_params);
+ tmp = 0;
+ if (cfg->perf_counters_enable)
+ tmp = BMI_COUNTERS_EN;
+ iowrite32be(tmp, ®s->fmbm_tpc);
+
+ return 0;
+}
+
+static int init_bmi_oh(struct fman_port *port,
+ struct fman_port_cfg *cfg,
+ struct fman_port_params *params)
+{
+ struct fman_port_oh_bmi_regs __iomem *regs = &port->bmi_regs->oh;
+ uint32_t tmp;
+
+ /* OP Configuration register */
+ tmp = 0;
+ if (cfg->discard_override)
+ tmp |= BMI_PORT_CFG_FDOVR;
+ iowrite32be(tmp, ®s->fmbm_ocfg);
+
+ /* DMA attributes */
+ tmp = (uint32_t)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT;
+ if (cfg->dma_ic_stash_on)
+ tmp |= BMI_DMA_ATTR_IC_STASH_ON;
+ if (cfg->dma_header_stash_on)
+ tmp |= BMI_DMA_ATTR_HDR_STASH_ON;
+ if (cfg->dma_sg_stash_on)
+ tmp |= BMI_DMA_ATTR_SG_STASH_ON;
+ if (cfg->dma_write_optimize)
+ tmp |= BMI_DMA_ATTR_WRITE_OPTIMIZE;
+ iowrite32be(tmp, ®s->fmbm_oda);
+
+ /* Tx FIFO parameters */
+ tmp = ((uint32_t)cfg->tx_fifo_deq_pipeline_depth - 1) <<
+ BMI_FIFO_PIPELINE_DEPTH_SHIFT;
+ iowrite32be(tmp, ®s->fmbm_ofp);
+
+ /* Internal context parameters */
+ tmp = ((uint32_t)cfg->ic_ext_offset / FMAN_PORT_IC_OFFSET_UNITS) <<
+ BMI_IC_TO_EXT_SHIFT;
+ tmp |= ((uint32_t)cfg->ic_int_offset / FMAN_PORT_IC_OFFSET_UNITS) <<
+ BMI_IC_FROM_INT_SHIFT;
+ tmp |= cfg->ic_size / FMAN_PORT_IC_OFFSET_UNITS;
+ iowrite32be(tmp, ®s->fmbm_oicp);
+
+ /* Frame attributes */
+ tmp = BMI_CMD_OP_MR_DEF;
+ tmp |= (uint32_t)cfg->color << BMI_CMD_ATTR_COLOR_SHIFT;
+ if (cfg->sync_req)
+ tmp |= BMI_CMD_ATTR_SYNC;
+ if (port->type == E_FMAN_PORT_TYPE_OP)
+ tmp |= BMI_CMD_ATTR_ORDER;
+ iowrite32be(tmp, ®s->fmbm_ofca);
+
+ /* Internal buffer offset */
+ tmp = ((uint32_t)cfg->int_buf_start_margin / FMAN_PORT_IC_OFFSET_UNITS)
+ << BMI_INT_BUF_MARG_SHIFT;
+ iowrite32be(tmp, ®s->fmbm_oim);
+
+ /* Dequeue NIA */
+ iowrite32be(NIA_ENG_QMI_DEQ, ®s->fmbm_ofdne);
+
+ /* NIA and Enqueue NIA */
+ if (port->type == E_FMAN_PORT_TYPE_HC) {
+ iowrite32be(NIA_ENG_FM_CTL | NIA_FM_CTL_AC_HC,
+ ®s->fmbm_ofne);
+ iowrite32be(NIA_ENG_QMI_ENQ, ®s->fmbm_ofene);
+ } else {
+ iowrite32be(get_no_pcd_nia_bmi_ac_enc_frame(cfg),
+ ®s->fmbm_ofne);
+ iowrite32be(NIA_ENG_QMI_ENQ | NIA_ORDER_RESTOR,
+ ®s->fmbm_ofene);
+ }
+
+ /* Default/error queues */
+ iowrite32be((params->dflt_fqid & 0x00FFFFFF), ®s->fmbm_ofqid);
+ iowrite32be((params->err_fqid & 0x00FFFFFF), ®s->fmbm_oefqid);
+
+ /* Discard/error masks */
+ if (port->type == E_FMAN_PORT_TYPE_OP) {
+ iowrite32be(params->discard_mask, ®s->fmbm_ofsdm);
+ iowrite32be(params->err_mask, ®s->fmbm_ofsem);
+ }
+
+ /* Statistics counters */
+ tmp = 0;
+ if (cfg->stats_counters_enable)
+ tmp = BMI_COUNTERS_EN;
+ iowrite32be(tmp, ®s->fmbm_ostc);
+
+ /* Performance counters */
+ fman_port_set_perf_cnt_params(port, &cfg->perf_cnt_params);
+ tmp = 0;
+ if (cfg->perf_counters_enable)
+ tmp = BMI_COUNTERS_EN;
+ iowrite32be(tmp, ®s->fmbm_opc);
+
+ return 0;
+}
+
+static int init_qmi(struct fman_port *port,
+ struct fman_port_cfg *cfg, struct fman_port_params *params)
+{
+ struct fman_port_qmi_regs __iomem *regs = port->qmi_regs;
+ uint32_t tmp;
+
+ tmp = 0;
+ if (cfg->queue_counters_enable)
+ tmp |= QMI_PORT_CFG_EN_COUNTERS;
+ iowrite32be(tmp, ®s->fmqm_pnc);
+
+ /* Rx port configuration */
+ if ((port->type == E_FMAN_PORT_TYPE_RX) ||
+ (port->type == E_FMAN_PORT_TYPE_RX_10G)) {
+ /* Enqueue NIA */
+ iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_RELEASE, ®s->fmqm_pnen);
+ return 0;
+ }
+
+ /* Continue with Tx and O/H port configuration */
+ if ((port->type == E_FMAN_PORT_TYPE_TX) ||
+ (port->type == E_FMAN_PORT_TYPE_TX_10G)) {
+ /* Enqueue NIA */
+ iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX_RELEASE,
+ ®s->fmqm_pnen);
+ /* Dequeue NIA */
+ iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_TX, ®s->fmqm_pndn);
+ } else {
+ /* Enqueue NIA */
+ iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_RELEASE, ®s->fmqm_pnen);
+ /* Dequeue NIA */
+ iowrite32be(NIA_ENG_BMI | NIA_BMI_AC_FETCH, ®s->fmqm_pndn);
+ }
+
+ /* Dequeue Configuration register */
+ tmp = 0;
+ if (cfg->deq_high_pri)
+ tmp |= QMI_DEQ_CFG_PRI;
+
+ switch (cfg->deq_type) {
+ case E_FMAN_PORT_DEQ_BY_PRI:
+ tmp |= QMI_DEQ_CFG_TYPE1;
+ break;
+ case E_FMAN_PORT_DEQ_ACTIVE_FQ:
+ tmp |= QMI_DEQ_CFG_TYPE2;
+ break;
+ case E_FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS:
+ tmp |= QMI_DEQ_CFG_TYPE3;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (cfg->qmi_deq_options_support) {
+ if ((port->type == E_FMAN_PORT_TYPE_HC) &&
+ (cfg->deq_prefetch_opt != E_FMAN_PORT_DEQ_NO_PREFETCH))
+ return -EINVAL;
+
+ switch (cfg->deq_prefetch_opt) {
+ case E_FMAN_PORT_DEQ_NO_PREFETCH:
+ break;
+ case E_FMAN_PORT_DEQ_PART_PREFETCH:
+ tmp |= QMI_DEQ_CFG_PREFETCH_PARTIAL;
+ break;
+ case E_FMAN_PORT_DEQ_FULL_PREFETCH:
+ tmp |= QMI_DEQ_CFG_PREFETCH_FULL;
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+ tmp |= (uint32_t)(params->deq_sp & QMI_DEQ_CFG_SP_MASK) <<
+ QMI_DEQ_CFG_SP_SHIFT;
+ tmp |= cfg->deq_byte_cnt;
+ iowrite32be(tmp, ®s->fmqm_pndc);
+
+ return 0;
+}
+
+static void get_rx_stats_reg(struct fman_port *port,
+ enum fman_port_stats_counters counter,
+ uint32_t __iomem **stats_reg)
+{
+ struct fman_port_rx_bmi_regs __iomem *regs = &port->bmi_regs->rx;
+
+ switch (counter) {
+ case E_FMAN_PORT_STATS_CNT_FRAME:
+ *stats_reg = ®s->fmbm_rfrc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_DISCARD:
+ *stats_reg = ®s->fmbm_rfdc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_DEALLOC_BUF:
+ *stats_reg = ®s->fmbm_rbdc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_RX_BAD_FRAME:
+ *stats_reg = ®s->fmbm_rfbc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_RX_LARGE_FRAME:
+ *stats_reg = ®s->fmbm_rlfc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_RX_OUT_OF_BUF:
+ *stats_reg = ®s->fmbm_rodc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_FILTERED_FRAME:
+ *stats_reg = ®s->fmbm_rffc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_DMA_ERR:
+ *stats_reg = ®s->fmbm_rfldec;
+ break;
+ default:
+ *stats_reg = NULL;
+ }
+}
+
+static void get_tx_stats_reg(struct fman_port *port,
+ enum fman_port_stats_counters counter,
+ uint32_t __iomem **stats_reg)
+{
+ struct fman_port_tx_bmi_regs __iomem *regs = &port->bmi_regs->tx;
+
+ switch (counter) {
+ case E_FMAN_PORT_STATS_CNT_FRAME:
+ *stats_reg = ®s->fmbm_tfrc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_DISCARD:
+ *stats_reg = ®s->fmbm_tfdc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_DEALLOC_BUF:
+ *stats_reg = ®s->fmbm_tbdc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_LEN_ERR:
+ *stats_reg = ®s->fmbm_tfledc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_UNSUPPORTED_FORMAT:
+ *stats_reg = ®s->fmbm_tfufdc;
+ break;
+ default:
+ *stats_reg = NULL;
+ }
+}
+
+static void get_oh_stats_reg(struct fman_port *port,
+ enum fman_port_stats_counters counter,
+ uint32_t __iomem **stats_reg)
+{
+ struct fman_port_oh_bmi_regs __iomem *regs = &port->bmi_regs->oh;
+
+ switch (counter) {
+ case E_FMAN_PORT_STATS_CNT_FRAME:
+ *stats_reg = ®s->fmbm_ofrc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_DISCARD:
+ *stats_reg = ®s->fmbm_ofdc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_DEALLOC_BUF:
+ *stats_reg = ®s->fmbm_obdc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_FILTERED_FRAME:
+ *stats_reg = ®s->fmbm_offc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_DMA_ERR:
+ *stats_reg = ®s->fmbm_ofldec;
+ break;
+ case E_FMAN_PORT_STATS_CNT_LEN_ERR:
+ *stats_reg = ®s->fmbm_ofledc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_UNSUPPORTED_FORMAT:
+ *stats_reg = ®s->fmbm_ofufdc;
+ break;
+ case E_FMAN_PORT_STATS_CNT_WRED_DISCARD:
+ *stats_reg = ®s->fmbm_ofwdc;
+ break;
+ default:
+ *stats_reg = NULL;
+ }
+}
+
+static void get_rx_perf_reg(struct fman_port *port,
+ enum fman_port_perf_counters counter,
+ uint32_t __iomem **perf_reg)
+{
+ struct fman_port_rx_bmi_regs __iomem *regs = &port->bmi_regs->rx;
+
+ switch (counter) {
+ case E_FMAN_PORT_PERF_CNT_CYCLE:
+ *perf_reg = ®s->fmbm_rccn;
+ break;
+ case E_FMAN_PORT_PERF_CNT_TASK_UTIL:
+ *perf_reg = ®s->fmbm_rtuc;
+ break;
+ case E_FMAN_PORT_PERF_CNT_QUEUE_UTIL:
+ *perf_reg = ®s->fmbm_rrquc;
+ break;
+ case E_FMAN_PORT_PERF_CNT_DMA_UTIL:
+ *perf_reg = ®s->fmbm_rduc;
+ break;
+ case E_FMAN_PORT_PERF_CNT_FIFO_UTIL:
+ *perf_reg = ®s->fmbm_rfuc;
+ break;
+ case E_FMAN_PORT_PERF_CNT_RX_PAUSE:
+ *perf_reg = ®s->fmbm_rpac;
+ break;
+ default:
+ *perf_reg = NULL;
+ }
+}
+
+static void get_tx_perf_reg(struct fman_port *port,
+ enum fman_port_perf_counters counter,
+ uint32_t __iomem **perf_reg)
+{
+ struct fman_port_tx_bmi_regs __iomem *regs = &port->bmi_regs->tx;
+
+ switch (counter) {
+ case E_FMAN_PORT_PERF_CNT_CYCLE:
+ *perf_reg = ®s->fmbm_tccn;
+ break;
+ case E_FMAN_PORT_PERF_CNT_TASK_UTIL:
+ *perf_reg = ®s->fmbm_ttuc;
+ break;
+ case E_FMAN_PORT_PERF_CNT_QUEUE_UTIL:
+ *perf_reg = ®s->fmbm_ttcquc;
+ break;
+ case E_FMAN_PORT_PERF_CNT_DMA_UTIL:
+ *perf_reg = ®s->fmbm_tduc;
+ break;
+ case E_FMAN_PORT_PERF_CNT_FIFO_UTIL:
+ *perf_reg = ®s->fmbm_tfuc;
+ break;
+ default:
+ *perf_reg = NULL;
+ }
+}
+
+static void get_oh_perf_reg(struct fman_port *port,
+ enum fman_port_perf_counters counter,
+ uint32_t __iomem **perf_reg)
+{
+ struct fman_port_oh_bmi_regs __iomem *regs = &port->bmi_regs->oh;
+
+ switch (counter) {
+ case E_FMAN_PORT_PERF_CNT_CYCLE:
+ *perf_reg = ®s->fmbm_occn;
+ break;
+ case E_FMAN_PORT_PERF_CNT_TASK_UTIL:
+ *perf_reg = ®s->fmbm_otuc;
+ break;
+ case E_FMAN_PORT_PERF_CNT_DMA_UTIL:
+ *perf_reg = ®s->fmbm_oduc;
+ break;
+ case E_FMAN_PORT_PERF_CNT_FIFO_UTIL:
+ *perf_reg = ®s->fmbm_ofuc;
+ break;
+ default:
+ *perf_reg = NULL;
+ }
+}
+
+static void get_qmi_counter_reg(struct fman_port *port,
+ enum fman_port_qmi_counters counter,
+ uint32_t __iomem **queue_reg)
+{
+ struct fman_port_qmi_regs __iomem *regs = port->qmi_regs;
+
+ switch (counter) {
+ case E_FMAN_PORT_ENQ_TOTAL:
+ *queue_reg = ®s->fmqm_pnetfc;
+ break;
+ case E_FMAN_PORT_DEQ_TOTAL:
+ if ((port->type == E_FMAN_PORT_TYPE_RX) ||
+ (port->type == E_FMAN_PORT_TYPE_RX_10G))
+ /* Counter not available for Rx ports */
+ *queue_reg = NULL;
+ else
+ *queue_reg = ®s->fmqm_pndtfc;
+ break;
+ case E_FMAN_PORT_DEQ_FROM_DFLT:
+ if ((port->type == E_FMAN_PORT_TYPE_RX) ||
+ (port->type == E_FMAN_PORT_TYPE_RX_10G))
+ /* Counter not available for Rx ports */
+ *queue_reg = NULL;
+ else
+ *queue_reg = ®s->fmqm_pndfdc;
+ break;
+ case E_FMAN_PORT_DEQ_CONFIRM:
+ if ((port->type == E_FMAN_PORT_TYPE_RX) ||
+ (port->type == E_FMAN_PORT_TYPE_RX_10G))
+ /* Counter not available for Rx ports */
+ *queue_reg = NULL;
+ else
+ *queue_reg = ®s->fmqm_pndcc;
+ break;
+ default:
+ *queue_reg = NULL;
+ }
+}
+
+void fman_port_defconfig(struct fman_port_cfg *cfg, enum fman_port_type type)
+{
+ cfg->dma_swap_data = E_FMAN_PORT_DMA_NO_SWAP;
+ cfg->dma_ic_stash_on = false;
+ cfg->dma_header_stash_on = false;
+ cfg->dma_sg_stash_on = false;
+ cfg->dma_write_optimize = true;
+ cfg->color = E_FMAN_PORT_COLOR_GREEN;
+ cfg->discard_override = false;
+ cfg->checksum_bytes_ignore = 0;
+ cfg->rx_cut_end_bytes = 4;
+ cfg->rx_pri_elevation = ((0x3FF + 1) * FMAN_PORT_BMI_FIFO_UNITS);
+ cfg->rx_fifo_thr = ((0x3FF + 1) * FMAN_PORT_BMI_FIFO_UNITS);
+ cfg->rx_fd_bits = 0;
+ cfg->ic_ext_offset = 0;
+ cfg->ic_int_offset = 0;
+ cfg->ic_size = 0;
+ cfg->int_buf_start_margin = 0;
+ cfg->ext_buf_start_margin = 0;
+ cfg->ext_buf_end_margin = 0;
+ cfg->tx_fifo_min_level = 0;
+ cfg->tx_fifo_low_comf_level = (5 * KILOBYTE);
+ cfg->stats_counters_enable = true;
+ cfg->perf_counters_enable = true;
+ cfg->deq_type = E_FMAN_PORT_DEQ_BY_PRI;
+
+ if (type == E_FMAN_PORT_TYPE_HC) {
+ cfg->sync_req = false;
+ cfg->deq_prefetch_opt = E_FMAN_PORT_DEQ_NO_PREFETCH;
+ } else {
+ cfg->sync_req = true;
+ cfg->deq_prefetch_opt = E_FMAN_PORT_DEQ_FULL_PREFETCH;
+ }
+
+ if (type == E_FMAN_PORT_TYPE_TX_10G) {
+ cfg->tx_fifo_deq_pipeline_depth = 4;
+ cfg->deq_high_pri = true;
+ cfg->deq_byte_cnt = 0x1400;
+ } else {
+ if ((type == E_FMAN_PORT_TYPE_HC) ||
+ (type == E_FMAN_PORT_TYPE_OP))
+ cfg->tx_fifo_deq_pipeline_depth = 2;
+ else
+ cfg->tx_fifo_deq_pipeline_depth = 1;
+
+ cfg->deq_high_pri = false;
+ cfg->deq_byte_cnt = 0x400;
+ }
+ cfg->no_scatter_gather = DEFAULT_FMAN_SP_NO_SCATTER_GATHER;
+}
+
+static uint8_t fman_port_find_bpool(struct fman_port *port, uint8_t bpid)
+{
+ uint32_t __iomem *bp_reg;
+ uint32_t tmp;
+ uint8_t i, id;
+
+ /* Find the pool */
+ bp_reg = port->bmi_regs->rx.fmbm_ebmpi;
+ for (i = 0;
+ (i < port->ext_pools_num && (i < FMAN_PORT_MAX_EXT_POOLS_NUM));
+ i++) {
+ tmp = ioread32be(&bp_reg[i]);
+ id = (uint8_t)((tmp & BMI_EXT_BUF_POOL_ID_MASK) >>
+ BMI_EXT_BUF_POOL_ID_SHIFT);
+
+ if (id == bpid)
+ break;
+ }
+
+ return i;
+}
+
+int fman_port_init(struct fman_port *port,
+ struct fman_port_cfg *cfg, struct fman_port_params *params)
+{
+ int err;
+
+ /* Init BMI registers */
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ err = init_bmi_rx(port, cfg, params);
+ break;
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ err = init_bmi_tx(port, cfg, params);
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ case E_FMAN_PORT_TYPE_HC:
+ err = init_bmi_oh(port, cfg, params);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (err)
+ return err;
+
+ /* Init QMI registers */
+ err = init_qmi(port, cfg, params);
+ return err;
+
+ return 0;
+}
+
+int fman_port_enable(struct fman_port *port)
+{
+ uint32_t __iomem *bmi_cfg_reg;
+ uint32_t tmp;
+ bool rx_port;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg;
+ rx_port = true;
+ break;
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg;
+ rx_port = false;
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ case E_FMAN_PORT_TYPE_HC:
+ bmi_cfg_reg = &port->bmi_regs->oh.fmbm_ocfg;
+ rx_port = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Enable QMI */
+ if (!rx_port) {
+ tmp = ioread32be(&port->qmi_regs->fmqm_pnc) | QMI_PORT_CFG_EN;
+ iowrite32be(tmp, &port->qmi_regs->fmqm_pnc);
+ }
+
+ /* Enable BMI */
+ tmp = ioread32be(bmi_cfg_reg) | BMI_PORT_CFG_EN;
+ iowrite32be(tmp, bmi_cfg_reg);
+
+ return 0;
+}
+
+int fman_port_disable(const struct fman_port *port)
+{
+ uint32_t __iomem *bmi_cfg_reg, *bmi_status_reg;
+ uint32_t tmp;
+ bool rx_port, failure = false;
+ int count;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ bmi_cfg_reg = &port->bmi_regs->rx.fmbm_rcfg;
+ bmi_status_reg = &port->bmi_regs->rx.fmbm_rst;
+ rx_port = true;
+ break;
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ bmi_cfg_reg = &port->bmi_regs->tx.fmbm_tcfg;
+ bmi_status_reg = &port->bmi_regs->tx.fmbm_tst;
+ rx_port = false;
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ case E_FMAN_PORT_TYPE_HC:
+ bmi_cfg_reg = &port->bmi_regs->oh.fmbm_ocfg;
+ bmi_status_reg = &port->bmi_regs->oh.fmbm_ost;
+ rx_port = false;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Disable QMI */
+ if (!rx_port) {
+ tmp = ioread32be(&port->qmi_regs->fmqm_pnc) & ~QMI_PORT_CFG_EN;
+ iowrite32be(tmp, &port->qmi_regs->fmqm_pnc);
+
+ /* Wait for QMI to finish FD handling */
+ count = 100;
+ do {
+ usleep_range(10, 11);
+ tmp = ioread32be(&port->qmi_regs->fmqm_pns);
+ } while ((tmp & QMI_PORT_STATUS_DEQ_FD_BSY) && --count);
+
+ if (count == 0) {
+ /* Timeout */
+ failure = true;
+ }
+ }
+
+ /* Disable BMI */
+ tmp = ioread32be(bmi_cfg_reg) & ~BMI_PORT_CFG_EN;
+ iowrite32be(tmp, bmi_cfg_reg);
+
+ /* Wait for graceful stop end */
+ count = 500;
+ do {
+ usleep_range(10, 11);
+ tmp = ioread32be(bmi_status_reg);
+ } while ((tmp & BMI_PORT_STATUS_BSY) && --count);
+
+ if (count == 0) {
+ /* Timeout */
+ failure = true;
+ }
+
+ if (failure)
+ return -EBUSY;
+
+ return 0;
+}
+
+int fman_port_set_bpools(const struct fman_port *port,
+ const struct fman_port_bpools *bp)
+{
+ uint32_t __iomem *bp_reg, *bp_depl_reg;
+ uint32_t tmp;
+ uint8_t i, max_bp_num;
+ bool grp_depl_used = false, rx_port;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ max_bp_num = port->ext_pools_num;
+ rx_port = true;
+ bp_reg = port->bmi_regs->rx.fmbm_ebmpi;
+ bp_depl_reg = &port->bmi_regs->rx.fmbm_mpd;
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ if (port->fm_rev_maj != 4)
+ return -EINVAL;
+ max_bp_num = FMAN_PORT_OBS_EXT_POOLS_NUM;
+ rx_port = false;
+ bp_reg = port->bmi_regs->oh.fmbm_oebmpi;
+ bp_depl_reg = &port->bmi_regs->oh.fmbm_ompd;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (rx_port) {
+ /* Check buffers are provided in ascending order */
+ for (i = 0; (i < (bp->count - 1) &&
+ (i < FMAN_PORT_MAX_EXT_POOLS_NUM - 1)); i++) {
+ if (bp->bpool[i].size > bp->bpool[i + 1].size)
+ return -EINVAL;
+ }
+ }
+
+ /* Set up external buffers pools */
+ for (i = 0; i < bp->count; i++) {
+ tmp = BMI_EXT_BUF_POOL_VALID;
+ tmp |= ((uint32_t)bp->bpool[i].bpid <<
+ BMI_EXT_BUF_POOL_ID_SHIFT) & BMI_EXT_BUF_POOL_ID_MASK;
+
+ if (rx_port) {
+ if (bp->counters_enable)
+ tmp |= BMI_EXT_BUF_POOL_EN_COUNTER;
+
+ if (bp->bpool[i].is_backup)
+ tmp |= BMI_EXT_BUF_POOL_BACKUP;
+
+ tmp |= (uint32_t)bp->bpool[i].size;
+ }
+
+ iowrite32be(tmp, &bp_reg[i]);
+ }
+
+ /* Clear unused pools */
+ for (i = bp->count; i < max_bp_num; i++)
+ iowrite32be(0, &bp_reg[i]);
+
+ /* Pools depletion */
+ tmp = 0;
+ for (i = 0; i < FMAN_PORT_MAX_EXT_POOLS_NUM; i++) {
+ if (bp->bpool[i].grp_bp_depleted) {
+ grp_depl_used = true;
+ tmp |= 0x80000000 >> i;
+ }
+
+ if (bp->bpool[i].single_bp_depleted)
+ tmp |= 0x80 >> i;
+
+ if (bp->bpool[i].pfc_priorities_en)
+ tmp |= 0x0100 << i;
+ }
+
+ if (grp_depl_used)
+ tmp |= ((uint32_t)bp->grp_bp_depleted_num - 1) <<
+ BMI_POOL_DEP_NUM_OF_POOLS_SHIFT;
+
+ iowrite32be(tmp, bp_depl_reg);
+ return 0;
+}
+
+int fman_port_set_rate_limiter(struct fman_port *port,
+ struct fman_port_rate_limiter *rate_limiter)
+{
+ uint32_t __iomem *rate_limit_reg, *rate_limit_scale_reg;
+ uint32_t granularity, tmp;
+ uint8_t usec_bit, factor;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ rate_limit_reg = &port->bmi_regs->tx.fmbm_trlmt;
+ rate_limit_scale_reg = &port->bmi_regs->tx.fmbm_trlmts;
+ granularity = BMI_RATE_LIMIT_GRAN_TX;
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ rate_limit_reg = &port->bmi_regs->oh.fmbm_orlmt;
+ rate_limit_scale_reg = &port->bmi_regs->oh.fmbm_orlmts;
+ granularity = BMI_RATE_LIMIT_GRAN_OP;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Factor is per 1 usec count */
+ factor = 1;
+ usec_bit = rate_limiter->count_1micro_bit;
+
+ /* If rate limit is too small for an 1usec factor, adjust timestamp
+ * scale and multiply the factor
+ **/
+ while (rate_limiter->rate < (granularity / factor)) {
+ if (usec_bit == 31)
+ /* Can't configure rate limiter - rate is too small */
+ return -EINVAL;
+
+ usec_bit++;
+ factor <<= 1;
+ }
+
+ /* Figure out register value. The "while" above quarantees that
+ * (rate_limiter->rate*factor / granularity) >= 1
+ **/
+ tmp = (uint32_t)(rate_limiter->rate * factor / granularity - 1);
+
+ /* Check rate limit isn't too large */
+ if (tmp >= BMI_RATE_LIMIT_MAX_RATE_IN_GRAN_UNITS)
+ return -EINVAL;
+
+ /* Check burst size is in allowed range */
+ if ((rate_limiter->burst_size == 0) ||
+ (rate_limiter->burst_size > BMI_RATE_LIMIT_MAX_BURST_SIZE))
+ return -EINVAL;
+
+ tmp |= (uint32_t)(rate_limiter->burst_size - 1) <<
+ BMI_RATE_LIMIT_MAX_BURST_SHIFT;
+
+ if ((port->type == E_FMAN_PORT_TYPE_OP) && (port->fm_rev_maj == 4)) {
+ if (rate_limiter->high_burst_size_gran)
+ tmp |= BMI_RATE_LIMIT_HIGH_BURST_SIZE_GRAN;
+ }
+
+ iowrite32be(tmp, rate_limit_reg);
+
+ /* Set up rate limiter scale register */
+ tmp = BMI_RATE_LIMIT_SCALE_EN;
+ tmp |= (31 - (uint32_t)usec_bit) << BMI_RATE_LIMIT_SCALE_TSBS_SHIFT;
+
+ if ((port->type == E_FMAN_PORT_TYPE_OP) && (port->fm_rev_maj == 4))
+ tmp |= rate_limiter->rate_factor;
+
+ iowrite32be(tmp, rate_limit_scale_reg);
+
+ return 0;
+}
+
+int fman_port_delete_rate_limiter(struct fman_port *port)
+{
+ uint32_t __iomem *rate_limit_scale_reg;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ rate_limit_scale_reg = &port->bmi_regs->tx.fmbm_trlmts;
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ rate_limit_scale_reg = &port->bmi_regs->oh.fmbm_orlmts;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ iowrite32be(0, rate_limit_scale_reg);
+ return 0;
+}
+
+int fman_port_set_err_mask(struct fman_port *port, uint32_t err_mask)
+{
+ uint32_t __iomem *err_mask_reg;
+
+ /* Obtain register address */
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ err_mask_reg = &port->bmi_regs->rx.fmbm_rfsem;
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ err_mask_reg = &port->bmi_regs->oh.fmbm_ofsem;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ iowrite32be(err_mask, err_mask_reg);
+ return 0;
+}
+
+int fman_port_set_discard_mask(struct fman_port *port, uint32_t discard_mask)
+{
+ uint32_t __iomem *discard_mask_reg;
+
+ /* Obtain register address */
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ discard_mask_reg = &port->bmi_regs->rx.fmbm_rfsdm;
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ discard_mask_reg = &port->bmi_regs->oh.fmbm_ofsdm;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ iowrite32be(discard_mask, discard_mask_reg);
+ return 0;
+}
+
+int fman_port_modify_rx_fd_bits(struct fman_port *port,
+ uint8_t rx_fd_bits, bool add)
+{
+ uint32_t tmp;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ tmp = ioread32be(&port->bmi_regs->rx.fmbm_rfne);
+
+ if (add)
+ tmp |= (uint32_t)rx_fd_bits << BMI_NEXT_ENG_FD_BITS_SHIFT;
+ else
+ tmp &= ~((uint32_t)rx_fd_bits << BMI_NEXT_ENG_FD_BITS_SHIFT);
+
+ iowrite32be(tmp, &port->bmi_regs->rx.fmbm_rfne);
+ return 0;
+}
+
+int fman_port_set_perf_cnt_params(struct fman_port *port,
+ struct fman_port_perf_cnt_params *params)
+{
+ uint32_t __iomem *pcp_reg;
+ uint32_t tmp;
+
+ /* Obtain register address and check parameters are in range */
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ pcp_reg = &port->bmi_regs->rx.fmbm_rpcp;
+ if ((params->queue_val == 0) ||
+ (params->queue_val > MAX_PERFORMANCE_RX_QUEUE_COMP))
+ return -EINVAL;
+ break;
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ pcp_reg = &port->bmi_regs->tx.fmbm_tpcp;
+ if ((params->queue_val == 0) ||
+ (params->queue_val > MAX_PERFORMANCE_TX_QUEUE_COMP))
+ return -EINVAL;
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ case E_FMAN_PORT_TYPE_HC:
+ pcp_reg = &port->bmi_regs->oh.fmbm_opcp;
+ if (params->queue_val != 0)
+ return -EINVAL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if ((params->task_val == 0) ||
+ (params->task_val > MAX_PERFORMANCE_TASK_COMP))
+ return -EINVAL;
+ if ((params->dma_val == 0) ||
+ (params->dma_val > MAX_PERFORMANCE_DMA_COMP))
+ return -EINVAL;
+ if ((params->fifo_val == 0) ||
+ ((params->fifo_val / FMAN_PORT_BMI_FIFO_UNITS) >
+ MAX_PERFORMANCE_FIFO_COMP))
+ return -EINVAL;
+ tmp = (uint32_t)(params->task_val - 1) <<
+ BMI_PERFORMANCE_TASK_COMP_SHIFT;
+ tmp |= (uint32_t)(params->dma_val - 1) <<
+ BMI_PERFORMANCE_DMA_COMP_SHIFT;
+ tmp |= (uint32_t)(params->fifo_val / FMAN_PORT_BMI_FIFO_UNITS - 1);
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ tmp |= (uint32_t)(params->queue_val - 1) <<
+ BMI_PERFORMANCE_QUEUE_COMP_SHIFT;
+ break;
+ default:
+ break;
+ }
+
+ iowrite32be(tmp, pcp_reg);
+ return 0;
+}
+
+int fman_port_set_stats_cnt_mode(struct fman_port *port, bool enable)
+{
+ uint32_t __iomem *stats_reg;
+ uint32_t tmp;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ stats_reg = &port->bmi_regs->rx.fmbm_rstc;
+ break;
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ stats_reg = &port->bmi_regs->tx.fmbm_tstc;
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ case E_FMAN_PORT_TYPE_HC:
+ stats_reg = &port->bmi_regs->oh.fmbm_ostc;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ tmp = ioread32be(stats_reg);
+
+ if (enable)
+ tmp |= BMI_COUNTERS_EN;
+ else
+ tmp &= ~BMI_COUNTERS_EN;
+
+ iowrite32be(tmp, stats_reg);
+ return 0;
+}
+
+int fman_port_set_perf_cnt_mode(struct fman_port *port, bool enable)
+{
+ uint32_t __iomem *stats_reg;
+ uint32_t tmp;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ stats_reg = &port->bmi_regs->rx.fmbm_rpc;
+ break;
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ stats_reg = &port->bmi_regs->tx.fmbm_tpc;
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ case E_FMAN_PORT_TYPE_HC:
+ stats_reg = &port->bmi_regs->oh.fmbm_opc;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ tmp = ioread32be(stats_reg);
+
+ if (enable)
+ tmp |= BMI_COUNTERS_EN;
+ else
+ tmp &= ~BMI_COUNTERS_EN;
+
+ iowrite32be(tmp, stats_reg);
+ return 0;
+}
+
+int fman_port_set_queue_cnt_mode(struct fman_port *port, bool enable)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(&port->qmi_regs->fmqm_pnc);
+
+ if (enable)
+ tmp |= QMI_PORT_CFG_EN_COUNTERS;
+ else
+ tmp &= ~QMI_PORT_CFG_EN_COUNTERS;
+
+ iowrite32be(tmp, &port->qmi_regs->fmqm_pnc);
+ return 0;
+}
+
+int fman_port_set_bpool_cnt_mode(struct fman_port *port,
+ uint8_t bpid, bool enable)
+{
+ uint8_t index;
+ uint32_t tmp;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* Find the pool */
+ index = fman_port_find_bpool(port, bpid);
+ if (index == port->ext_pools_num ||
+ index == FMAN_PORT_MAX_EXT_POOLS_NUM)
+ /* Not found */
+ return -EINVAL;
+
+ tmp = ioread32be(&port->bmi_regs->rx.fmbm_ebmpi[index]);
+
+ if (enable)
+ tmp |= BMI_EXT_BUF_POOL_EN_COUNTER;
+ else
+ tmp &= ~BMI_EXT_BUF_POOL_EN_COUNTER;
+
+ iowrite32be(tmp, &port->bmi_regs->rx.fmbm_ebmpi[index]);
+ return 0;
+}
+
+uint32_t fman_port_get_stats_counter(struct fman_port *port,
+ enum fman_port_stats_counters counter)
+{
+ uint32_t __iomem *stats_reg;
+ uint32_t ret_val;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ get_rx_stats_reg(port, counter, &stats_reg);
+ break;
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ get_tx_stats_reg(port, counter, &stats_reg);
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ case E_FMAN_PORT_TYPE_HC:
+ get_oh_stats_reg(port, counter, &stats_reg);
+ break;
+ default:
+ stats_reg = NULL;
+ }
+
+ if (!stats_reg)
+ return 0;
+
+ ret_val = ioread32be(stats_reg);
+ return ret_val;
+}
+
+void fman_port_set_stats_counter(struct fman_port *port,
+ enum fman_port_stats_counters counter,
+ uint32_t value)
+{
+ uint32_t __iomem *stats_reg;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ get_rx_stats_reg(port, counter, &stats_reg);
+ break;
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ get_tx_stats_reg(port, counter, &stats_reg);
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ case E_FMAN_PORT_TYPE_HC:
+ get_oh_stats_reg(port, counter, &stats_reg);
+ break;
+ default:
+ stats_reg = NULL;
+ }
+
+ if (!stats_reg)
+ return;
+
+ iowrite32be(value, stats_reg);
+}
+
+uint32_t fman_port_get_perf_counter(struct fman_port *port,
+ enum fman_port_perf_counters counter)
+{
+ uint32_t __iomem *perf_reg;
+ uint32_t ret_val;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ get_rx_perf_reg(port, counter, &perf_reg);
+ break;
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ get_tx_perf_reg(port, counter, &perf_reg);
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ case E_FMAN_PORT_TYPE_HC:
+ get_oh_perf_reg(port, counter, &perf_reg);
+ break;
+ default:
+ perf_reg = NULL;
+ }
+
+ if (!perf_reg)
+ return 0;
+
+ ret_val = ioread32be(perf_reg);
+ return ret_val;
+}
+
+void fman_port_set_perf_counter(struct fman_port *port,
+ enum fman_port_perf_counters counter,
+ uint32_t value)
+{
+ uint32_t __iomem *perf_reg;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ get_rx_perf_reg(port, counter, &perf_reg);
+ break;
+ case E_FMAN_PORT_TYPE_TX:
+ case E_FMAN_PORT_TYPE_TX_10G:
+ get_tx_perf_reg(port, counter, &perf_reg);
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ case E_FMAN_PORT_TYPE_HC:
+ get_oh_perf_reg(port, counter, &perf_reg);
+ break;
+ default:
+ perf_reg = NULL;
+ }
+
+ if (!perf_reg)
+ return;
+
+ iowrite32be(value, perf_reg);
+}
+
+uint32_t fman_port_get_qmi_counter(struct fman_port *port,
+ enum fman_port_qmi_counters counter)
+{
+ uint32_t __iomem *queue_reg;
+ uint32_t ret_val;
+
+ get_qmi_counter_reg(port, counter, &queue_reg);
+
+ if (!queue_reg)
+ return 0;
+
+ ret_val = ioread32be(queue_reg);
+ return ret_val;
+}
+
+void fman_port_set_qmi_counter(struct fman_port *port,
+ enum fman_port_qmi_counters counter,
+ uint32_t value)
+{
+ uint32_t __iomem *queue_reg;
+
+ get_qmi_counter_reg(port, counter, &queue_reg);
+
+ if (!queue_reg)
+ return;
+
+ iowrite32be(value, queue_reg);
+}
+
+uint32_t fman_port_get_bpool_counter(struct fman_port *port, uint8_t bpid)
+{
+ uint8_t index;
+ uint32_t ret_val;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ break;
+ default:
+ return 0;
+ }
+
+ /* Find the pool */
+ index = fman_port_find_bpool(port, bpid);
+ if (index == port->ext_pools_num ||
+ index == FMAN_PORT_MAX_EXT_POOLS_NUM)
+ /* Not found */
+ return 0;
+
+ ret_val = ioread32be(&port->bmi_regs->rx.fmbm_acnt[index]);
+ return ret_val;
+}
+
+void fman_port_set_bpool_counter(struct fman_port *port,
+ uint8_t bpid, uint32_t value)
+{
+ uint8_t index;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ break;
+ default:
+ return;
+ }
+
+ /* Find the pool */
+ index = fman_port_find_bpool(port, bpid);
+ if (index == port->ext_pools_num ||
+ index == FMAN_PORT_MAX_EXT_POOLS_NUM)
+ /* Not found */
+ return;
+
+ iowrite32be(value, &port->bmi_regs->rx.fmbm_acnt[index]);
+}
+
+int fman_port_add_congestion_grps(struct fman_port *port,
+ uint32_t grps_map[FMAN_PORT_CG_MAP_NUM])
+{
+ int i;
+ uint32_t __iomem *grp_map_reg;
+ uint32_t tmp;
+ uint8_t max_grp_map_num;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ if (port->fm_rev_maj == 4)
+ max_grp_map_num = 1;
+ else
+ max_grp_map_num = FMAN_PORT_CG_MAP_NUM;
+ grp_map_reg = port->bmi_regs->rx.fmbm_rcgm;
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ max_grp_map_num = 1;
+ if (port->fm_rev_maj != 4)
+ return -EINVAL;
+ grp_map_reg = &port->bmi_regs->oh.fmbm_ocgm;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ for (i = (max_grp_map_num - 1); i >= 0; i--) {
+ if (grps_map[i] == 0)
+ continue;
+ tmp = ioread32be(&grp_map_reg[i]);
+ tmp |= grps_map[i];
+ iowrite32be(tmp, &grp_map_reg[i]);
+ }
+
+ return 0;
+}
+
+int fman_port_remove_congestion_grps(struct fman_port *port,
+ uint32_t grps_map[FMAN_PORT_CG_MAP_NUM])
+{
+ int i;
+ uint32_t __iomem *grp_map_reg;
+ uint32_t tmp;
+ uint8_t max_grp_map_num;
+
+ switch (port->type) {
+ case E_FMAN_PORT_TYPE_RX:
+ case E_FMAN_PORT_TYPE_RX_10G:
+ if (port->fm_rev_maj == 4)
+ max_grp_map_num = 1;
+ else
+ max_grp_map_num = FMAN_PORT_CG_MAP_NUM;
+ grp_map_reg = port->bmi_regs->rx.fmbm_rcgm;
+ break;
+ case E_FMAN_PORT_TYPE_OP:
+ max_grp_map_num = 1;
+ if (port->fm_rev_maj != 4)
+ return -EINVAL;
+ grp_map_reg = &port->bmi_regs->oh.fmbm_ocgm;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ for (i = (max_grp_map_num - 1); i >= 0; i--) {
+ if (grps_map[i] == 0)
+ continue;
+ tmp = ioread32be(&grp_map_reg[i]);
+ tmp &= ~grps_map[i];
+ iowrite32be(tmp, &grp_map_reg[i]);
+ }
+ return 0;
+}
--
2.3.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 4/7] soc/fman: Add the FMan MAC FLIB
2015-03-05 5:45 [PATCH 0/7] Freescale DPAA FMan FLIB(s) Emil Medve
` (2 preceding siblings ...)
2015-03-05 5:45 ` [PATCH 3/7] soc/fman: Add the FMan port FLIB Emil Medve
@ 2015-03-05 5:45 ` Emil Medve
2015-03-05 5:45 ` [PATCH 5/7] soc/fman: Add the FMan parser and KeyGen FLIB(s) Emil Medve
` (3 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Emil Medve @ 2015-03-05 5:45 UTC (permalink / raw)
To: linuxppc-dev, netdev, linux-kernel; +Cc: Igal Liberman
From: Igal Liberman <Igal.Liberman@freescale.com>
Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
---
drivers/soc/fsl/fman/Kconfig | 6 +
drivers/soc/fsl/fman/Makefile | 7 +-
drivers/soc/fsl/fman/mac/Makefile | 15 +
drivers/soc/fsl/fman/mac/fman_crc32.c | 117 ++++
drivers/soc/fsl/fman/mac/fman_crc32.h | 40 ++
drivers/soc/fsl/fman/mac/fman_dtsec.c | 844 ++++++++++++++++++++++++++
drivers/soc/fsl/fman/mac/fman_dtsec_mii_acc.c | 169 ++++++
drivers/soc/fsl/fman/mac/fman_memac.c | 504 +++++++++++++++
drivers/soc/fsl/fman/mac/fman_memac_mii_acc.c | 218 +++++++
drivers/soc/fsl/fman/mac/fman_tgec.c | 372 ++++++++++++
10 files changed, 2289 insertions(+), 3 deletions(-)
create mode 100644 drivers/soc/fsl/fman/mac/Makefile
create mode 100644 drivers/soc/fsl/fman/mac/fman_crc32.c
create mode 100644 drivers/soc/fsl/fman/mac/fman_crc32.h
create mode 100644 drivers/soc/fsl/fman/mac/fman_dtsec.c
create mode 100644 drivers/soc/fsl/fman/mac/fman_dtsec_mii_acc.c
create mode 100644 drivers/soc/fsl/fman/mac/fman_memac.c
create mode 100644 drivers/soc/fsl/fman/mac/fman_memac_mii_acc.c
create mode 100644 drivers/soc/fsl/fman/mac/fman_tgec.c
diff --git a/drivers/soc/fsl/fman/Kconfig b/drivers/soc/fsl/fman/Kconfig
index a5f981f..c1c258c 100644
--- a/drivers/soc/fsl/fman/Kconfig
+++ b/drivers/soc/fsl/fman/Kconfig
@@ -14,4 +14,10 @@ config FSL_FMAN_PORT
help
Freescale DPAA FMan port support
+config FSL_FMAN_MAC
+ bool "FMan MAC"
+ default n
+ help
+ Freescale DPAA FMan MAC support
+
endif # FSL_FMAN
diff --git a/drivers/soc/fsl/fman/Makefile b/drivers/soc/fsl/fman/Makefile
index a0132cc..ffaabd9 100644
--- a/drivers/soc/fsl/fman/Makefile
+++ b/drivers/soc/fsl/fman/Makefile
@@ -6,10 +6,11 @@ FMAN = $(srctree)/drivers/soc/fsl/fman
ccflags-y += -I$(FMAN)/flib
-obj-$(CONFIG_FSL_FMAN) += fsl_fman.o
+obj-$(CONFIG_FSL_FMAN) += fsl_fman.o
-fsl_fman-objs := fman.o
+fsl_fman-objs := fman.o
-obj-$(CONFIG_FSL_FMAN_PORT) += port/
+obj-$(CONFIG_FSL_FMAN_PORT) += port/
+obj-$(CONFIG_FSL_FMAN_MAC) += mac/
endif
diff --git a/drivers/soc/fsl/fman/mac/Makefile b/drivers/soc/fsl/fman/mac/Makefile
new file mode 100644
index 0000000..3188c46
--- /dev/null
+++ b/drivers/soc/fsl/fman/mac/Makefile
@@ -0,0 +1,15 @@
+ccflags-y += -DVERSION=\"\"
+
+ifeq ($(CONFIG_FSL_FMAN_MAC),y)
+
+FMAN = $(srctree)/drivers/soc/fsl/fman
+
+ccflags-y += -I$(FMAN)/flib
+
+obj-$(CONFIG_FSL_FMAN_MAC) += fsl_fman_mac.o
+
+fsl_fman_mac-objs := fman_dtsec.o fman_dtsec_mii_acc.o \
+ fman_memac.o fman_tgec.o \
+ fman_crc32.o fman_memac_mii_acc.o
+
+endif
diff --git a/drivers/soc/fsl/fman/mac/fman_crc32.c b/drivers/soc/fsl/fman/mac/fman_crc32.c
new file mode 100644
index 0000000..2c85178
--- /dev/null
+++ b/drivers/soc/fsl/fman/mac/fman_crc32.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fman_crc32.h"
+#include "common/general.h"
+
+/* precomputed CRC values for address hashing */
+static const uint32_t crc_tbl[256] = {
+ 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
+ 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+ 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
+ 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+ 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
+ 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+ 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
+ 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+ 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
+ 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+ 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
+ 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+ 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
+ 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+ 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
+ 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+ 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
+ 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+ 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
+ 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+ 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
+ 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+ 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
+ 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+ 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
+ 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+ 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
+ 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+ 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
+ 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+ 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
+ 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+ 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
+ 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+ 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
+ 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+ 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
+ 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+ 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
+ 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+ 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
+ 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+ 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
+};
+
+/* Get the mirrored value of a byte size number. (0x11010011 --> 0x11001011) */
+static inline uint8_t get_mirror8(uint8_t n)
+{
+ uint8_t mirror[16] = {
+ 0x00, 0x08, 0x04, 0x0c, 0x02, 0x0a, 0x06, 0x0e,
+ 0x01, 0x09, 0x05, 0x0d, 0x03, 0x0b, 0x07, 0x0f
+ };
+ return (uint8_t)(((mirror[n & 0x0f] << 4) | (mirror[n >> 4])));
+}
+
+static inline uint32_t get_mirror32(uint32_t n)
+{
+ return ((uint32_t)get_mirror8((uint8_t)(n)) << 24) |
+ ((uint32_t)get_mirror8((uint8_t)(n >> 8)) << 16) |
+ ((uint32_t)get_mirror8((uint8_t)(n >> 16)) << 8) |
+ ((uint32_t)get_mirror8((uint8_t)(n >> 24)));
+}
+
+uint32_t get_mac_addr_crc(uint64_t _addr)
+{
+ uint32_t i;
+ uint8_t data;
+ uint32_t crc;
+
+ /* CRC calculation */
+ crc = 0xffffffff;
+ for (i = 0; i < 6; i++) {
+ data = (uint8_t)(_addr >> ((5 - i) * 8));
+ crc = crc ^ data;
+ crc = crc_tbl[crc & 0xff] ^ (crc >> 8);
+ }
+
+ crc = get_mirror32(crc);
+ return crc;
+}
diff --git a/drivers/soc/fsl/fman/mac/fman_crc32.h b/drivers/soc/fsl/fman/mac/fman_crc32.h
new file mode 100644
index 0000000..9e7c518
--- /dev/null
+++ b/drivers/soc/fsl/fman/mac/fman_crc32.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FMAN_CRC32_H
+#define __FMAN_CRC32_H
+
+#include "common/general.h"
+
+uint32_t get_mac_addr_crc(uint64_t _addr);
+
+#endif /* __FMAN_CRC32_H */
diff --git a/drivers/soc/fsl/fman/mac/fman_dtsec.c b/drivers/soc/fsl/fman/mac/fman_dtsec.c
new file mode 100644
index 0000000..f3abbd5
--- /dev/null
+++ b/drivers/soc/fsl/fman/mac/fman_dtsec.c
@@ -0,0 +1,844 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fman_dtsec.h"
+
+void fman_dtsec_stop_rx(struct dtsec_regs __iomem *regs)
+{
+ /* Assert the graceful stop bit */
+ iowrite32be(ioread32be(®s->rctrl) | RCTRL_GRS, ®s->rctrl);
+}
+
+void fman_dtsec_stop_tx(struct dtsec_regs __iomem *regs)
+{
+ /* Assert the graceful stop bit */
+ iowrite32be(ioread32be(®s->tctrl) | DTSEC_TCTRL_GTS, ®s->tctrl);
+}
+
+void fman_dtsec_start_tx(struct dtsec_regs __iomem *regs)
+{
+ /* clear the graceful stop bit */
+ iowrite32be(ioread32be(®s->tctrl) & ~DTSEC_TCTRL_GTS, ®s->tctrl);
+}
+
+void fman_dtsec_start_rx(struct dtsec_regs __iomem *regs)
+{
+ /* clear the graceful stop bit */
+ iowrite32be(ioread32be(®s->rctrl) & ~RCTRL_GRS, ®s->rctrl);
+}
+
+void fman_dtsec_defconfig(struct dtsec_cfg *cfg)
+{
+ cfg->halfdup_on = DEFAULT_HALFDUP_ON;
+ cfg->halfdup_retransmit = DEFAULT_HALFDUP_RETRANSMIT;
+ cfg->halfdup_coll_window = DEFAULT_HALFDUP_COLL_WINDOW;
+ cfg->halfdup_excess_defer = DEFAULT_HALFDUP_EXCESS_DEFER;
+ cfg->halfdup_no_backoff = DEFAULT_HALFDUP_NO_BACKOFF;
+ cfg->halfdup_bp_no_backoff = DEFAULT_HALFDUP_BP_NO_BACKOFF;
+ cfg->halfdup_alt_backoff_val = DEFAULT_HALFDUP_ALT_BACKOFF_VAL;
+ cfg->halfdup_alt_backoff_en = DEFAULT_HALFDUP_ALT_BACKOFF_EN;
+ cfg->rx_drop_bcast = DEFAULT_RX_DROP_BCAST;
+ cfg->rx_short_frm = DEFAULT_RX_SHORT_FRM;
+ cfg->rx_len_check = DEFAULT_RX_LEN_CHECK;
+ cfg->tx_pad_crc = DEFAULT_TX_PAD_CRC;
+ cfg->tx_crc = DEFAULT_TX_CRC;
+ cfg->rx_ctrl_acc = DEFAULT_RX_CTRL_ACC;
+ cfg->tx_pause_time = DEFAULT_TX_PAUSE_TIME;
+ /* PHY address 0 is reserved (DPAA RM) */
+ cfg->tbipa = DEFAULT_TBIPA;
+ cfg->rx_prepend = DEFAULT_RX_PREPEND;
+ cfg->ptp_tsu_en = DEFAULT_PTP_TSU_EN;
+ cfg->ptp_exception_en = DEFAULT_PTP_EXCEPTION_EN;
+ cfg->preamble_len = DEFAULT_PREAMBLE_LEN;
+ cfg->rx_preamble = DEFAULT_RX_PREAMBLE;
+ cfg->tx_preamble = DEFAULT_TX_PREAMBLE;
+ cfg->loopback = DEFAULT_LOOPBACK;
+ cfg->rx_time_stamp_en = DEFAULT_RX_TIME_STAMP_EN;
+ cfg->tx_time_stamp_en = DEFAULT_TX_TIME_STAMP_EN;
+ cfg->rx_flow = DEFAULT_RX_FLOW;
+ cfg->tx_flow = DEFAULT_TX_FLOW;
+ cfg->rx_group_hash_exd = DEFAULT_RX_GROUP_HASH_EXD;
+ cfg->tx_pause_time_extd = DEFAULT_TX_PAUSE_TIME_EXTD;
+ cfg->rx_promisc = DEFAULT_RX_PROMISC;
+ cfg->non_back_to_back_ipg1 = DEFAULT_NON_BACK_TO_BACK_IPG1;
+ cfg->non_back_to_back_ipg2 = DEFAULT_NON_BACK_TO_BACK_IPG2;
+ cfg->min_ifg_enforcement = DEFAULT_MIN_IFG_ENFORCEMENT;
+ cfg->back_to_back_ipg = DEFAULT_BACK_TO_BACK_IPG;
+ cfg->maximum_frame = DEFAULT_MAXIMUM_FRAME;
+ cfg->tbi_phy_addr = DEFAULT_TBI_PHY_ADDR;
+ cfg->wake_on_lan = DEFAULT_WAKE_ON_LAN;
+}
+
+int fman_dtsec_init(struct dtsec_regs __iomem *regs, struct dtsec_cfg *cfg,
+ enum enet_interface iface_mode,
+ enum enet_speed iface_speed,
+ uint8_t *macaddr,
+ uint8_t fm_rev_maj,
+ uint8_t fm_rev_min, uint32_t exception_mask)
+{
+ bool is_rgmii, is_sgmii, is_qsgmii;
+ int i;
+ uint32_t tmp;
+
+ UNUSED(fm_rev_maj);
+ UNUSED(fm_rev_min);
+
+ /* let's start with a soft reset */
+ iowrite32be(MACCFG1_SOFT_RESET, ®s->maccfg1);
+ iowrite32be(0, ®s->maccfg1);
+
+ /*dtsec_id2*/
+ tmp = ioread32be(®s->tsec_id2);
+
+ /* check RGMII support */
+ if (iface_mode == E_ENET_IF_RGMII || iface_mode == E_ENET_IF_RMII)
+ if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
+ return -EINVAL;
+
+ if (iface_mode == E_ENET_IF_SGMII || iface_mode == E_ENET_IF_MII)
+ if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
+ return -EINVAL;
+
+ /*ECNTRL*/
+
+ is_rgmii = (bool)((iface_mode == E_ENET_IF_RGMII) ? true : false);
+ is_sgmii = (bool)((iface_mode == E_ENET_IF_SGMII) ? true : false);
+ is_qsgmii = (bool)((iface_mode == E_ENET_IF_QSGMII) ? true : false);
+
+ tmp = 0;
+ if (is_rgmii || iface_mode == E_ENET_IF_GMII)
+ tmp |= DTSEC_ECNTRL_GMIIM;
+ if (is_sgmii)
+ tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM);
+ if (is_qsgmii)
+ tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM |
+ DTSEC_ECNTRL_QSGMIIM);
+ if (is_rgmii)
+ tmp |= DTSEC_ECNTRL_RPM;
+ if (iface_speed == E_ENET_SPEED_100)
+ tmp |= DTSEC_ECNTRL_R100M;
+
+ iowrite32be(tmp, ®s->ecntrl);
+ /*ECNTRL*/
+
+ /*TCTRL*/
+ tmp = 0;
+ if (cfg->halfdup_on)
+ tmp |= DTSEC_TCTRL_THDF;
+ if (cfg->tx_time_stamp_en)
+ tmp |= DTSEC_TCTRL_TTSE;
+
+ iowrite32be(tmp, ®s->tctrl);
+
+ /*TCTRL*/
+
+ /*PTV*/
+ tmp = 0;
+
+#ifdef FM_SHORT_PAUSE_TIME_ERRATA_DTSEC1
+ if ((fm_rev_maj == 1) && (fm_rev_min == 0))
+ cfg->tx_pause_time += 2;
+#endif /* FM_SHORT_PAUSE_TIME_ERRATA_DTSEC1 */
+
+ if (cfg->tx_pause_time)
+ tmp |= cfg->tx_pause_time;
+ if (cfg->tx_pause_time_extd)
+ tmp |= cfg->tx_pause_time_extd << PTV_PTE_OFST;
+ iowrite32be(tmp, ®s->ptv);
+
+ /*RCTRL*/
+ tmp = 0;
+ tmp |= ((uint32_t)(cfg->rx_prepend & 0x0000001f)) << 16;
+ if (cfg->rx_ctrl_acc)
+ tmp |= RCTRL_CFA;
+ if (cfg->rx_group_hash_exd)
+ tmp |= RCTRL_GHTX;
+ if (cfg->rx_time_stamp_en)
+ tmp |= RCTRL_RTSE;
+ if (cfg->rx_drop_bcast)
+ tmp |= RCTRL_BC_REJ;
+ if (cfg->rx_short_frm)
+ tmp |= RCTRL_RSF;
+ if (cfg->rx_promisc)
+ tmp |= RCTRL_PROM;
+
+ iowrite32be(tmp, ®s->rctrl);
+ /*RCTRL*/
+
+ /*Assign a Phy Address to the TBI (TBIPA).
+ *Done also in cases where TBI is not selected to avoid conflict with
+ *the external PHY's Physical address
+ */
+ iowrite32be(cfg->tbipa, ®s->tbipa);
+
+ /*TMR_CTL*/
+ iowrite32be(0, ®s->tmr_ctrl);
+
+ if (cfg->ptp_tsu_en) {
+ tmp = 0;
+ tmp |= TMR_PEVENT_TSRE;
+ iowrite32be(tmp, ®s->tmr_pevent);
+
+ if (cfg->ptp_exception_en) {
+ tmp = 0;
+ tmp |= TMR_PEMASK_TSREEN;
+ iowrite32be(tmp, ®s->tmr_pemask);
+ }
+ }
+
+ /*MACCFG1*/
+ tmp = 0;
+ if (cfg->loopback)
+ tmp |= MACCFG1_LOOPBACK;
+ if (cfg->rx_flow)
+ tmp |= MACCFG1_RX_FLOW;
+ if (cfg->tx_flow)
+ tmp |= MACCFG1_TX_FLOW;
+ iowrite32be(tmp, ®s->maccfg1);
+
+ /*MACCFG1*/
+
+ /*MACCFG2*/
+ tmp = 0;
+
+ if (iface_speed < E_ENET_SPEED_1000)
+ tmp |= MACCFG2_NIBBLE_MODE;
+ else if (iface_speed == E_ENET_SPEED_1000)
+ tmp |= MACCFG2_BYTE_MODE;
+
+ tmp |= ((uint32_t)cfg->preamble_len & 0x0000000f)
+ << PREAMBLE_LENGTH_SHIFT;
+
+ if (cfg->rx_preamble)
+ tmp |= MACCFG2_PRE_AM_RX_EN;
+ if (cfg->tx_preamble)
+ tmp |= MACCFG2_PRE_AM_TX_EN;
+ if (cfg->rx_len_check)
+ tmp |= MACCFG2_LENGTH_CHECK;
+ if (cfg->tx_pad_crc)
+ tmp |= MACCFG2_PAD_CRC_EN;
+ if (cfg->tx_crc)
+ tmp |= MACCFG2_CRC_EN;
+ if (!cfg->halfdup_on)
+ tmp |= MACCFG2_FULL_DUPLEX;
+ iowrite32be(tmp, ®s->maccfg2);
+
+ /*MACCFG2*/
+
+ /*IPGIFG*/
+ tmp = (((cfg->non_back_to_back_ipg1 <<
+ IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT)
+ & IPGIFG_NON_BACK_TO_BACK_IPG_1)
+ | ((cfg->non_back_to_back_ipg2 <<
+ IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT)
+ & IPGIFG_NON_BACK_TO_BACK_IPG_2)
+ | ((cfg->min_ifg_enforcement << IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT)
+ & IPGIFG_MIN_IFG_ENFORCEMENT)
+ | (cfg->back_to_back_ipg & IPGIFG_BACK_TO_BACK_IPG));
+ iowrite32be(tmp, ®s->ipgifg);
+
+ /*IPGIFG*/
+
+ /*HAFDUP*/
+ tmp = 0;
+
+ if (cfg->halfdup_alt_backoff_en)
+ tmp = (uint32_t)(HAFDUP_ALT_BEB |
+ ((cfg->halfdup_alt_backoff_val & 0x0000000f)
+ << HAFDUP_ALTERNATE_BEB_TRUNCATION_SHIFT));
+ if (cfg->halfdup_bp_no_backoff)
+ tmp |= HAFDUP_BP_NO_BACKOFF;
+ if (cfg->halfdup_no_backoff)
+ tmp |= HAFDUP_NO_BACKOFF;
+ if (cfg->halfdup_excess_defer)
+ tmp |= HAFDUP_EXCESS_DEFER;
+ tmp |= ((cfg->halfdup_retransmit << HAFDUP_RETRANSMISSION_MAX_SHIFT)
+ & HAFDUP_RETRANSMISSION_MAX);
+ tmp |= (cfg->halfdup_coll_window & HAFDUP_COLLISION_WINDOW);
+
+ iowrite32be(tmp, ®s->hafdup);
+ /*HAFDUP*/
+
+ /*MAXFRM*/
+ /* Initialize MAXFRM */
+ iowrite32be(cfg->maximum_frame, ®s->maxfrm);
+
+ /*MAXFRM*/
+
+ /*CAM1*/
+ iowrite32be(0xffffffff, ®s->cam1);
+ iowrite32be(0xffffffff, ®s->cam2);
+
+ /*IMASK*/
+ iowrite32be(exception_mask, ®s->imask);
+ /*IMASK*/
+
+ /*IEVENT*/
+ iowrite32be(0xffffffff, ®s->ievent);
+
+ /*MACSTNADDR1/2*/
+
+ tmp = (uint32_t)((macaddr[5] << 24) |
+ (macaddr[4] << 16) | (macaddr[3] << 8) | macaddr[2]);
+ iowrite32be(tmp, ®s->macstnaddr1);
+
+ tmp = (uint32_t)((macaddr[1] << 24) | (macaddr[0] << 16));
+ iowrite32be(tmp, ®s->macstnaddr2);
+
+ /*MACSTNADDR1/2*/
+
+ /*HASH*/
+ for (i = 0; i < NUM_OF_HASH_REGS; i++) {
+ /* Initialize IADDRx */
+ iowrite32be(0, ®s->igaddr[i]);
+ /* Initialize GADDRx */
+ iowrite32be(0, ®s->gaddr[i]);
+ }
+
+ fman_dtsec_reset_stat(regs);
+
+ return 0;
+}
+
+uint16_t fman_dtsec_get_max_frame_len(struct dtsec_regs __iomem *regs)
+{
+ return (uint16_t)ioread32be(®s->maxfrm);
+}
+
+void fman_dtsec_set_max_frame_len(struct dtsec_regs __iomem *regs,
+ uint16_t length)
+{
+ iowrite32be(length, ®s->maxfrm);
+}
+
+void fman_dtsec_set_mac_address(struct dtsec_regs __iomem *regs, uint8_t *adr)
+{
+ uint32_t tmp;
+
+ tmp = (uint32_t)((adr[5] << 24) |
+ (adr[4] << 16) | (adr[3] << 8) | adr[2]);
+ iowrite32be(tmp, ®s->macstnaddr1);
+
+ tmp = (uint32_t)((adr[1] << 24) | (adr[0] << 16));
+ iowrite32be(tmp, ®s->macstnaddr2);
+}
+
+void fman_dtsec_get_mac_address(struct dtsec_regs __iomem *regs,
+ uint8_t *macaddr)
+{
+ uint32_t tmp1, tmp2;
+
+ tmp1 = ioread32be(®s->macstnaddr1);
+ tmp2 = ioread32be(®s->macstnaddr2);
+
+ macaddr[0] = (uint8_t)((tmp2 & 0x00ff0000) >> 16);
+ macaddr[1] = (uint8_t)((tmp2 & 0xff000000) >> 24);
+ macaddr[2] = (uint8_t)(tmp1 & 0x000000ff);
+ macaddr[3] = (uint8_t)((tmp1 & 0x0000ff00) >> 8);
+ macaddr[4] = (uint8_t)((tmp1 & 0x00ff0000) >> 16);
+ macaddr[5] = (uint8_t)((tmp1 & 0xff000000) >> 24);
+}
+
+void fman_dtsec_set_hash_table(struct dtsec_regs __iomem *regs, uint32_t crc,
+ bool mcast, bool ghtx)
+{
+ int32_t bucket;
+
+ if (ghtx) {
+ bucket = (int32_t)((crc >> 23) & 0x1ff);
+ } else {
+ bucket = (int32_t)((crc >> 24) & 0xff);
+ /* if !ghtx and mcast the bit must be set in gaddr
+ * instead of igaddr.
+ */
+ if (mcast)
+ bucket += 0x100;
+ }
+ fman_dtsec_set_bucket(regs, bucket, true);
+}
+
+void fman_dtsec_set_bucket(struct dtsec_regs __iomem *regs, int bucket,
+ bool enable)
+{
+ int reg_idx = (bucket >> 5) & 0xf;
+ int bit_idx = bucket & 0x1f;
+ uint32_t bit_mask = 0x80000000 >> bit_idx;
+ uint32_t __iomem *reg;
+
+ if (reg_idx > 7)
+ reg = ®s->gaddr[reg_idx - 8];
+ else
+ reg = ®s->igaddr[reg_idx];
+
+ if (enable)
+ iowrite32be(ioread32be(reg) | bit_mask, reg);
+ else
+ iowrite32be(ioread32be(reg) & (~bit_mask), reg);
+}
+
+void fman_dtsec_reset_filter_table(struct dtsec_regs __iomem *regs, bool mcast,
+ bool ucast)
+{
+ int i;
+ bool ghtx;
+
+ ghtx = (bool)((ioread32be(®s->rctrl) & RCTRL_GHTX) ? true : false);
+
+ if (ucast || (ghtx && mcast)) {
+ for (i = 0; i < NUM_OF_HASH_REGS; i++)
+ iowrite32be(0, ®s->igaddr[i]);
+ }
+ if (mcast) {
+ for (i = 0; i < NUM_OF_HASH_REGS; i++)
+ iowrite32be(0, ®s->gaddr[i]);
+ }
+}
+
+int fman_dtsec_set_tbi_phy_addr(struct dtsec_regs __iomem *regs, uint8_t addr)
+{
+ if (addr > 0 && addr < 32)
+ iowrite32be(addr, ®s->tbipa);
+ else
+ return -EINVAL;
+
+ return 0;
+}
+
+void fman_dtsec_set_wol(struct dtsec_regs __iomem *regs, bool en)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->maccfg2);
+ if (en)
+ tmp |= MACCFG2_MAGIC_PACKET_EN;
+ else
+ tmp &= ~MACCFG2_MAGIC_PACKET_EN;
+ iowrite32be(tmp, ®s->maccfg2);
+}
+
+int fman_dtsec_adjust_link(struct dtsec_regs __iomem *regs,
+ enum enet_interface iface_mode,
+ enum enet_speed speed, bool full_dx)
+{
+ uint32_t tmp;
+
+ UNUSED(iface_mode);
+
+ if ((speed == E_ENET_SPEED_1000) && !full_dx)
+ return -EINVAL;
+
+ tmp = ioread32be(®s->maccfg2);
+ if (!full_dx)
+ tmp &= ~MACCFG2_FULL_DUPLEX;
+ else
+ tmp |= MACCFG2_FULL_DUPLEX;
+
+ tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE);
+ if (speed < E_ENET_SPEED_1000)
+ tmp |= MACCFG2_NIBBLE_MODE;
+ else if (speed == E_ENET_SPEED_1000)
+ tmp |= MACCFG2_BYTE_MODE;
+ iowrite32be(tmp, ®s->maccfg2);
+
+ tmp = ioread32be(®s->ecntrl);
+ if (speed == E_ENET_SPEED_100)
+ tmp |= DTSEC_ECNTRL_R100M;
+ else
+ tmp &= ~DTSEC_ECNTRL_R100M;
+ iowrite32be(tmp, ®s->ecntrl);
+
+ return 0;
+}
+
+void fman_dtsec_set_uc_promisc(struct dtsec_regs __iomem *regs, bool enable)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->rctrl);
+
+ if (enable)
+ tmp |= RCTRL_UPROM;
+ else
+ tmp &= ~RCTRL_UPROM;
+
+ iowrite32be(tmp, ®s->rctrl);
+}
+
+void fman_dtsec_set_mc_promisc(struct dtsec_regs __iomem *regs, bool enable)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->rctrl);
+
+ if (enable)
+ tmp |= RCTRL_MPROM;
+ else
+ tmp &= ~RCTRL_MPROM;
+
+ iowrite32be(tmp, ®s->rctrl);
+}
+
+bool fman_dtsec_get_clear_carry_regs(struct dtsec_regs __iomem *regs,
+ uint32_t *car1, uint32_t *car2)
+{
+ /* read carry registers */
+ *car1 = ioread32be(®s->car1);
+ *car2 = ioread32be(®s->car2);
+ /* clear carry registers */
+ if (*car1)
+ iowrite32be(*car1, ®s->car1);
+ if (*car2)
+ iowrite32be(*car2, ®s->car2);
+
+ return (bool)((*car1 | *car2) ? true : false);
+}
+
+void fman_dtsec_reset_stat(struct dtsec_regs __iomem *regs)
+{
+ /* clear HW counters */
+ iowrite32be(ioread32be(®s->ecntrl) |
+ DTSEC_ECNTRL_CLRCNT, ®s->ecntrl);
+}
+
+int fman_dtsec_set_stat_level(struct dtsec_regs __iomem *regs,
+ enum dtsec_stat_level level)
+{
+ switch (level) {
+ case E_MAC_STAT_NONE:
+ iowrite32be(0xffffffff, ®s->cam1);
+ iowrite32be(0xffffffff, ®s->cam2);
+ iowrite32be(ioread32be(®s->ecntrl) & ~DTSEC_ECNTRL_STEN,
+ ®s->ecntrl);
+ iowrite32be(ioread32be(®s->imask) & ~DTSEC_IMASK_MSROEN,
+ ®s->imask);
+ break;
+ case E_MAC_STAT_PARTIAL:
+ iowrite32be(CAM1_ERRORS_ONLY, ®s->cam1);
+ iowrite32be(CAM2_ERRORS_ONLY, ®s->cam2);
+ iowrite32be(ioread32be(®s->ecntrl) | DTSEC_ECNTRL_STEN,
+ ®s->ecntrl);
+ iowrite32be(ioread32be(®s->imask) | DTSEC_IMASK_MSROEN,
+ ®s->imask);
+ break;
+ case E_MAC_STAT_MIB_GRP1:
+ iowrite32be((uint32_t)~CAM1_MIB_GRP_1, ®s->cam1);
+ iowrite32be((uint32_t)~CAM2_MIB_GRP_1, ®s->cam2);
+ iowrite32be(ioread32be(®s->ecntrl) | DTSEC_ECNTRL_STEN,
+ ®s->ecntrl);
+ iowrite32be(ioread32be(®s->imask) | DTSEC_IMASK_MSROEN,
+ ®s->imask);
+ break;
+ case E_MAC_STAT_FULL:
+ iowrite32be(0, ®s->cam1);
+ iowrite32be(0, ®s->cam2);
+ iowrite32be(ioread32be(®s->ecntrl) | DTSEC_ECNTRL_STEN,
+ ®s->ecntrl);
+ iowrite32be(ioread32be(®s->imask) | DTSEC_IMASK_MSROEN,
+ ®s->imask);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+void fman_dtsec_set_ts(struct dtsec_regs __iomem *regs, bool en)
+{
+ if (en) {
+ iowrite32be(ioread32be(®s->rctrl) | RCTRL_RTSE,
+ ®s->rctrl);
+ iowrite32be(ioread32be(®s->tctrl) | DTSEC_TCTRL_TTSE,
+ ®s->tctrl);
+ } else {
+ iowrite32be(ioread32be(®s->rctrl) & ~RCTRL_RTSE,
+ ®s->rctrl);
+ iowrite32be(ioread32be(®s->tctrl) & ~DTSEC_TCTRL_TTSE,
+ ®s->tctrl);
+ }
+}
+
+void fman_dtsec_enable(struct dtsec_regs __iomem *regs, bool apply_rx,
+ bool apply_tx)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->maccfg1);
+
+ if (apply_rx)
+ tmp |= MACCFG1_RX_EN;
+
+ if (apply_tx)
+ tmp |= MACCFG1_TX_EN;
+
+ iowrite32be(tmp, ®s->maccfg1);
+}
+
+void fman_dtsec_clear_addr_in_paddr(struct dtsec_regs __iomem *regs,
+ uint8_t paddr_num)
+{
+ iowrite32be(0, ®s->macaddr[paddr_num].exact_match1);
+ iowrite32be(0, ®s->macaddr[paddr_num].exact_match2);
+}
+
+void fman_dtsec_add_addr_in_paddr(struct dtsec_regs __iomem *regs,
+ uint64_t addr, uint8_t paddr_num)
+{
+ uint32_t tmp;
+
+ tmp = (uint32_t)(addr);
+ /* swap */
+ tmp = (((tmp & 0x000000FF) << 24) |
+ ((tmp & 0x0000FF00) << 8) |
+ ((tmp & 0x00FF0000) >> 8) | ((tmp & 0xFF000000) >> 24));
+ iowrite32be(tmp, ®s->macaddr[paddr_num].exact_match1);
+
+ tmp = (uint32_t)(addr >> 32);
+ /* swap */
+ tmp = (((tmp & 0x000000FF) << 24) |
+ ((tmp & 0x0000FF00) << 8) |
+ ((tmp & 0x00FF0000) >> 8) | ((tmp & 0xFF000000) >> 24));
+ iowrite32be(tmp, ®s->macaddr[paddr_num].exact_match2);
+}
+
+void fman_dtsec_disable(struct dtsec_regs __iomem *regs, bool apply_rx,
+ bool apply_tx)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->maccfg1);
+
+ if (apply_rx)
+ tmp &= ~MACCFG1_RX_EN;
+
+ if (apply_tx)
+ tmp &= ~MACCFG1_TX_EN;
+
+ iowrite32be(tmp, ®s->maccfg1);
+}
+
+void fman_dtsec_set_tx_pause_frames(struct dtsec_regs __iomem *regs,
+ uint16_t time)
+{
+ uint32_t ptv = 0;
+
+ /* fixme: don't enable tx pause for half-duplex */
+
+ if (time) {
+ ptv = ioread32be(®s->ptv);
+ ptv &= 0xffff0000;
+ ptv |= time & 0x0000ffff;
+ iowrite32be(ptv, ®s->ptv);
+
+ /* trigger the transmission of a flow-control pause frame */
+ iowrite32be(ioread32be(®s->maccfg1) | MACCFG1_TX_FLOW,
+ ®s->maccfg1);
+ } else
+ iowrite32be(ioread32be(®s->maccfg1) & ~MACCFG1_TX_FLOW,
+ ®s->maccfg1);
+}
+
+void fman_dtsec_handle_rx_pause(struct dtsec_regs __iomem *regs, bool en)
+{
+ uint32_t tmp;
+
+ /* todo: check if mac is set to full-duplex */
+
+ tmp = ioread32be(®s->maccfg1);
+ if (en)
+ tmp |= MACCFG1_RX_FLOW;
+ else
+ tmp &= ~MACCFG1_RX_FLOW;
+ iowrite32be(tmp, ®s->maccfg1);
+}
+
+uint32_t fman_dtsec_get_rctrl(struct dtsec_regs __iomem *regs)
+{
+ return ioread32be(®s->rctrl);
+}
+
+uint32_t fman_dtsec_get_revision(struct dtsec_regs __iomem *regs)
+{
+ return ioread32be(®s->tsec_id);
+}
+
+uint32_t fman_dtsec_get_event(struct dtsec_regs __iomem *regs,
+ uint32_t ev_mask)
+{
+ return ioread32be(®s->ievent) & ev_mask;
+}
+
+void fman_dtsec_ack_event(struct dtsec_regs __iomem *regs, uint32_t ev_mask)
+{
+ iowrite32be(ev_mask, ®s->ievent);
+}
+
+uint32_t fman_dtsec_get_interrupt_mask(struct dtsec_regs __iomem *regs)
+{
+ return ioread32be(®s->imask);
+}
+
+uint32_t fman_dtsec_check_and_clear_tmr_event(struct dtsec_regs __iomem *regs)
+{
+ uint32_t event;
+
+ event = ioread32be(®s->tmr_pevent);
+ event &= ioread32be(®s->tmr_pemask);
+
+ if (event)
+ iowrite32be(event, ®s->tmr_pevent);
+ return event;
+}
+
+void fman_dtsec_enable_tmr_interrupt(struct dtsec_regs __iomem *regs)
+{
+ iowrite32be(ioread32be(®s->tmr_pemask) | TMR_PEMASK_TSREEN,
+ ®s->tmr_pemask);
+}
+
+void fman_dtsec_disable_tmr_interrupt(struct dtsec_regs __iomem *regs)
+{
+ iowrite32be(ioread32be(®s->tmr_pemask) & ~TMR_PEMASK_TSREEN,
+ ®s->tmr_pemask);
+}
+
+void fman_dtsec_enable_interrupt(struct dtsec_regs __iomem *regs,
+ uint32_t ev_mask)
+{
+ iowrite32be(ioread32be(®s->imask) | ev_mask, ®s->imask);
+}
+
+void fman_dtsec_disable_interrupt(struct dtsec_regs __iomem *regs,
+ uint32_t ev_mask)
+{
+ iowrite32be(ioread32be(®s->imask) & ~ev_mask, ®s->imask);
+}
+
+uint32_t fman_dtsec_get_stat_counter(struct dtsec_regs __iomem *regs,
+ enum dtsec_stat_counters reg_name)
+{
+ uint32_t ret_val;
+
+ switch (reg_name) {
+ case E_DTSEC_STAT_TR64:
+ ret_val = ioread32be(®s->tr64);
+ break;
+ case E_DTSEC_STAT_TR127:
+ ret_val = ioread32be(®s->tr127);
+ break;
+ case E_DTSEC_STAT_TR255:
+ ret_val = ioread32be(®s->tr255);
+ break;
+ case E_DTSEC_STAT_TR511:
+ ret_val = ioread32be(®s->tr511);
+ break;
+ case E_DTSEC_STAT_TR1K:
+ ret_val = ioread32be(®s->tr1k);
+ break;
+ case E_DTSEC_STAT_TRMAX:
+ ret_val = ioread32be(®s->trmax);
+ break;
+ case E_DTSEC_STAT_TRMGV:
+ ret_val = ioread32be(®s->trmgv);
+ break;
+ case E_DTSEC_STAT_RBYT:
+ ret_val = ioread32be(®s->rbyt);
+ break;
+ case E_DTSEC_STAT_RPKT:
+ ret_val = ioread32be(®s->rpkt);
+ break;
+ case E_DTSEC_STAT_RMCA:
+ ret_val = ioread32be(®s->rmca);
+ break;
+ case E_DTSEC_STAT_RBCA:
+ ret_val = ioread32be(®s->rbca);
+ break;
+ case E_DTSEC_STAT_RXPF:
+ ret_val = ioread32be(®s->rxpf);
+ break;
+ case E_DTSEC_STAT_RALN:
+ ret_val = ioread32be(®s->raln);
+ break;
+ case E_DTSEC_STAT_RFLR:
+ ret_val = ioread32be(®s->rflr);
+ break;
+ case E_DTSEC_STAT_RCDE:
+ ret_val = ioread32be(®s->rcde);
+ break;
+ case E_DTSEC_STAT_RCSE:
+ ret_val = ioread32be(®s->rcse);
+ break;
+ case E_DTSEC_STAT_RUND:
+ ret_val = ioread32be(®s->rund);
+ break;
+ case E_DTSEC_STAT_ROVR:
+ ret_val = ioread32be(®s->rovr);
+ break;
+ case E_DTSEC_STAT_RFRG:
+ ret_val = ioread32be(®s->rfrg);
+ break;
+ case E_DTSEC_STAT_RJBR:
+ ret_val = ioread32be(®s->rjbr);
+ break;
+ case E_DTSEC_STAT_RDRP:
+ ret_val = ioread32be(®s->rdrp);
+ break;
+ case E_DTSEC_STAT_TFCS:
+ ret_val = ioread32be(®s->tfcs);
+ break;
+ case E_DTSEC_STAT_TBYT:
+ ret_val = ioread32be(®s->tbyt);
+ break;
+ case E_DTSEC_STAT_TPKT:
+ ret_val = ioread32be(®s->tpkt);
+ break;
+ case E_DTSEC_STAT_TMCA:
+ ret_val = ioread32be(®s->tmca);
+ break;
+ case E_DTSEC_STAT_TBCA:
+ ret_val = ioread32be(®s->tbca);
+ break;
+ case E_DTSEC_STAT_TXPF:
+ ret_val = ioread32be(®s->txpf);
+ break;
+ case E_DTSEC_STAT_TNCL:
+ ret_val = ioread32be(®s->tncl);
+ break;
+ case E_DTSEC_STAT_TDRP:
+ ret_val = ioread32be(®s->tdrp);
+ break;
+ default:
+ ret_val = 0;
+ }
+
+ return ret_val;
+}
diff --git a/drivers/soc/fsl/fman/mac/fman_dtsec_mii_acc.c b/drivers/soc/fsl/fman/mac/fman_dtsec_mii_acc.c
new file mode 100644
index 0000000..81092e2
--- /dev/null
+++ b/drivers/soc/fsl/fman/mac/fman_dtsec_mii_acc.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "common/general.h"
+#include "fsl_fman_dtsec_mii_acc.h"
+
+/*dtsec_mii_get_div() - calculates the value of the dtsec mii divider
+ *@dtsec_freq: dtsec clock frequency (in Mhz)
+ *This function calculates the dtsec mii clock divider that determines
+ *the MII MDC clock. MII MDC clock will be set to work in the range
+ *of 1.5 to 2.5Mhz
+ *The output of this function is the value of MIIMCFG[MgmtClk] which
+ *implicitly determines the divider value.
+ *Note: the dTSEC system clock is equal to 1/2 of the FMan clock.
+ *The table below which reflects dtsec_mii_get_div() functionality
+ *shows the relations among dtsec_freq, MgmtClk, actual divider
+ *and the MII frequency:
+ *dtsec freq MgmtClk div MII freq Mhz
+ *[0.....80] 1 (1/4)(1/8) [0 to 2.5]
+ *[81...120] 2 (1/6)(1/8) [1.6 to 2.5]
+ *[121..160] 3 (1/8)(1/8) [1.8 to 2.5]
+ *[161..200] 4 (1/10)(1/8) [2.0 to 2.5]
+ *[201..280] 5 (1/14)(1/8) [1.8 to 2.5]
+ *[281..400] 6 (1/20)(1/8) [1.1 to 2.5]
+ *[401..560] 7 (1/28)(1/8) [1.8 to 2.5]
+ *[560..frq] 7 (1/28)(1/8) [frq/224]
+ *Returns: the MIIMCFG[MgmtClk] appropriate value
+ */
+
+static uint8_t dtsec_mii_get_div(uint16_t dtsec_freq)
+{
+ uint16_t mgmt_clk;
+
+ if (dtsec_freq < 80)
+ mgmt_clk = 1;
+ else if (dtsec_freq < 120)
+ mgmt_clk = 2;
+ else if (dtsec_freq < 160)
+ mgmt_clk = 3;
+ else if (dtsec_freq < 200)
+ mgmt_clk = 4;
+ else if (dtsec_freq < 280)
+ mgmt_clk = 5;
+ else if (dtsec_freq < 400)
+ mgmt_clk = 6;
+ else
+ mgmt_clk = 7;
+
+ return (uint8_t)mgmt_clk;
+}
+
+void fman_dtsec_mii_reset(struct dtsec_mii_reg __iomem *regs)
+{
+ /* Reset the management interface */
+ iowrite32be(ioread32be(®s->miimcfg) | MIIMCFG_RESET_MGMT,
+ ®s->miimcfg);
+ iowrite32be(ioread32be(®s->miimcfg) & ~MIIMCFG_RESET_MGMT,
+ ®s->miimcfg);
+}
+
+int fman_dtsec_mii_write_reg(struct dtsec_mii_reg __iomem *regs, uint8_t addr,
+ uint8_t reg, uint16_t data, uint16_t dtsec_freq)
+{
+ uint32_t tmp;
+
+ /* Setup the MII Mgmt clock speed */
+ iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), ®s->miimcfg);
+ /* Memory barrier */
+ wmb();
+
+ /* Stop the MII management read cycle */
+ iowrite32be(0, ®s->miimcom);
+ /* Dummy read to make sure MIIMCOM is written */
+ tmp = ioread32be(®s->miimcom);
+ /* Memory barrier */
+ wmb();
+
+ /* Setting up MII Management Address Register */
+ tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg);
+ iowrite32be(tmp, ®s->miimadd);
+ /* Memory barrier */
+ wmb();
+
+ /* Setting up MII Management Control Register with data */
+ iowrite32be((uint32_t)data, ®s->miimcon);
+ /* Dummy read to make sure MIIMCON is written */
+ tmp = ioread32be(®s->miimcon);
+ /* Memory barrier */
+ wmb();
+
+ /* Wait until MII management write is complete */
+ /* todo: a timeout could be useful here */
+ while ((ioread32be(®s->miimind)) & MIIMIND_BUSY)
+ ; /* busy wait */
+
+ return 0;
+}
+
+int fman_dtsec_mii_read_reg(struct dtsec_mii_reg __iomem *regs, uint8_t addr,
+ uint8_t reg, uint16_t *data, uint16_t dtsec_freq)
+{
+ uint32_t tmp;
+
+ /* Setup the MII Mgmt clock speed */
+ iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), ®s->miimcfg);
+ /* Memory barrier */
+ wmb();
+
+ /* Setting up the MII Management Address Register */
+ tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg);
+ iowrite32be(tmp, ®s->miimadd);
+ /* Memory barrier */
+ wmb();
+
+ /* Perform an MII management read cycle */
+ iowrite32be(MIIMCOM_READ_CYCLE, ®s->miimcom);
+ /* Dummy read to make sure MIIMCOM is written */
+ tmp = ioread32be(®s->miimcom);
+ /* Memory barrier */
+ wmb();
+
+ /* Wait until MII management read is complete */
+ /* todo: a timeout could be useful here */
+ while ((ioread32be(®s->miimind)) & MIIMIND_BUSY)
+ ; /* busy wait */
+
+ /* Read MII management status */
+ *data = (uint16_t)ioread32be(®s->miimstat);
+ /* Memory barrier */
+ wmb();
+
+ iowrite32be(0, ®s->miimcom);
+ /* Dummy read to make sure MIIMCOM is written */
+ tmp = ioread32be(®s->miimcom);
+
+ if (*data == 0xffff)
+ return -ENXIO;
+
+ return 0;
+}
diff --git a/drivers/soc/fsl/fman/mac/fman_memac.c b/drivers/soc/fsl/fman/mac/fman_memac.c
new file mode 100644
index 0000000..0fa453b
--- /dev/null
+++ b/drivers/soc/fsl/fman/mac/fman_memac.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fman_memac.h"
+
+uint32_t fman_memac_get_event(struct memac_regs __iomem *regs, uint32_t ev_mask)
+{
+ return ioread32be(®s->ievent) & ev_mask;
+}
+
+uint32_t fman_memac_get_interrupt_mask(struct memac_regs __iomem *regs)
+{
+ return ioread32be(®s->imask);
+}
+
+void fman_memac_ack_event(struct memac_regs __iomem *regs, uint32_t ev_mask)
+{
+ iowrite32be(ev_mask, ®s->ievent);
+}
+
+void fman_memac_set_promiscuous(struct memac_regs __iomem *regs, bool val)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->command_config);
+
+ if (val)
+ tmp |= CMD_CFG_PROMIS_EN;
+ else
+ tmp &= ~CMD_CFG_PROMIS_EN;
+
+ iowrite32be(tmp, ®s->command_config);
+}
+
+void fman_memac_clear_addr_in_paddr(struct memac_regs __iomem *regs,
+ uint8_t paddr_num)
+{
+ if (paddr_num == 0) {
+ iowrite32be(0, ®s->mac_addr0.mac_addr_l);
+ iowrite32be(0, ®s->mac_addr0.mac_addr_u);
+ } else {
+ iowrite32be(0x0, ®s->mac_addr[paddr_num - 1].mac_addr_l);
+ iowrite32be(0x0, ®s->mac_addr[paddr_num - 1].mac_addr_u);
+ }
+}
+
+void fman_memac_add_addr_in_paddr(struct memac_regs __iomem *regs,
+ uint8_t *adr, uint8_t paddr_num)
+{
+ uint32_t tmp0, tmp1;
+
+ tmp0 = (uint32_t)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
+ tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
+
+ if (paddr_num == 0) {
+ iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l);
+ iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u);
+ } else {
+ iowrite32be(tmp0, ®s->mac_addr[paddr_num - 1].mac_addr_l);
+ iowrite32be(tmp1, ®s->mac_addr[paddr_num - 1].mac_addr_u);
+ }
+}
+
+void fman_memac_enable(struct memac_regs __iomem *regs, bool apply_rx,
+ bool apply_tx)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->command_config);
+
+ if (apply_rx)
+ tmp |= CMD_CFG_RX_EN;
+
+ if (apply_tx)
+ tmp |= CMD_CFG_TX_EN;
+
+ iowrite32be(tmp, ®s->command_config);
+}
+
+void fman_memac_disable(struct memac_regs __iomem *regs, bool apply_rx,
+ bool apply_tx)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->command_config);
+
+ if (apply_rx)
+ tmp &= ~CMD_CFG_RX_EN;
+
+ if (apply_tx)
+ tmp &= ~CMD_CFG_TX_EN;
+
+ iowrite32be(tmp, ®s->command_config);
+}
+
+void fman_memac_reset_stat(struct memac_regs __iomem *regs)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->statn_config);
+
+ tmp |= STATS_CFG_CLR;
+
+ iowrite32be(tmp, ®s->statn_config);
+
+ while (ioread32be(®s->statn_config) & STATS_CFG_CLR)
+ ;
+}
+
+void fman_memac_reset(struct memac_regs __iomem *regs)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->command_config);
+
+ tmp |= CMD_CFG_SW_RESET;
+
+ iowrite32be(tmp, ®s->command_config);
+
+ while (ioread32be(®s->command_config) & CMD_CFG_SW_RESET)
+ ;
+}
+
+int fman_memac_init(struct memac_regs __iomem *regs,
+ struct memac_cfg *cfg,
+ enum enet_interface enet_interface,
+ enum enet_speed enet_speed, uint32_t exceptions)
+{
+ uint32_t tmp;
+
+ /* Config */
+ tmp = 0;
+ if (cfg->wan_mode_enable)
+ tmp |= CMD_CFG_WAN_MODE;
+ if (cfg->promiscuous_mode_enable)
+ tmp |= CMD_CFG_PROMIS_EN;
+ if (cfg->pause_forward_enable)
+ tmp |= CMD_CFG_PAUSE_FWD;
+ if (cfg->pause_ignore)
+ tmp |= CMD_CFG_PAUSE_IGNORE;
+ if (cfg->tx_addr_ins_enable)
+ tmp |= CMD_CFG_TX_ADDR_INS;
+ if (cfg->loopback_enable)
+ tmp |= CMD_CFG_LOOPBACK_EN;
+ if (cfg->cmd_frame_enable)
+ tmp |= CMD_CFG_CNT_FRM_EN;
+ if (cfg->send_idle_enable)
+ tmp |= CMD_CFG_SEND_IDLE;
+ if (cfg->no_length_check_enable)
+ tmp |= CMD_CFG_NO_LEN_CHK;
+ if (cfg->rx_sfd_any)
+ tmp |= CMD_CFG_SFD_ANY;
+ if (cfg->pad_enable)
+ tmp |= CMD_CFG_TX_PAD_EN;
+ if (cfg->wake_on_lan)
+ tmp |= CMD_CFG_MG;
+
+ tmp |= CMD_CFG_CRC_FWD;
+
+ iowrite32be(tmp, ®s->command_config);
+
+ /* Max Frame Length */
+ iowrite32be((uint32_t)cfg->max_frame_length, ®s->maxfrm);
+
+ /* Pause Time */
+ iowrite32be((uint32_t)cfg->pause_quanta, ®s->pause_quanta[0]);
+ iowrite32be((uint32_t)0, ®s->pause_thresh[0]);
+
+ /* IF_MODE */
+ tmp = 0;
+ switch (enet_interface) {
+ case E_ENET_IF_XGMII:
+ case E_ENET_IF_XFI:
+ tmp |= IF_MODE_XGMII;
+ break;
+ default:
+ tmp |= IF_MODE_GMII;
+ if (enet_interface == E_ENET_IF_RGMII && !cfg->loopback_enable)
+ tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO;
+ }
+ iowrite32be(tmp, ®s->if_mode);
+
+ /* TX_FIFO_SECTIONS */
+ tmp = 0;
+ if (enet_interface == E_ENET_IF_XGMII ||
+ enet_interface == E_ENET_IF_XFI) {
+ tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G |
+ TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
+ } else {
+ tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G |
+ TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G);
+ }
+ iowrite32be(tmp, ®s->tx_fifo_sections);
+
+ /* clear all pending events and set-up interrupts */
+ fman_memac_ack_event(regs, 0xffffffff);
+ fman_memac_set_exception(regs, exceptions, true);
+
+ return 0;
+}
+
+void fman_memac_set_exception(struct memac_regs __iomem *regs, uint32_t val,
+ bool enable)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->imask);
+ if (enable)
+ tmp |= val;
+ else
+ tmp &= ~val;
+
+ iowrite32be(tmp, ®s->imask);
+}
+
+void fman_memac_reset_filter_table(struct memac_regs __iomem *regs)
+{
+ uint32_t i;
+
+ for (i = 0; i < 64; i++)
+ iowrite32be(i & ~HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl);
+}
+
+void fman_memac_set_hash_table_entry(struct memac_regs __iomem *regs,
+ uint32_t crc)
+{
+ iowrite32be(crc | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl);
+}
+
+void fman_memac_set_hash_table(struct memac_regs __iomem *regs, uint32_t val)
+{
+ iowrite32be(val, ®s->hashtable_ctrl);
+}
+
+uint16_t fman_memac_get_max_frame_len(struct memac_regs __iomem *regs)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->maxfrm);
+
+ return (uint16_t)tmp;
+}
+
+void fman_memac_set_tx_pause_frames(struct memac_regs __iomem *regs,
+ uint8_t priority,
+ uint16_t pause_time, uint16_t thresh_time)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->tx_fifo_sections);
+
+ if (priority == 0xff) {
+ GET_TX_EMPTY_DEFAULT_VALUE(tmp);
+ iowrite32be(tmp, ®s->tx_fifo_sections);
+
+ tmp = ioread32be(®s->command_config);
+ tmp &= ~CMD_CFG_PFC_MODE;
+ priority = 0;
+ } else {
+ GET_TX_EMPTY_PFC_VALUE(tmp);
+ iowrite32be(tmp, ®s->tx_fifo_sections);
+
+ tmp = ioread32be(®s->command_config);
+ tmp |= CMD_CFG_PFC_MODE;
+ }
+
+ iowrite32be(tmp, ®s->command_config);
+
+ tmp = ioread32be(®s->pause_quanta[priority / 2]);
+ if (priority % 2)
+ tmp &= 0x0000FFFF;
+ else
+ tmp &= 0xFFFF0000;
+ tmp |= ((uint32_t)pause_time << (16 * (priority % 2)));
+ iowrite32be(tmp, ®s->pause_quanta[priority / 2]);
+
+ tmp = ioread32be(®s->pause_thresh[priority / 2]);
+ if (priority % 2)
+ tmp &= 0x0000FFFF;
+ else
+ tmp &= 0xFFFF0000;
+ tmp |= ((uint32_t)thresh_time << (16 * (priority % 2)));
+ iowrite32be(tmp, ®s->pause_thresh[priority / 2]);
+}
+
+void fman_memac_set_rx_ignore_pause_frames(struct memac_regs __iomem *regs,
+ bool enable)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->command_config);
+ if (enable)
+ tmp |= CMD_CFG_PAUSE_IGNORE;
+ else
+ tmp &= ~CMD_CFG_PAUSE_IGNORE;
+
+ iowrite32be(tmp, ®s->command_config);
+}
+
+void fman_memac_set_wol(struct memac_regs __iomem *regs, bool enable)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->command_config);
+
+ if (enable)
+ tmp |= CMD_CFG_MG;
+ else
+ tmp &= ~CMD_CFG_MG;
+
+ iowrite32be(tmp, ®s->command_config);
+}
+
+#define GET_MEMAC_CNTR_64(bn) \
+ (ioread32be(®s->bn ## _l) | \
+ ((uint64_t)ioread32be(®s->bn ## _u) << 32))
+
+uint64_t fman_memac_get_counter(struct memac_regs __iomem *regs,
+ enum memac_counters reg_name)
+{
+ uint64_t ret_val;
+
+ switch (reg_name) {
+ case E_MEMAC_COUNTER_R64:
+ ret_val = GET_MEMAC_CNTR_64(r64);
+ break;
+ case E_MEMAC_COUNTER_R127:
+ ret_val = GET_MEMAC_CNTR_64(r127);
+ break;
+ case E_MEMAC_COUNTER_R255:
+ ret_val = GET_MEMAC_CNTR_64(r255);
+ break;
+ case E_MEMAC_COUNTER_R511:
+ ret_val = GET_MEMAC_CNTR_64(r511);
+ break;
+ case E_MEMAC_COUNTER_R1023:
+ ret_val = GET_MEMAC_CNTR_64(r1023);
+ break;
+ case E_MEMAC_COUNTER_R1518:
+ ret_val = GET_MEMAC_CNTR_64(r1518);
+ break;
+ case E_MEMAC_COUNTER_R1519X:
+ ret_val = GET_MEMAC_CNTR_64(r1519x);
+ break;
+ case E_MEMAC_COUNTER_RFRG:
+ ret_val = GET_MEMAC_CNTR_64(rfrg);
+ break;
+ case E_MEMAC_COUNTER_RJBR:
+ ret_val = GET_MEMAC_CNTR_64(rjbr);
+ break;
+ case E_MEMAC_COUNTER_RDRP:
+ ret_val = GET_MEMAC_CNTR_64(rdrp);
+ break;
+ case E_MEMAC_COUNTER_RALN:
+ ret_val = GET_MEMAC_CNTR_64(raln);
+ break;
+ case E_MEMAC_COUNTER_TUND:
+ ret_val = GET_MEMAC_CNTR_64(tund);
+ break;
+ case E_MEMAC_COUNTER_ROVR:
+ ret_val = GET_MEMAC_CNTR_64(rovr);
+ break;
+ case E_MEMAC_COUNTER_RXPF:
+ ret_val = GET_MEMAC_CNTR_64(rxpf);
+ break;
+ case E_MEMAC_COUNTER_TXPF:
+ ret_val = GET_MEMAC_CNTR_64(txpf);
+ break;
+ case E_MEMAC_COUNTER_ROCT:
+ ret_val = GET_MEMAC_CNTR_64(roct);
+ break;
+ case E_MEMAC_COUNTER_RMCA:
+ ret_val = GET_MEMAC_CNTR_64(rmca);
+ break;
+ case E_MEMAC_COUNTER_RBCA:
+ ret_val = GET_MEMAC_CNTR_64(rbca);
+ break;
+ case E_MEMAC_COUNTER_RPKT:
+ ret_val = GET_MEMAC_CNTR_64(rpkt);
+ break;
+ case E_MEMAC_COUNTER_RUCA:
+ ret_val = GET_MEMAC_CNTR_64(ruca);
+ break;
+ case E_MEMAC_COUNTER_RERR:
+ ret_val = GET_MEMAC_CNTR_64(rerr);
+ break;
+ case E_MEMAC_COUNTER_TOCT:
+ ret_val = GET_MEMAC_CNTR_64(toct);
+ break;
+ case E_MEMAC_COUNTER_TMCA:
+ ret_val = GET_MEMAC_CNTR_64(tmca);
+ break;
+ case E_MEMAC_COUNTER_TBCA:
+ ret_val = GET_MEMAC_CNTR_64(tbca);
+ break;
+ case E_MEMAC_COUNTER_TUCA:
+ ret_val = GET_MEMAC_CNTR_64(tuca);
+ break;
+ case E_MEMAC_COUNTER_TERR:
+ ret_val = GET_MEMAC_CNTR_64(terr);
+ break;
+ default:
+ ret_val = 0;
+ }
+
+ return ret_val;
+}
+
+void fman_memac_adjust_link(struct memac_regs __iomem *regs,
+ enum enet_interface iface_mode,
+ enum enet_speed speed, bool full_dx)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->if_mode);
+
+ if (full_dx)
+ tmp &= ~IF_MODE_HD;
+ else
+ tmp |= IF_MODE_HD;
+
+ if (iface_mode == E_ENET_IF_RGMII) {
+ /* Configure RGMII in manual mode */
+ tmp &= ~IF_MODE_RGMII_AUTO;
+ tmp &= ~IF_MODE_RGMII_SP_MASK;
+
+ if (full_dx)
+ tmp |= IF_MODE_RGMII_FD;
+ else
+ tmp &= ~IF_MODE_RGMII_FD;
+
+ switch (speed) {
+ case E_ENET_SPEED_1000:
+ tmp |= IF_MODE_RGMII_1000;
+ break;
+ case E_ENET_SPEED_100:
+ tmp |= IF_MODE_RGMII_100;
+ break;
+ case E_ENET_SPEED_10:
+ tmp |= IF_MODE_RGMII_10;
+ break;
+ default:
+ break;
+ }
+ }
+
+ iowrite32be(tmp, ®s->if_mode);
+}
+
+void fman_memac_defconfig(struct memac_cfg *cfg)
+{
+ cfg->reset_on_init = false;
+ cfg->wan_mode_enable = false;
+ cfg->promiscuous_mode_enable = false;
+ cfg->pause_forward_enable = false;
+ cfg->pause_ignore = false;
+ cfg->tx_addr_ins_enable = false;
+ cfg->loopback_enable = false;
+ cfg->cmd_frame_enable = false;
+ cfg->rx_error_discard = false;
+ cfg->send_idle_enable = false;
+ cfg->no_length_check_enable = true;
+ cfg->lgth_check_nostdr = false;
+ cfg->time_stamp_enable = false;
+ cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
+ cfg->max_frame_length = DEFAULT_FRAME_LENGTH;
+ cfg->pause_quanta = DEFAULT_PAUSE_QUANTA;
+ cfg->pad_enable = true;
+ cfg->phy_tx_ena_on = false;
+ cfg->rx_sfd_any = false;
+ cfg->rx_pbl_fwd = false;
+ cfg->tx_pbl_fwd = false;
+ cfg->debug_mode = false;
+ cfg->wake_on_lan = false;
+}
diff --git a/drivers/soc/fsl/fman/mac/fman_memac_mii_acc.c b/drivers/soc/fsl/fman/mac/fman_memac_mii_acc.c
new file mode 100644
index 0000000..53f9174
--- /dev/null
+++ b/drivers/soc/fsl/fman/mac/fman_memac_mii_acc.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fman_memac_mii_acc.h"
+
+static void write_phy_reg_10g(struct memac_mii_access_mem_map __iomem *mii_regs,
+ uint8_t phy_addr, uint8_t reg, uint16_t data)
+{
+ uint32_t tmp_reg;
+
+ tmp_reg = ioread32be(&mii_regs->mdio_cfg);
+ /* Leave only MDIO_CLK_DIV bits set on */
+ tmp_reg &= MDIO_CFG_CLK_DIV_MASK;
+ /* Set maximum MDIO_HOLD value to allow phy to see
+ * change of data signal
+ **/
+ tmp_reg |= MDIO_CFG_HOLD_MASK;
+ /* Add 10G interface mode */
+ tmp_reg |= MDIO_CFG_ENC45;
+ iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
+
+ /* Wait for command completion */
+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
+ udelay(1);
+
+ /* Specify phy and register to be accessed */
+ iowrite32be(phy_addr, &mii_regs->mdio_ctrl);
+ iowrite32be(reg, &mii_regs->mdio_addr);
+ /* memory barrier */
+ wmb();
+
+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
+ udelay(1);
+
+ /* Write data */
+ iowrite32be(data, &mii_regs->mdio_data);
+ /* memory barrier */
+ wmb();
+
+ /* Wait for write transaction end */
+ while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
+ udelay(1);
+}
+
+static uint32_t read_phy_reg_10g(struct memac_mii_access_mem_map __iomem
+ *mii_regs, uint8_t phy_addr, uint8_t reg,
+ uint16_t *data)
+{
+ uint32_t tmp_reg;
+
+ tmp_reg = ioread32be(&mii_regs->mdio_cfg);
+ /* Leave only MDIO_CLK_DIV bits set on */
+ tmp_reg &= MDIO_CFG_CLK_DIV_MASK;
+ /* Set maximum MDIO_HOLD value to allow phy to see
+ * change of data signal
+ **/
+ tmp_reg |= MDIO_CFG_HOLD_MASK;
+ /* Add 10G interface mode */
+ tmp_reg |= MDIO_CFG_ENC45;
+ iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
+
+ /* Wait for command completion */
+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
+ udelay(1);
+
+ /* Specify phy and register to be accessed */
+ iowrite32be(phy_addr, &mii_regs->mdio_ctrl);
+ iowrite32be(reg, &mii_regs->mdio_addr);
+ /* memory barrier */
+ wmb();
+
+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
+ udelay(1);
+
+ /* Read cycle */
+ tmp_reg = phy_addr;
+ tmp_reg |= MDIO_CTL_READ;
+ iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
+ /* memory barrier */
+ wmb();
+
+ /* Wait for data to be available */
+ while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
+ udelay(1);
+
+ *data = (uint16_t)ioread32be(&mii_regs->mdio_data);
+
+ /* Check if there was an error */
+ return ioread32be(&mii_regs->mdio_cfg);
+}
+
+static void write_phy_reg_1g(struct memac_mii_access_mem_map __iomem *mii_regs,
+ uint8_t phy_addr, uint8_t reg, uint16_t data)
+{
+ uint32_t tmp_reg;
+
+ /* Leave only MDIO_CLK_DIV and MDIO_HOLD bits set on */
+ tmp_reg = ioread32be(&mii_regs->mdio_cfg);
+ tmp_reg &= (MDIO_CFG_CLK_DIV_MASK | MDIO_CFG_HOLD_MASK);
+ iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
+
+ /* Wait for command completion */
+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
+ udelay(1);
+
+ /* Write transaction */
+ tmp_reg = (phy_addr << MDIO_CTL_PHY_ADDR_SHIFT);
+ tmp_reg |= reg;
+ iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
+
+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
+ udelay(1);
+
+ iowrite32be(data, &mii_regs->mdio_data);
+
+ /* memory barrier */
+ wmb();
+
+ /* Wait for write transaction to end */
+ while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
+ udelay(1);
+}
+
+static uint32_t read_phy_reg_1g(struct memac_mii_access_mem_map __iomem
+ *mii_regs, uint8_t phy_addr, uint8_t reg,
+ uint16_t *data)
+{
+ uint32_t tmp_reg;
+
+ /* Leave only MDIO_CLK_DIV and MDIO_HOLD bits set on */
+ tmp_reg = ioread32be(&mii_regs->mdio_cfg);
+ tmp_reg &= (MDIO_CFG_CLK_DIV_MASK | MDIO_CFG_HOLD_MASK);
+ iowrite32be(tmp_reg, &mii_regs->mdio_cfg);
+
+ /* Wait for command completion */
+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
+ udelay(1);
+
+ /* Read transaction */
+ tmp_reg = (phy_addr << MDIO_CTL_PHY_ADDR_SHIFT);
+ tmp_reg |= reg;
+ tmp_reg |= MDIO_CTL_READ;
+ iowrite32be(tmp_reg, &mii_regs->mdio_ctrl);
+
+ while ((ioread32be(&mii_regs->mdio_cfg)) & MDIO_CFG_BSY)
+ udelay(1);
+
+ /* Wait for data to be available */
+ while ((ioread32be(&mii_regs->mdio_data)) & MDIO_DATA_BSY)
+ udelay(1);
+
+ *data = (uint16_t)ioread32be(&mii_regs->mdio_data);
+
+ /* Check error */
+ return ioread32be(&mii_regs->mdio_cfg);
+}
+
+int fman_memac_mii_write_phy_reg(struct memac_mii_access_mem_map __iomem
+ *mii_regs, uint8_t phy_addr, uint8_t reg,
+ uint16_t data, enum enet_speed enet_speed)
+{
+ /* Figure out interface type - 10G vs 1G.
+ * In 10G interface both phy_addr and devAddr present.
+ **/
+ if (enet_speed == E_ENET_SPEED_10000)
+ write_phy_reg_10g(mii_regs, phy_addr, reg, data);
+ else
+ write_phy_reg_1g(mii_regs, phy_addr, reg, data);
+
+ return 0;
+}
+
+int fman_memac_mii_read_phy_reg(struct memac_mii_access_mem_map __iomem
+ *mii_regs, uint8_t phy_addr, uint8_t reg,
+ uint16_t *data, enum enet_speed enet_speed)
+{
+ uint32_t ans;
+ /* Figure out interface type - 10G vs 1G.
+ * In 10G interface both phy_addr and devAddr present.
+ **/
+ if (enet_speed == E_ENET_SPEED_10000)
+ ans = read_phy_reg_10g(mii_regs, phy_addr, reg, data);
+ else
+ ans = read_phy_reg_1g(mii_regs, phy_addr, reg, data);
+
+ if (ans & MDIO_CFG_READ_ERR)
+ return -EINVAL;
+ return 0;
+}
diff --git a/drivers/soc/fsl/fman/mac/fman_tgec.c b/drivers/soc/fsl/fman/mac/fman_tgec.c
new file mode 100644
index 0000000..e0f27cb
--- /dev/null
+++ b/drivers/soc/fsl/fman/mac/fman_tgec.c
@@ -0,0 +1,372 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fman_tgec.h"
+
+void fman_tgec_set_mac_address(struct tgec_regs __iomem *regs, uint8_t *adr)
+{
+ uint32_t tmp0, tmp1;
+
+ tmp0 = (uint32_t)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
+ tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
+ iowrite32be(tmp0, ®s->mac_addr_0);
+ iowrite32be(tmp1, ®s->mac_addr_1);
+}
+
+void fman_tgec_reset_stat(struct tgec_regs __iomem *regs)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->command_config);
+
+ tmp |= CMD_CFG_STAT_CLR;
+
+ iowrite32be(tmp, ®s->command_config);
+
+ while (ioread32be(®s->command_config) & CMD_CFG_STAT_CLR)
+ ;
+}
+
+#define GET_TGEC_CNTR_64(bn) \
+ (((uint64_t)ioread32be(®s->bn ## _u) << 32) | \
+ ioread32be(®s->bn ## _l))
+
+uint64_t fman_tgec_get_counter(struct tgec_regs __iomem *regs,
+ enum tgec_counters reg_name)
+{
+ uint64_t ret_val;
+
+ switch (reg_name) {
+ case E_TGEC_COUNTER_R64:
+ ret_val = GET_TGEC_CNTR_64(r64);
+ break;
+ case E_TGEC_COUNTER_R127:
+ ret_val = GET_TGEC_CNTR_64(r127);
+ break;
+ case E_TGEC_COUNTER_R255:
+ ret_val = GET_TGEC_CNTR_64(r255);
+ break;
+ case E_TGEC_COUNTER_R511:
+ ret_val = GET_TGEC_CNTR_64(r511);
+ break;
+ case E_TGEC_COUNTER_R1023:
+ ret_val = GET_TGEC_CNTR_64(r1023);
+ break;
+ case E_TGEC_COUNTER_R1518:
+ ret_val = GET_TGEC_CNTR_64(r1518);
+ break;
+ case E_TGEC_COUNTER_R1519X:
+ ret_val = GET_TGEC_CNTR_64(r1519x);
+ break;
+ case E_TGEC_COUNTER_TRFRG:
+ ret_val = GET_TGEC_CNTR_64(trfrg);
+ break;
+ case E_TGEC_COUNTER_TRJBR:
+ ret_val = GET_TGEC_CNTR_64(trjbr);
+ break;
+ case E_TGEC_COUNTER_RDRP:
+ ret_val = GET_TGEC_CNTR_64(rdrp);
+ break;
+ case E_TGEC_COUNTER_RALN:
+ ret_val = GET_TGEC_CNTR_64(raln);
+ break;
+ case E_TGEC_COUNTER_TRUND:
+ ret_val = GET_TGEC_CNTR_64(trund);
+ break;
+ case E_TGEC_COUNTER_TROVR:
+ ret_val = GET_TGEC_CNTR_64(trovr);
+ break;
+ case E_TGEC_COUNTER_RXPF:
+ ret_val = GET_TGEC_CNTR_64(rxpf);
+ break;
+ case E_TGEC_COUNTER_TXPF:
+ ret_val = GET_TGEC_CNTR_64(txpf);
+ break;
+ case E_TGEC_COUNTER_ROCT:
+ ret_val = GET_TGEC_CNTR_64(roct);
+ break;
+ case E_TGEC_COUNTER_RMCA:
+ ret_val = GET_TGEC_CNTR_64(rmca);
+ break;
+ case E_TGEC_COUNTER_RBCA:
+ ret_val = GET_TGEC_CNTR_64(rbca);
+ break;
+ case E_TGEC_COUNTER_RPKT:
+ ret_val = GET_TGEC_CNTR_64(rpkt);
+ break;
+ case E_TGEC_COUNTER_RUCA:
+ ret_val = GET_TGEC_CNTR_64(ruca);
+ break;
+ case E_TGEC_COUNTER_RERR:
+ ret_val = GET_TGEC_CNTR_64(rerr);
+ break;
+ case E_TGEC_COUNTER_TOCT:
+ ret_val = GET_TGEC_CNTR_64(toct);
+ break;
+ case E_TGEC_COUNTER_TMCA:
+ ret_val = GET_TGEC_CNTR_64(tmca);
+ break;
+ case E_TGEC_COUNTER_TBCA:
+ ret_val = GET_TGEC_CNTR_64(tbca);
+ break;
+ case E_TGEC_COUNTER_TUCA:
+ ret_val = GET_TGEC_CNTR_64(tuca);
+ break;
+ case E_TGEC_COUNTER_TERR:
+ ret_val = GET_TGEC_CNTR_64(terr);
+ break;
+ default:
+ ret_val = 0;
+ }
+
+ return ret_val;
+}
+
+void fman_tgec_enable(struct tgec_regs __iomem *regs, bool apply_rx,
+ bool apply_tx)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->command_config);
+ if (apply_rx)
+ tmp |= CMD_CFG_RX_EN;
+ if (apply_tx)
+ tmp |= CMD_CFG_TX_EN;
+ iowrite32be(tmp, ®s->command_config);
+}
+
+void fman_tgec_disable(struct tgec_regs __iomem *regs, bool apply_rx,
+ bool apply_tx)
+{
+ uint32_t tmp_reg_32;
+
+ tmp_reg_32 = ioread32be(®s->command_config);
+ if (apply_rx)
+ tmp_reg_32 &= ~CMD_CFG_RX_EN;
+ if (apply_tx)
+ tmp_reg_32 &= ~CMD_CFG_TX_EN;
+ iowrite32be(tmp_reg_32, ®s->command_config);
+}
+
+void fman_tgec_set_promiscuous(struct tgec_regs __iomem *regs, bool val)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->command_config);
+ if (val)
+ tmp |= CMD_CFG_PROMIS_EN;
+ else
+ tmp &= ~CMD_CFG_PROMIS_EN;
+ iowrite32be(tmp, ®s->command_config);
+}
+
+void fman_tgec_reset_filter_table(struct tgec_regs __iomem *regs)
+{
+ uint32_t i;
+
+ for (i = 0; i < 512; i++)
+ iowrite32be(i & ~TGEC_HASH_MCAST_EN, ®s->hashtable_ctrl);
+}
+
+void fman_tgec_set_hash_table_entry(struct tgec_regs __iomem *regs,
+ uint32_t crc)
+{
+ /* Take 9 MSB bits */
+ uint32_t hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK;
+
+ iowrite32be(hash | TGEC_HASH_MCAST_EN, ®s->hashtable_ctrl);
+}
+
+void fman_tgec_set_hash_table(struct tgec_regs __iomem *regs, uint32_t value)
+{
+ iowrite32be(value, ®s->hashtable_ctrl);
+}
+
+void fman_tgec_set_tx_pause_frames(struct tgec_regs __iomem *regs,
+ uint16_t pause_time)
+{
+ iowrite32be((uint32_t)pause_time, ®s->pause_quant);
+}
+
+void fman_tgec_set_rx_ignore_pause_frames(struct tgec_regs __iomem *regs,
+ bool en)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->command_config);
+ if (en)
+ tmp |= CMD_CFG_PAUSE_IGNORE;
+ else
+ tmp &= ~CMD_CFG_PAUSE_IGNORE;
+ iowrite32be(tmp, ®s->command_config);
+}
+
+void fman_tgec_enable_1588_time_stamp(struct tgec_regs __iomem *regs, bool en)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->command_config);
+ if (en)
+ tmp |= CMD_CFG_EN_TIMESTAMP;
+ else
+ tmp &= ~CMD_CFG_EN_TIMESTAMP;
+ iowrite32be(tmp, ®s->command_config);
+}
+
+uint32_t fman_tgec_get_event(struct tgec_regs __iomem *regs, uint32_t ev_mask)
+{
+ return ioread32be(®s->ievent) & ev_mask;
+}
+
+void fman_tgec_ack_event(struct tgec_regs __iomem *regs, uint32_t ev_mask)
+{
+ iowrite32be(ev_mask, ®s->ievent);
+}
+
+uint32_t fman_tgec_get_interrupt_mask(struct tgec_regs __iomem *regs)
+{
+ return ioread32be(®s->imask);
+}
+
+void fman_tgec_add_addr_in_paddr(struct tgec_regs __iomem *regs, uint8_t *adr)
+{
+ uint32_t tmp0, tmp1;
+
+ tmp0 = (uint32_t)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
+ tmp1 = (uint32_t)(adr[4] | adr[5] << 8);
+ iowrite32be(tmp0, ®s->mac_addr_2);
+ iowrite32be(tmp1, ®s->mac_addr_3);
+}
+
+void fman_tgec_clear_addr_in_paddr(struct tgec_regs __iomem *regs)
+{
+ iowrite32be(0, ®s->mac_addr_2);
+ iowrite32be(0, ®s->mac_addr_3);
+}
+
+uint32_t fman_tgec_get_revision(struct tgec_regs __iomem *regs)
+{
+ return ioread32be(®s->tgec_id);
+}
+
+void fman_tgec_enable_interrupt(struct tgec_regs __iomem *regs,
+ uint32_t ev_mask)
+{
+ iowrite32be(ioread32be(®s->imask) | ev_mask, ®s->imask);
+}
+
+void fman_tgec_disable_interrupt(struct tgec_regs __iomem *regs,
+ uint32_t ev_mask)
+{
+ iowrite32be(ioread32be(®s->imask) & ~ev_mask, ®s->imask);
+}
+
+uint16_t fman_tgec_get_max_frame_len(struct tgec_regs __iomem *regs)
+{
+ return (uint16_t)ioread32be(®s->maxfrm);
+}
+
+void fman_tgec_defconfig(struct tgec_cfg *cfg)
+{
+ cfg->wan_mode_enable = DEFAULT_WAN_MODE_ENABLE;
+ cfg->promiscuous_mode_enable = DEFAULT_PROMISCUOUS_MODE_ENABLE;
+ cfg->pause_forward_enable = DEFAULT_PAUSE_FORWARD_ENABLE;
+ cfg->pause_ignore = DEFAULT_PAUSE_IGNORE;
+ cfg->tx_addr_ins_enable = DEFAULT_TX_ADDR_INS_ENABLE;
+ cfg->loopback_enable = DEFAULT_LOOPBACK_ENABLE;
+ cfg->cmd_frame_enable = DEFAULT_CMD_FRAME_ENABLE;
+ cfg->rx_error_discard = DEFAULT_RX_ERROR_DISCARD;
+ cfg->send_idle_enable = DEFAULT_SEND_IDLE_ENABLE;
+ cfg->no_length_check_enable = DEFAULT_NO_LENGTH_CHECK_ENABLE;
+ cfg->lgth_check_nostdr = DEFAULT_LGTH_CHECK_NOSTDR;
+ cfg->time_stamp_enable = DEFAULT_TIME_STAMP_ENABLE;
+ cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
+ cfg->max_frame_length = DEFAULT_MAX_FRAME_LENGTH;
+ cfg->pause_quant = DEFAULT_PAUSE_QUANT;
+#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
+ cfg->skip_fman11_workaround = false;
+#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
+}
+
+int fman_tgec_init(struct tgec_regs __iomem *regs, struct tgec_cfg *cfg,
+ uint32_t exception_mask)
+{
+ uint32_t tmp;
+
+ /* Config */
+ tmp = 0x40; /* CRC forward */
+ if (cfg->wan_mode_enable)
+ tmp |= CMD_CFG_WAN_MODE;
+ if (cfg->promiscuous_mode_enable)
+ tmp |= CMD_CFG_PROMIS_EN;
+ if (cfg->pause_forward_enable)
+ tmp |= CMD_CFG_PAUSE_FWD;
+ if (cfg->pause_ignore)
+ tmp |= CMD_CFG_PAUSE_IGNORE;
+ if (cfg->tx_addr_ins_enable)
+ tmp |= CMD_CFG_TX_ADDR_INS;
+ if (cfg->loopback_enable)
+ tmp |= CMD_CFG_LOOPBACK_EN;
+ if (cfg->cmd_frame_enable)
+ tmp |= CMD_CFG_CMD_FRM_EN;
+ if (cfg->rx_error_discard)
+ tmp |= CMD_CFG_RX_ER_DISC;
+ if (cfg->send_idle_enable)
+ tmp |= CMD_CFG_SEND_IDLE;
+ if (cfg->no_length_check_enable)
+ tmp |= CMD_CFG_NO_LEN_CHK;
+ if (cfg->time_stamp_enable)
+ tmp |= CMD_CFG_EN_TIMESTAMP;
+ iowrite32be(tmp, ®s->command_config);
+
+ /* Max Frame Length */
+ iowrite32be((uint32_t)cfg->max_frame_length, ®s->maxfrm);
+ /* Pause Time */
+ iowrite32be(cfg->pause_quant, ®s->pause_quant);
+
+ /* clear all pending events and set-up interrupts */
+ fman_tgec_ack_event(regs, 0xffffffff);
+ fman_tgec_enable_interrupt(regs, exception_mask);
+
+ return 0;
+}
+
+void fman_tgec_set_erratum_tx_fifo_corruption_10gmac_a007(struct tgec_regs
+ __iomem *regs)
+{
+ uint32_t tmp;
+
+ /* restore the default tx ipg Length */
+ tmp = (ioread32be(®s->tx_ipg_len) & ~TGEC_TX_IPG_LENGTH_MASK) | 12;
+
+ iowrite32be(tmp, ®s->tx_ipg_len);
+}
--
2.3.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 5/7] soc/fman: Add the FMan parser and KeyGen FLIB(s)
2015-03-05 5:45 [PATCH 0/7] Freescale DPAA FMan FLIB(s) Emil Medve
` (3 preceding siblings ...)
2015-03-05 5:45 ` [PATCH 4/7] soc/fman: Add the FMan MAC FLIB Emil Medve
@ 2015-03-05 5:45 ` Emil Medve
2015-03-05 5:45 ` [PATCH 6/7] soc/fman: Add the FMan RTC FLIB Emil Medve
` (2 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Emil Medve @ 2015-03-05 5:45 UTC (permalink / raw)
To: linuxppc-dev, netdev, linux-kernel; +Cc: Igal Liberman
From: Igal Liberman <Igal.Liberman@freescale.com>
Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
---
drivers/soc/fsl/fman/Kconfig | 6 +
drivers/soc/fsl/fman/Makefile | 1 +
drivers/soc/fsl/fman/pcd/Makefile | 13 +
drivers/soc/fsl/fman/pcd/fman_kg.c | 850 ++++++++++++++++++++++++++++++++++++
drivers/soc/fsl/fman/pcd/fman_prs.c | 127 ++++++
5 files changed, 997 insertions(+)
create mode 100644 drivers/soc/fsl/fman/pcd/Makefile
create mode 100644 drivers/soc/fsl/fman/pcd/fman_kg.c
create mode 100644 drivers/soc/fsl/fman/pcd/fman_prs.c
diff --git a/drivers/soc/fsl/fman/Kconfig b/drivers/soc/fsl/fman/Kconfig
index c1c258c..2559ee9 100644
--- a/drivers/soc/fsl/fman/Kconfig
+++ b/drivers/soc/fsl/fman/Kconfig
@@ -20,4 +20,10 @@ config FSL_FMAN_MAC
help
Freescale DPAA FMan MAC support
+config FSL_FMAN_PCD
+ bool "FMan PCD"
+ default n
+ help
+ Freescale DPAA FMan Parse, Classify and Distribute support
+
endif # FSL_FMAN
diff --git a/drivers/soc/fsl/fman/Makefile b/drivers/soc/fsl/fman/Makefile
index ffaabd9..dc37f35 100644
--- a/drivers/soc/fsl/fman/Makefile
+++ b/drivers/soc/fsl/fman/Makefile
@@ -12,5 +12,6 @@ fsl_fman-objs := fman.o
obj-$(CONFIG_FSL_FMAN_PORT) += port/
obj-$(CONFIG_FSL_FMAN_MAC) += mac/
+obj-$(CONFIG_FSL_FMAN_PCD) += pcd/
endif
diff --git a/drivers/soc/fsl/fman/pcd/Makefile b/drivers/soc/fsl/fman/pcd/Makefile
new file mode 100644
index 0000000..fa40367
--- /dev/null
+++ b/drivers/soc/fsl/fman/pcd/Makefile
@@ -0,0 +1,13 @@
+ccflags-y += -DVERSION=\"\"
+
+ifeq ($(CONFIG_FSL_FMAN_PCD),y)
+
+FMAN = $(srctree)/drivers/soc/fsl/fman
+
+ccflags-y += -I$(FMAN)/flib
+
+obj-$(CONFIG_FSL_FMAN_PCD) += fsl_fman_pcd.o
+
+fsl_fman_pcd-objs := fman_kg.o fman_prs.o
+
+endif
diff --git a/drivers/soc/fsl/fman/pcd/fman_kg.c b/drivers/soc/fsl/fman/pcd/fman_kg.c
new file mode 100644
index 0000000..f420db6
--- /dev/null
+++ b/drivers/soc/fsl/fman/pcd/fman_kg.c
@@ -0,0 +1,850 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fman_kg.h"
+
+/* static functions */
+
+static uint32_t build_ar_bind_scheme(uint8_t hwport_id, bool write)
+{
+ uint32_t rw;
+
+ rw = write ? (uint32_t)FM_KG_KGAR_WRITE : (uint32_t)FM_KG_KGAR_READ;
+
+ return (uint32_t)(FM_KG_KGAR_GO | rw | FM_PCD_KG_KGAR_SEL_PORT_ENTRY |
+ hwport_id | FM_PCD_KG_KGAR_SEL_PORT_WSEL_SP);
+}
+
+static void clear_pe_all_scheme(struct fman_kg_regs __iomem *regs,
+ uint8_t hwport_id)
+{
+ uint32_t ar;
+
+ fman_kg_write_sp(regs, 0xffffffff, 0);
+
+ ar = build_ar_bind_scheme(hwport_id, true);
+ fman_kg_write_ar_wait(regs, ar);
+}
+
+static uint32_t build_ar_bind_cls_plan(uint8_t hwport_id, bool write)
+{
+ uint32_t rw;
+
+ rw = write ? (uint32_t)FM_KG_KGAR_WRITE : (uint32_t)FM_KG_KGAR_READ;
+
+ return (uint32_t)(FM_KG_KGAR_GO | rw | FM_PCD_KG_KGAR_SEL_PORT_ENTRY |
+ hwport_id | FM_PCD_KG_KGAR_SEL_PORT_WSEL_CPP);
+}
+
+static void clear_pe_all_cls_plan(struct fman_kg_regs __iomem *regs,
+ uint8_t hwport_id)
+{
+ uint32_t ar;
+
+ fman_kg_write_cpp(regs, 0);
+
+ ar = build_ar_bind_cls_plan(hwport_id, true);
+ fman_kg_write_ar_wait(regs, ar);
+}
+
+static uint8_t get_gen_ht_code(enum fman_kg_gen_extract_src src,
+ bool no_validation, uint8_t *offset)
+{
+ int code;
+
+ switch (src) {
+ case E_FMAN_KG_GEN_EXTRACT_ETH:
+ code = no_validation ? 0x73 : 0x3;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_ETYPE:
+ code = no_validation ? 0x77 : 0x7;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_SNAP:
+ code = no_validation ? 0x74 : 0x4;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_VLAN_TCI_1:
+ code = no_validation ? 0x75 : 0x5;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_VLAN_TCI_N:
+ code = no_validation ? 0x76 : 0x6;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_PPPOE:
+ code = no_validation ? 0x78 : 0x8;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_MPLS_1:
+ code = no_validation ? 0x79 : 0x9;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_MPLS_2:
+ code = no_validation ? FM_KG_SCH_GEN_HT_INVALID : 0x19;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_MPLS_3:
+ code = no_validation ? FM_KG_SCH_GEN_HT_INVALID : 0x29;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_MPLS_N:
+ code = no_validation ? 0x7a : 0xa;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_IPV4_1:
+ code = no_validation ? 0x7b : 0xb;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_IPV6_1:
+ code = no_validation ? 0x7b : 0x1b;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_IPV4_2:
+ code = no_validation ? 0x7c : 0xc;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_IPV6_2:
+ code = no_validation ? 0x7c : 0x1c;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_MINENCAP:
+ code = no_validation ? 0x7c : 0x2c;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_IP_PID:
+ code = no_validation ? 0x72 : 0x2;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_GRE:
+ code = no_validation ? 0x7d : 0xd;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_TCP:
+ code = no_validation ? 0x7e : 0xe;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_UDP:
+ code = no_validation ? 0x7e : 0x1e;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_SCTP:
+ code = no_validation ? 0x7e : 0x3e;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_DCCP:
+ code = no_validation ? 0x7e : 0x4e;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_IPSEC_AH:
+ code = no_validation ? 0x7e : 0x2e;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_IPSEC_ESP:
+ code = no_validation ? 0x7e : 0x6e;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_SHIM_1:
+ code = 0x70;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_SHIM_2:
+ code = 0x71;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_FROM_DFLT:
+ code = 0x10;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_FROM_FRAME_START:
+ code = 0x40;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_FROM_PARSE_RESULT:
+ code = 0x20;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_FROM_END_OF_PARSE:
+ code = 0x7f;
+ break;
+
+ case E_FMAN_KG_GEN_EXTRACT_FROM_FQID:
+ code = 0x20;
+ *offset += 0x20;
+ break;
+
+ default:
+ code = FM_KG_SCH_GEN_HT_INVALID;
+ }
+
+ return (uint8_t)code;
+}
+
+static uint32_t build_ar_scheme(uint8_t scheme,
+ uint8_t hwport_id,
+ bool update_counter, bool write)
+{
+ uint32_t rw;
+
+ rw = (uint32_t)(write ? FM_KG_KGAR_WRITE : FM_KG_KGAR_READ);
+
+ return (uint32_t)(FM_KG_KGAR_GO | rw | FM_KG_KGAR_SEL_SCHEME_ENTRY |
+ hwport_id |
+ ((uint32_t)scheme << FM_KG_KGAR_NUM_SHIFT) |
+ (update_counter ? FM_KG_KGAR_SCM_WSEL_UPDATE_CNT :
+ 0));
+}
+
+static uint32_t build_ar_cls_plan(uint8_t grp,
+ uint8_t entries_mask,
+ uint8_t hwport_id, bool write)
+{
+ uint32_t rw;
+
+ rw = (uint32_t)(write ? FM_KG_KGAR_WRITE : FM_KG_KGAR_READ);
+
+ return (uint32_t)(FM_KG_KGAR_GO | rw |
+ FM_PCD_KG_KGAR_SEL_CLS_PLAN_ENTRY | hwport_id |
+ ((uint32_t)grp << FM_KG_KGAR_NUM_SHIFT) |
+ ((uint32_t)entries_mask << FM_KG_KGAR_WSEL_SHIFT));
+}
+
+int fman_kg_write_ar_wait(struct fman_kg_regs __iomem *regs, uint32_t fmkg_ar)
+{
+ iowrite32be(fmkg_ar, ®s->fmkg_ar);
+ /* Wait for GO to be idle and read error */
+ while ((fmkg_ar = ioread32be(®s->fmkg_ar)) & FM_KG_KGAR_GO)
+ ;
+ if (fmkg_ar & FM_PCD_KG_KGAR_ERR)
+ return -EINVAL;
+ return 0;
+}
+
+void fman_kg_write_sp(struct fman_kg_regs __iomem *regs, uint32_t sp, bool add)
+{
+ struct fman_kg_pe_regs __iomem *kgpe_regs;
+ uint32_t tmp;
+
+ kgpe_regs = (struct fman_kg_pe_regs __iomem *)®s->fmkg_indirect[0];
+ tmp = ioread32be(&kgpe_regs->fmkg_pe_sp);
+
+ if (add)
+ tmp |= sp;
+ else /* clear */
+ tmp &= ~sp;
+
+ iowrite32be(tmp, &kgpe_regs->fmkg_pe_sp);
+}
+
+void fman_kg_write_cpp(struct fman_kg_regs __iomem *regs, uint32_t cpp)
+{
+ struct fman_kg_pe_regs __iomem *kgpe_regs;
+
+ kgpe_regs = (struct fman_kg_pe_regs __iomem *)®s->fmkg_indirect[0];
+
+ iowrite32be(cpp, &kgpe_regs->fmkg_pe_cpp);
+}
+
+void fman_kg_get_event(struct fman_kg_regs __iomem *regs,
+ uint32_t *event, uint32_t *scheme_idx)
+{
+ uint32_t mask, force;
+
+ *event = ioread32be(®s->fmkg_eer);
+ mask = ioread32be(®s->fmkg_eeer);
+ *scheme_idx = ioread32be(®s->fmkg_seer);
+ *scheme_idx &= ioread32be(®s->fmkg_seeer);
+
+ *event &= mask;
+
+ /* clear the forced events */
+ force = ioread32be(®s->fmkg_feer);
+ if (force & *event)
+ iowrite32be(force & ~*event, ®s->fmkg_feer);
+
+ iowrite32be(*event, ®s->fmkg_eer);
+ iowrite32be(*scheme_idx, ®s->fmkg_seer);
+}
+
+void fman_kg_init(struct fman_kg_regs __iomem *regs,
+ uint32_t exceptions, uint32_t dflt_nia)
+{
+ uint32_t tmp;
+ int i;
+
+ iowrite32be(FM_EX_KG_DOUBLE_ECC | FM_EX_KG_KEYSIZE_OVERFLOW,
+ ®s->fmkg_eer);
+
+ tmp = 0;
+ if (exceptions & FM_EX_KG_DOUBLE_ECC)
+ tmp |= FM_EX_KG_DOUBLE_ECC;
+
+ if (exceptions & FM_EX_KG_KEYSIZE_OVERFLOW)
+ tmp |= FM_EX_KG_KEYSIZE_OVERFLOW;
+
+ iowrite32be(tmp, ®s->fmkg_eeer);
+ iowrite32be(0, ®s->fmkg_fdor);
+ iowrite32be(0, ®s->fmkg_gdv0r);
+ iowrite32be(0, ®s->fmkg_gdv1r);
+ iowrite32be(dflt_nia, ®s->fmkg_gcr);
+
+ /* Clear binding between ports to schemes and classification plans
+ * so that all ports are not bound to any scheme/classification plan
+ */
+ for (i = 0; i < FMAN_MAX_NUM_OF_HW_PORTS; i++) {
+ clear_pe_all_scheme(regs, (uint8_t)i);
+ clear_pe_all_cls_plan(regs, (uint8_t)i);
+ }
+}
+
+void fman_kg_enable_scheme_interrupts(struct fman_kg_regs __iomem *regs)
+{
+ /* enable and enable all scheme interrupts */
+ iowrite32be(0xFFFFFFFF, ®s->fmkg_seer);
+ iowrite32be(0xFFFFFFFF, ®s->fmkg_seeer);
+}
+
+void fman_kg_enable(struct fman_kg_regs __iomem *regs)
+{
+ iowrite32be(ioread32be(®s->fmkg_gcr) | FM_KG_KGGCR_EN,
+ ®s->fmkg_gcr);
+}
+
+void fman_kg_disable(struct fman_kg_regs __iomem *regs)
+{
+ iowrite32be(ioread32be(®s->fmkg_gcr) & ~FM_KG_KGGCR_EN,
+ ®s->fmkg_gcr);
+}
+
+void fman_kg_set_data_after_prs(struct fman_kg_regs __iomem *regs,
+ uint8_t offset)
+{
+ iowrite32be(offset, ®s->fmkg_fdor);
+}
+
+void fman_kg_set_dflt_val(struct fman_kg_regs __iomem *regs,
+ uint8_t def_id, uint32_t val)
+{
+ if (def_id == 0)
+ iowrite32be(val, ®s->fmkg_gdv0r);
+ else
+ iowrite32be(val, ®s->fmkg_gdv1r);
+}
+
+void fman_kg_set_exception(struct fman_kg_regs __iomem *regs,
+ uint32_t exception, bool enable)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->fmkg_eeer);
+
+ if (enable)
+ tmp |= exception;
+ else
+ tmp &= ~exception;
+
+ iowrite32be(tmp, ®s->fmkg_eeer);
+}
+
+void fman_kg_get_exception(struct fman_kg_regs __iomem *regs,
+ uint32_t *events, uint32_t *scheme_ids, bool clear)
+{
+ uint32_t mask;
+
+ *events = ioread32be(®s->fmkg_eer);
+ mask = ioread32be(®s->fmkg_eeer);
+ *events &= mask;
+
+ *scheme_ids = 0;
+
+ if (*events & FM_EX_KG_KEYSIZE_OVERFLOW) {
+ *scheme_ids = ioread32be(®s->fmkg_seer);
+ mask = ioread32be(®s->fmkg_seeer);
+ *scheme_ids &= mask;
+ }
+
+ if (clear) {
+ iowrite32be(*scheme_ids, ®s->fmkg_seer);
+ iowrite32be(*events, ®s->fmkg_eer);
+ }
+}
+
+void fman_kg_get_capture(struct fman_kg_regs __iomem *regs,
+ struct fman_kg_ex_ecc_attr *ecc_attr, bool clear)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->fmkg_serc);
+
+ if (tmp & KG_FMKG_SERC_CAP) {
+ /* Captured data is valid */
+ ecc_attr->valid = true;
+ ecc_attr->double_ecc =
+ (bool)((tmp & KG_FMKG_SERC_CET) ? true : false);
+ ecc_attr->single_ecc_count =
+ (uint8_t)((tmp & KG_FMKG_SERC_CNT_MSK) >>
+ KG_FMKG_SERC_CNT_SHIFT);
+ ecc_attr->addr = (uint16_t)(tmp & KG_FMKG_SERC_ADDR_MSK);
+
+ if (clear)
+ iowrite32be(KG_FMKG_SERC_CAP, ®s->fmkg_serc);
+ } else {
+ /* No ECC error is captured */
+ ecc_attr->valid = false;
+ }
+}
+
+int fman_kg_build_scheme(struct fman_kg_scheme_params *params,
+ struct fman_kg_scheme_regs *scheme_regs)
+{
+ struct fman_kg_extract_params *extract_params;
+ struct fman_kg_gen_extract_params *gen_params;
+ uint32_t tmp_reg, i, select, mask, fqb;
+ uint8_t offset, shift, ht;
+
+ /* Zero out all registers so no need to care about unused ones */
+ memset(scheme_regs, 0, sizeof(struct fman_kg_scheme_regs));
+
+ /* Mode register */
+ tmp_reg = fm_kg_build_nia(params->next_engine,
+ params->next_engine_action);
+ if (tmp_reg == KG_NIA_INVALID)
+ return -EINVAL;
+
+ if (params->next_engine == E_FMAN_PCD_PLCR) {
+ tmp_reg |= FMAN_KG_SCH_MODE_NIA_PLCR;
+ } else if (params->next_engine == E_FMAN_PCD_CC) {
+ tmp_reg |= (uint32_t)params->cc_params.base_offset <<
+ FMAN_KG_SCH_MODE_CCOBASE_SHIFT;
+ }
+
+ tmp_reg |= FMAN_KG_SCH_MODE_EN;
+ scheme_regs->kgse_mode = tmp_reg;
+
+ /* Match vector */
+ scheme_regs->kgse_mv = params->match_vector;
+
+ extract_params = ¶ms->extract_params;
+
+ /* Scheme default values registers */
+ scheme_regs->kgse_dv0 = extract_params->def_scheme_0;
+ scheme_regs->kgse_dv1 = extract_params->def_scheme_1;
+
+ /* Extract Known Fields Command register */
+ scheme_regs->kgse_ekfc = extract_params->known_fields;
+
+ /* Entry Extract Known Default Value register */
+ tmp_reg = 0;
+ tmp_reg |= extract_params->known_fields_def.mac_addr <<
+ FMAN_KG_SCH_DEF_MAC_ADDR_SHIFT;
+ tmp_reg |= extract_params->known_fields_def.vlan_tci <<
+ FMAN_KG_SCH_DEF_VLAN_TCI_SHIFT;
+ tmp_reg |= extract_params->known_fields_def.etype <<
+ FMAN_KG_SCH_DEF_ETYPE_SHIFT;
+ tmp_reg |= extract_params->known_fields_def.ppp_sid <<
+ FMAN_KG_SCH_DEF_PPP_SID_SHIFT;
+ tmp_reg |= extract_params->known_fields_def.ppp_pid <<
+ FMAN_KG_SCH_DEF_PPP_PID_SHIFT;
+ tmp_reg |= extract_params->known_fields_def.mpls <<
+ FMAN_KG_SCH_DEF_MPLS_SHIFT;
+ tmp_reg |= extract_params->known_fields_def.ip_addr <<
+ FMAN_KG_SCH_DEF_IP_ADDR_SHIFT;
+ tmp_reg |= extract_params->known_fields_def.ptype <<
+ FMAN_KG_SCH_DEF_PTYPE_SHIFT;
+ tmp_reg |= extract_params->known_fields_def.ip_tos_tc <<
+ FMAN_KG_SCH_DEF_IP_TOS_TC_SHIFT;
+ tmp_reg |= extract_params->known_fields_def.ipv6_fl <<
+ FMAN_KG_SCH_DEF_IPV6_FL_SHIFT;
+ tmp_reg |= extract_params->known_fields_def.ipsec_spi <<
+ FMAN_KG_SCH_DEF_IPSEC_SPI_SHIFT;
+ tmp_reg |= extract_params->known_fields_def.l4_port <<
+ FMAN_KG_SCH_DEF_L4_PORT_SHIFT;
+ tmp_reg |= extract_params->known_fields_def.tcp_flg <<
+ FMAN_KG_SCH_DEF_TCP_FLG_SHIFT;
+
+ scheme_regs->kgse_ekdv = tmp_reg;
+
+ /* Generic extract registers */
+ if (extract_params->gen_extract_num > FM_KG_NUM_OF_GENERIC_REGS)
+ return -EINVAL;
+
+ for (i = 0; i < extract_params->gen_extract_num; i++) {
+ gen_params = extract_params->gen_extract + i;
+
+ tmp_reg = FMAN_KG_SCH_GEN_VALID;
+ tmp_reg |= (uint32_t)gen_params->def_val <<
+ FMAN_KG_SCH_GEN_DEF_SHIFT;
+
+ if (gen_params->type == E_FMAN_KG_HASH_EXTRACT) {
+ if ((gen_params->extract > FMAN_KG_SCH_GEN_SIZE_MAX) ||
+ (gen_params->extract == 0)) {
+ return -EINVAL;
+ }
+ } else {
+ tmp_reg |= FMAN_KG_SCH_GEN_OR;
+ }
+
+ tmp_reg |= (uint32_t)gen_params->extract <<
+ FMAN_KG_SCH_GEN_SIZE_SHIFT;
+ tmp_reg |= (uint32_t)gen_params->mask <<
+ FMAN_KG_SCH_GEN_MASK_SHIFT;
+
+ offset = gen_params->offset;
+ ht = get_gen_ht_code(gen_params->src,
+ gen_params->no_validation, &offset);
+ tmp_reg |= (uint32_t)ht << FMAN_KG_SCH_GEN_HT_SHIFT;
+ tmp_reg |= offset;
+
+ scheme_regs->kgse_gec[i] = tmp_reg;
+ }
+
+ /* Masks registers */
+ if (extract_params->masks_num > FM_KG_EXTRACT_MASKS_NUM)
+ return -EINVAL;
+
+ select = 0;
+ mask = 0;
+ fqb = 0;
+ for (i = 0; i < extract_params->masks_num; i++) {
+ /* MCSx fields */
+ KG_GET_MASK_SEL_SHIFT(shift, i);
+ if (extract_params->masks[i].is_known) {
+ /* Mask known field */
+ select |= extract_params->masks[i].field_or_gen_idx <<
+ shift;
+ } else {
+ /* Mask generic extract */
+ select |= (extract_params->masks[i].field_or_gen_idx +
+ FM_KG_MASK_SEL_GEN_BASE) << shift;
+ }
+
+ /* MOx fields - spread between se_bmch and se_fqb registers */
+ KG_GET_MASK_OFFSET_SHIFT(shift, i);
+ if (i < 2) {
+ select |= (uint32_t)extract_params->masks[i].offset <<
+ shift;
+ } else {
+ fqb |= (uint32_t)extract_params->masks[i].offset <<
+ shift;
+ }
+
+ /* BMx fields */
+ KG_GET_MASK_SHIFT(shift, i);
+ mask |= (uint32_t)extract_params->masks[i].mask << shift;
+ }
+
+ /* Finish with rest of BMx fileds -
+ * don't mask bits for unused masks by setting
+ * corresponding BMx field = 0xFF
+ */
+ for (i = extract_params->masks_num; i < FM_KG_EXTRACT_MASKS_NUM; i++) {
+ KG_GET_MASK_SHIFT(shift, i);
+ mask |= 0xFF << shift;
+ }
+
+ scheme_regs->kgse_bmch = select;
+ scheme_regs->kgse_bmcl = mask;
+
+ /* Finish with FQB register initialization.
+ * Check fqid is 24-bit value.
+ */
+ if (params->base_fqid & ~0x00FFFFFF)
+ return -EINVAL;
+
+ fqb |= params->base_fqid;
+ scheme_regs->kgse_fqb = fqb;
+
+ /* Hash Configuration register */
+ tmp_reg = 0;
+ if (params->hash_params.use_hash) {
+ /* Check hash mask is 24-bit value */
+ if (params->hash_params.mask & ~0x00FFFFFF)
+ return -EINVAL;
+
+ /* Hash function produces 64-bit value, 24 bits of that
+ * are used to generate fq_id and policer profile.
+ * Thus, maximal shift is 40 bits to allow 24 bits out of 64.
+ */
+ if (params->hash_params.shift_r > FMAN_KG_SCH_HASH_HSHIFT_MAX)
+ return -EINVAL;
+
+ tmp_reg |= params->hash_params.mask;
+ tmp_reg |= (uint32_t)params->hash_params.shift_r <<
+ FMAN_KG_SCH_HASH_HSHIFT_SHIFT;
+
+ if (params->hash_params.sym)
+ tmp_reg |= FMAN_KG_SCH_HASH_SYM;
+ }
+
+ if (params->bypass_fqid_gen)
+ tmp_reg |= FMAN_KG_SCH_HASH_NO_FQID_GEN;
+
+ scheme_regs->kgse_hc = tmp_reg;
+
+ /* Policer Profile register */
+ if (params->policer_params.bypass_pp_gen) {
+ tmp_reg = FMAN_KG_SCH_PP_NO_GEN;
+ } else {
+ /* Lower 8 bits of 24-bits extracted from hash result
+ * are used for policer profile generation.
+ * That leaves maximum shift value = 23.
+ */
+ if (params->policer_params.shift > FMAN_KG_SCH_PP_SHIFT_MAX)
+ return -EINVAL;
+
+ tmp_reg = params->policer_params.base;
+ tmp_reg |= ((uint32_t)params->policer_params.shift <<
+ FMAN_KG_SCH_PP_SH_SHIFT) & FMAN_KG_SCH_PP_SH_MASK;
+ tmp_reg |= ((uint32_t)params->policer_params.shift <<
+ FMAN_KG_SCH_PP_SL_SHIFT) & FMAN_KG_SCH_PP_SL_MASK;
+ tmp_reg |= (uint32_t)params->policer_params.mask <<
+ FMAN_KG_SCH_PP_MASK_SHIFT;
+ }
+
+ scheme_regs->kgse_ppc = tmp_reg;
+
+ /* Coarse Classification Bit Select register */
+ if (params->next_engine == E_FMAN_PCD_CC)
+ scheme_regs->kgse_ccbs = params->cc_params.qlcv_bits_sel;
+
+ /* Packets Counter register */
+ if (params->update_counter)
+ scheme_regs->kgse_spc = params->counter_value;
+ return 0;
+}
+
+int fman_kg_write_scheme(struct fman_kg_regs __iomem *regs,
+ uint8_t scheme_id,
+ uint8_t hwport_id,
+ struct fman_kg_scheme_regs *scheme_regs,
+ bool update_counter)
+{
+ struct fman_kg_scheme_regs __iomem *kgse_regs;
+ uint32_t tmp_reg;
+ int err, i;
+
+ /* Write indirect scheme registers */
+ kgse_regs =
+ (struct fman_kg_scheme_regs __iomem *)®s->fmkg_indirect[0];
+
+ iowrite32be(scheme_regs->kgse_mode, &kgse_regs->kgse_mode);
+ iowrite32be(scheme_regs->kgse_ekfc, &kgse_regs->kgse_ekfc);
+ iowrite32be(scheme_regs->kgse_ekdv, &kgse_regs->kgse_ekdv);
+ iowrite32be(scheme_regs->kgse_bmch, &kgse_regs->kgse_bmch);
+ iowrite32be(scheme_regs->kgse_bmcl, &kgse_regs->kgse_bmcl);
+ iowrite32be(scheme_regs->kgse_fqb, &kgse_regs->kgse_fqb);
+ iowrite32be(scheme_regs->kgse_hc, &kgse_regs->kgse_hc);
+ iowrite32be(scheme_regs->kgse_ppc, &kgse_regs->kgse_ppc);
+ iowrite32be(scheme_regs->kgse_spc, &kgse_regs->kgse_spc);
+ iowrite32be(scheme_regs->kgse_dv0, &kgse_regs->kgse_dv0);
+ iowrite32be(scheme_regs->kgse_dv1, &kgse_regs->kgse_dv1);
+ iowrite32be(scheme_regs->kgse_ccbs, &kgse_regs->kgse_ccbs);
+ iowrite32be(scheme_regs->kgse_mv, &kgse_regs->kgse_mv);
+
+ for (i = 0; i < FM_KG_NUM_OF_GENERIC_REGS; i++)
+ iowrite32be(scheme_regs->kgse_gec[i], &kgse_regs->kgse_gec[i]);
+
+ /* Write AR (Action register) */
+ tmp_reg = build_ar_scheme(scheme_id, hwport_id, update_counter, true);
+ err = fman_kg_write_ar_wait(regs, tmp_reg);
+ return err;
+}
+
+int fman_kg_delete_scheme(struct fman_kg_regs __iomem *regs,
+ uint8_t scheme_id, uint8_t hwport_id)
+{
+ struct fman_kg_scheme_regs __iomem *kgse_regs;
+ uint32_t tmp_reg;
+ int err, i;
+
+ kgse_regs =
+ (struct fman_kg_scheme_regs __iomem *)®s->fmkg_indirect[0];
+
+ /* Clear all registers including enable bit in mode register */
+ for (i = 0; i < (sizeof(struct fman_kg_scheme_regs)) / 4; ++i)
+ iowrite32be(0, ((uint32_t __iomem *)kgse_regs + i));
+
+ /* Write AR (Action register) */
+ tmp_reg = build_ar_scheme(scheme_id, hwport_id, false, true);
+ err = fman_kg_write_ar_wait(regs, tmp_reg);
+ return err;
+}
+
+int fman_kg_get_scheme_counter(struct fman_kg_regs __iomem *regs,
+ uint8_t scheme_id,
+ uint8_t hwport_id, uint32_t *counter)
+{
+ struct fman_kg_scheme_regs __iomem *kgse_regs;
+ uint32_t tmp_reg;
+ int err;
+
+ kgse_regs =
+ (struct fman_kg_scheme_regs __iomem *)®s->fmkg_indirect[0];
+
+ tmp_reg = build_ar_scheme(scheme_id, hwport_id, true, false);
+ err = fman_kg_write_ar_wait(regs, tmp_reg);
+
+ if (err != 0)
+ return err;
+
+ *counter = ioread32be(&kgse_regs->kgse_spc);
+
+ return 0;
+}
+
+int fman_kg_set_scheme_counter(struct fman_kg_regs __iomem *regs,
+ uint8_t scheme_id,
+ uint8_t hwport_id, uint32_t counter)
+{
+ struct fman_kg_scheme_regs __iomem *kgse_regs;
+ uint32_t tmp_reg;
+ int err;
+
+ kgse_regs =
+ (struct fman_kg_scheme_regs __iomem *)®s->fmkg_indirect[0];
+
+ tmp_reg = build_ar_scheme(scheme_id, hwport_id, true, false);
+
+ err = fman_kg_write_ar_wait(regs, tmp_reg);
+ if (err != 0)
+ return err;
+
+ /* Keygen indirect access memory contains all scheme_id registers
+ * by now. Change only counter value.
+ */
+ iowrite32be(counter, &kgse_regs->kgse_spc);
+
+ /* Write back scheme registers */
+ tmp_reg = build_ar_scheme(scheme_id, hwport_id, true, true);
+ err = fman_kg_write_ar_wait(regs, tmp_reg);
+
+ return err;
+}
+
+uint32_t fman_kg_get_schemes_total_counter(struct fman_kg_regs __iomem *regs)
+{
+ return ioread32be(®s->fmkg_tpc);
+}
+
+int fman_kg_build_cls_plan(struct fman_kg_cls_plan_params *params,
+ struct fman_kg_cp_regs *cls_plan_regs)
+{
+ uint8_t entries_set, entry_bit;
+ int i;
+
+ /* Zero out all group's register */
+ memset(cls_plan_regs, 0, sizeof(struct fman_kg_cp_regs));
+
+ /* Go over all classification entries in params->entries_mask and
+ * configure the corresponding cpe register
+ */
+ entries_set = params->entries_mask;
+ for (i = 0; entries_set; i++) {
+ entry_bit = (uint8_t)(0x80 >> i);
+ if ((entry_bit & entries_set) == 0)
+ continue;
+ entries_set ^= entry_bit;
+ cls_plan_regs->kgcpe[i] = params->mask_vector[i];
+ }
+
+ return 0;
+}
+
+int fman_kg_write_cls_plan(struct fman_kg_regs __iomem *regs,
+ uint8_t grp_id,
+ uint8_t entries_mask,
+ uint8_t hwport_id,
+ struct fman_kg_cp_regs __iomem *cls_plan_regs)
+{
+ struct fman_kg_cp_regs __iomem *kgcpe_regs;
+ uint32_t tmp_reg;
+ int i, err;
+
+ /* Check group index is valid and the group isn't empty */
+ if (grp_id >= FM_KG_CLS_PLAN_GRPS_NUM)
+ return -EINVAL;
+
+ /* Write indirect classification plan registers */
+ kgcpe_regs = (struct fman_kg_cp_regs __iomem *)®s->fmkg_indirect[0];
+
+ for (i = 0; i < FM_KG_NUM_CLS_PLAN_ENTR; i++)
+ iowrite32be(cls_plan_regs->kgcpe[i], &kgcpe_regs->kgcpe[i]);
+
+ tmp_reg = build_ar_cls_plan(grp_id, entries_mask, hwport_id, true);
+ err = fman_kg_write_ar_wait(regs, tmp_reg);
+ return err;
+}
+
+int fman_kg_write_bind_schemes(struct fman_kg_regs __iomem *regs,
+ uint8_t hwport_id, uint32_t schemes)
+{
+ struct fman_kg_pe_regs __iomem *kg_pe_regs;
+ uint32_t tmp_reg;
+ int err;
+
+ kg_pe_regs = (struct fman_kg_pe_regs __iomem *)®s->fmkg_indirect[0];
+
+ iowrite32be(schemes, &kg_pe_regs->fmkg_pe_sp);
+
+ tmp_reg = build_ar_bind_scheme(hwport_id, true);
+ err = fman_kg_write_ar_wait(regs, tmp_reg);
+ return err;
+}
+
+int fman_kg_build_bind_cls_plans(uint8_t grp_base,
+ uint8_t grp_mask, uint32_t *bind_cls_plans)
+{
+ /* Check grp_base and grp_mask are 5-bits values */
+ if ((grp_base & ~0x0000001F) || (grp_mask & ~0x0000001F))
+ return -EINVAL;
+
+ *bind_cls_plans =
+ (uint32_t)((grp_mask << FMAN_KG_PE_CPP_MASK_SHIFT) | grp_base);
+ return 0;
+}
+
+int fman_kg_write_bind_cls_plans(struct fman_kg_regs __iomem *regs,
+ uint8_t hwport_id, uint32_t bind_cls_plans)
+{
+ struct fman_kg_pe_regs __iomem *kg_pe_regs;
+ uint32_t tmp_reg;
+ int err;
+
+ kg_pe_regs = (struct fman_kg_pe_regs __iomem *)®s->fmkg_indirect[0];
+
+ iowrite32be(bind_cls_plans, &kg_pe_regs->fmkg_pe_cpp);
+
+ tmp_reg = build_ar_bind_cls_plan(hwport_id, true);
+ err = fman_kg_write_ar_wait(regs, tmp_reg);
+ return err;
+}
diff --git a/drivers/soc/fsl/fman/pcd/fman_prs.c b/drivers/soc/fsl/fman/pcd/fman_prs.c
new file mode 100644
index 0000000..e4bb20f
--- /dev/null
+++ b/drivers/soc/fsl/fman/pcd/fman_prs.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fman_prs.h"
+
+uint32_t fman_prs_get_err_event(struct fman_prs_regs __iomem *regs,
+ uint32_t ev_mask)
+{
+ return ioread32be(®s->fmpr_perr) & ev_mask;
+}
+
+uint32_t fman_prs_get_err_ev_mask(struct fman_prs_regs __iomem *regs)
+{
+ return ioread32be(®s->fmpr_perer);
+}
+
+void fman_prs_ack_err_event(struct fman_prs_regs __iomem *regs, uint32_t event)
+{
+ iowrite32be(event, ®s->fmpr_perr);
+}
+
+uint32_t fman_prs_get_expt_event(struct fman_prs_regs __iomem *regs,
+ uint32_t ev_mask)
+{
+ return ioread32be(®s->fmpr_pevr) & ev_mask;
+}
+
+uint32_t fman_prs_get_expt_ev_mask(struct fman_prs_regs __iomem *regs)
+{
+ return ioread32be(®s->fmpr_pever);
+}
+
+void fman_prs_ack_expt_event(struct fman_prs_regs __iomem *regs, uint32_t event)
+{
+ iowrite32be(event, ®s->fmpr_pevr);
+}
+
+void fman_prs_defconfig(struct fman_prs_cfg *cfg)
+{
+ cfg->port_id_stat = 0;
+ cfg->max_prs_cyc_lim = DEFAULT_MAX_PRS_CYC_LIM;
+ cfg->prs_exceptions = 0x03000000;
+}
+
+int fman_prs_init(struct fman_prs_regs __iomem *regs, struct fman_prs_cfg *cfg)
+{
+ uint32_t tmp;
+
+ iowrite32be(cfg->max_prs_cyc_lim, ®s->fmpr_rpclim);
+ iowrite32be((FM_PCD_PRS_SINGLE_ECC | FM_PCD_PRS_PORT_IDLE_STS),
+ ®s->fmpr_pevr);
+
+ if (cfg->prs_exceptions & FM_PCD_EX_PRS_SINGLE_ECC)
+ iowrite32be(FM_PCD_PRS_SINGLE_ECC, ®s->fmpr_pever);
+ else
+ iowrite32be(0, ®s->fmpr_pever);
+
+ iowrite32be(FM_PCD_PRS_DOUBLE_ECC, ®s->fmpr_perr);
+
+ tmp = 0;
+ if (cfg->prs_exceptions & FM_PCD_EX_PRS_DOUBLE_ECC)
+ tmp |= FM_PCD_PRS_DOUBLE_ECC;
+ iowrite32be(tmp, ®s->fmpr_perer);
+
+ iowrite32be(cfg->port_id_stat, ®s->fmpr_ppsc);
+
+ return 0;
+}
+
+void fman_prs_enable(struct fman_prs_regs __iomem *regs)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->fmpr_rpimac) | FM_PCD_PRS_RPIMAC_EN;
+ iowrite32be(tmp, ®s->fmpr_rpimac);
+}
+
+void fman_prs_disable(struct fman_prs_regs __iomem *regs)
+{
+ uint32_t tmp;
+
+ tmp = ioread32be(®s->fmpr_rpimac) & ~FM_PCD_PRS_RPIMAC_EN;
+ iowrite32be(tmp, ®s->fmpr_rpimac);
+}
+
+void fman_prs_set_stst_port_msk(struct fman_prs_regs __iomem *regs,
+ uint32_t pid_msk)
+{
+ iowrite32be(pid_msk, ®s->fmpr_ppsc);
+}
+
+void fman_prs_set_stst(struct fman_prs_regs __iomem *regs, bool enable)
+{
+ if (enable)
+ iowrite32be(FM_PCD_PRS_PPSC_ALL_PORTS, ®s->fmpr_ppsc);
+ else
+ iowrite32be(0, ®s->fmpr_ppsc);
+}
--
2.3.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 6/7] soc/fman: Add the FMan RTC FLIB
2015-03-05 5:45 [PATCH 0/7] Freescale DPAA FMan FLIB(s) Emil Medve
` (4 preceding siblings ...)
2015-03-05 5:45 ` [PATCH 5/7] soc/fman: Add the FMan parser and KeyGen FLIB(s) Emil Medve
@ 2015-03-05 5:45 ` Emil Medve
2015-03-05 5:45 ` [PATCH 7/7] soc/fman: Add the FMan SP FLIB Emil Medve
2015-03-05 12:32 ` [PATCH 0/7] Freescale DPAA FMan FLIB(s) Jamal Hadi Salim
7 siblings, 0 replies; 15+ messages in thread
From: Emil Medve @ 2015-03-05 5:45 UTC (permalink / raw)
To: linuxppc-dev, netdev, linux-kernel; +Cc: Igal Liberman
From: Igal Liberman <Igal.Liberman@freescale.com>
Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
---
drivers/soc/fsl/fman/Kconfig | 6 +
drivers/soc/fsl/fman/Makefile | 1 +
drivers/soc/fsl/fman/rtc/Makefile | 13 ++
drivers/soc/fsl/fman/rtc/fman_rtc.c | 354 ++++++++++++++++++++++++++++++++++++
4 files changed, 374 insertions(+)
create mode 100644 drivers/soc/fsl/fman/rtc/Makefile
create mode 100644 drivers/soc/fsl/fman/rtc/fman_rtc.c
diff --git a/drivers/soc/fsl/fman/Kconfig b/drivers/soc/fsl/fman/Kconfig
index 2559ee9..a144eb5 100644
--- a/drivers/soc/fsl/fman/Kconfig
+++ b/drivers/soc/fsl/fman/Kconfig
@@ -26,4 +26,10 @@ config FSL_FMAN_PCD
help
Freescale DPAA FMan Parse, Classify and Distribute support
+config FSL_FMAN_RTC
+ bool "FMan RTC"
+ default n
+ help
+ Freescale DPAA FMan Real Time Clock (PTP) support
+
endif # FSL_FMAN
diff --git a/drivers/soc/fsl/fman/Makefile b/drivers/soc/fsl/fman/Makefile
index dc37f35..f415188 100644
--- a/drivers/soc/fsl/fman/Makefile
+++ b/drivers/soc/fsl/fman/Makefile
@@ -13,5 +13,6 @@ fsl_fman-objs := fman.o
obj-$(CONFIG_FSL_FMAN_PORT) += port/
obj-$(CONFIG_FSL_FMAN_MAC) += mac/
obj-$(CONFIG_FSL_FMAN_PCD) += pcd/
+obj-$(CONFIG_FSL_FMAN_RTC) += rtc/
endif
diff --git a/drivers/soc/fsl/fman/rtc/Makefile b/drivers/soc/fsl/fman/rtc/Makefile
new file mode 100644
index 0000000..69a92fb
--- /dev/null
+++ b/drivers/soc/fsl/fman/rtc/Makefile
@@ -0,0 +1,13 @@
+ccflags-y += -DVERSION=\"\"
+
+ifeq ($(CONFIG_FSL_FMAN_RTC),y)
+
+FMAN = $(srctree)/drivers/soc/fsl/fman
+
+ccflags-y += -I$(FMAN)/flib
+
+obj-$(CONFIG_FSL_FMAN_RTC) += fsl_fman_rtc.o
+
+fsl_fman_rtc-objs := fman_rtc.o
+
+endif
diff --git a/drivers/soc/fsl/fman/rtc/fman_rtc.c b/drivers/soc/fsl/fman/rtc/fman_rtc.c
new file mode 100644
index 0000000..e6d6dae
--- /dev/null
+++ b/drivers/soc/fsl/fman/rtc/fman_rtc.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fman_rtc.h"
+
+void fman_rtc_defconfig(struct rtc_cfg *cfg)
+{
+ int i;
+
+ cfg->src_clk = DEFAULT_SRC_CLOCK;
+ cfg->invert_input_clk_phase = DEFAULT_INVERT_INPUT_CLK_PHASE;
+ cfg->invert_output_clk_phase = DEFAULT_INVERT_OUTPUT_CLK_PHASE;
+ cfg->pulse_realign = DEFAULT_PULSE_REALIGN;
+ for (i = 0; i < FMAN_RTC_MAX_NUM_OF_ALARMS; i++)
+ cfg->alarm_polarity[i] = DEFAULT_ALARM_POLARITY;
+ for (i = 0; i < FMAN_RTC_MAX_NUM_OF_EXT_TRIGGERS; i++)
+ cfg->trigger_polarity[i] = DEFAULT_TRIGGER_POLARITY;
+}
+
+uint32_t fman_rtc_get_events(struct rtc_regs __iomem *regs)
+{
+ return ioread32be(®s->tmr_tevent);
+}
+
+uint32_t fman_rtc_get_event(struct rtc_regs __iomem *regs, uint32_t ev_mask)
+{
+ return ioread32be(®s->tmr_tevent) & ev_mask;
+}
+
+uint32_t fman_rtc_get_interrupt_mask(struct rtc_regs __iomem *regs)
+{
+ return ioread32be(®s->tmr_temask);
+}
+
+void fman_rtc_set_interrupt_mask(struct rtc_regs __iomem *regs, uint32_t mask)
+{
+ iowrite32be(mask, ®s->tmr_temask);
+}
+
+void fman_rtc_ack_event(struct rtc_regs __iomem *regs, uint32_t events)
+{
+ iowrite32be(events, ®s->tmr_tevent);
+}
+
+uint32_t fman_rtc_check_and_clear_event(struct rtc_regs __iomem *regs)
+{
+ uint32_t event;
+
+ event = ioread32be(®s->tmr_tevent);
+ event &= ioread32be(®s->tmr_temask);
+
+ if (event)
+ iowrite32be(event, ®s->tmr_tevent);
+ return event;
+}
+
+uint32_t fman_rtc_get_frequency_compensation(struct rtc_regs __iomem *regs)
+{
+ return ioread32be(®s->tmr_add);
+}
+
+void fman_rtc_set_frequency_compensation(struct rtc_regs __iomem *regs,
+ uint32_t val)
+{
+ iowrite32be(val, ®s->tmr_add);
+}
+
+void fman_rtc_enable_interrupt(struct rtc_regs __iomem *regs, uint32_t events)
+{
+ fman_rtc_set_interrupt_mask(regs,
+ fman_rtc_get_interrupt_mask(regs) | events);
+}
+
+void fman_rtc_disable_interrupt(struct rtc_regs __iomem *regs, uint32_t events)
+{
+ fman_rtc_set_interrupt_mask(regs,
+ fman_rtc_get_interrupt_mask(regs) &
+ ~events);
+}
+
+void fman_rtc_set_timer_alarm_l(struct rtc_regs __iomem *regs, int index,
+ uint32_t val)
+{
+ iowrite32be(val, ®s->tmr_alarm[index].tmr_alarm_l);
+}
+
+void fman_rtc_set_timer_fiper(struct rtc_regs __iomem *regs, int index,
+ uint32_t val)
+{
+ iowrite32be(val, ®s->tmr_fiper[index]);
+}
+
+void fman_rtc_set_timer_alarm(struct rtc_regs __iomem *regs, int index,
+ int64_t val)
+{
+ iowrite32be((uint32_t)val, ®s->tmr_alarm[index].tmr_alarm_l);
+ iowrite32be((uint32_t)(val >> 32),
+ ®s->tmr_alarm[index].tmr_alarm_h);
+}
+
+void fman_rtc_set_timer_offset(struct rtc_regs __iomem *regs, int64_t val)
+{
+ iowrite32be((uint32_t)val, ®s->tmr_off_l);
+ iowrite32be((uint32_t)(val >> 32), ®s->tmr_off_h);
+}
+
+uint64_t fman_rtc_get_trigger_stamp(struct rtc_regs __iomem *regs, int id)
+{
+ uint64_t time;
+ /* TMR_CNT_L must be read first to get an accurate value */
+ time = (uint64_t)ioread32be(®s->tmr_etts[id].tmr_etts_l);
+ time |= ((uint64_t)ioread32be(®s->tmr_etts[id].tmr_etts_h)
+ << 32);
+
+ return time;
+}
+
+uint32_t fman_rtc_get_timer_ctrl(struct rtc_regs __iomem *regs)
+{
+ return ioread32be(®s->tmr_ctrl);
+}
+
+void fman_rtc_set_timer_ctrl(struct rtc_regs __iomem *regs, uint32_t val)
+{
+ iowrite32be(val, ®s->tmr_ctrl);
+}
+
+void fman_rtc_timers_soft_reset(struct rtc_regs __iomem *regs)
+{
+ fman_rtc_set_timer_ctrl(regs, FMAN_RTC_TMR_CTRL_TMSR);
+ udelay(10);
+ fman_rtc_set_timer_ctrl(regs, 0);
+}
+
+void fman_rtc_init(struct rtc_cfg *cfg, struct rtc_regs __iomem *regs,
+ int num_alarms, int num_fipers, int num_ext_triggers,
+ bool init_freq_comp, uint32_t freq_compensation,
+ uint32_t output_clock_divisor)
+{
+ uint32_t tmr_ctrl;
+ int i;
+
+ fman_rtc_timers_soft_reset(regs);
+
+ /* Set the source clock */
+ switch (cfg->src_clk) {
+ case FMAN_RTC_SOURCE_CLOCK_SYSTEM:
+ tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_MAC_CLK;
+ break;
+ case FMAN_RTC_SOURCE_CLOCK_OSCILATOR:
+ tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_OSC_CLK;
+ break;
+ default:
+ /* Use a clock from the External TMR reference clock. */
+ tmr_ctrl = FMAN_RTC_TMR_CTRL_CKSEL_EXT_CLK;
+ break;
+ }
+
+ /* whatever period the user picked, the timestamp will advance in '1'
+ * every time the period passed.
+ **/
+ tmr_ctrl |= ((1 << FMAN_RTC_TMR_CTRL_TCLK_PERIOD_SHIFT) &
+ FMAN_RTC_TMR_CTRL_TCLK_PERIOD_MASK);
+
+ if (cfg->invert_input_clk_phase)
+ tmr_ctrl |= FMAN_RTC_TMR_CTRL_CIPH;
+ if (cfg->invert_output_clk_phase)
+ tmr_ctrl |= FMAN_RTC_TMR_CTRL_COPH;
+
+ for (i = 0; i < num_alarms; i++) {
+ if (cfg->alarm_polarity[i] ==
+ FMAN_RTC_ALARM_POLARITY_ACTIVE_LOW)
+ tmr_ctrl |= (FMAN_RTC_TMR_CTRL_ALMP1 >> i);
+ }
+
+ for (i = 0; i < num_ext_triggers; i++)
+ if (cfg->trigger_polarity[i] ==
+ FMAN_RTC_TRIGGER_ON_FALLING_EDGE)
+ tmr_ctrl |= (FMAN_RTC_TMR_CTRL_ETEP1 << i);
+
+ if (!cfg->timer_slave_mode && cfg->bypass)
+ tmr_ctrl |= FMAN_RTC_TMR_CTRL_BYP;
+
+ fman_rtc_set_timer_ctrl(regs, tmr_ctrl);
+ if (init_freq_comp)
+ fman_rtc_set_frequency_compensation(regs, freq_compensation);
+
+ /* Clear TMR_ALARM registers */
+ for (i = 0; i < num_alarms; i++)
+ fman_rtc_set_timer_alarm(regs, i, 0xFFFFFFFFFFFFFFFFLL);
+
+ /* Clear TMR_TEVENT */
+ fman_rtc_ack_event(regs, FMAN_RTC_TMR_TEVENT_ALL);
+
+ /* Initialize TMR_TEMASK */
+ fman_rtc_set_interrupt_mask(regs, 0);
+
+ /* Clear TMR_FIPER registers */
+ for (i = 0; i < num_fipers; i++)
+ fman_rtc_set_timer_fiper(regs, i, 0xFFFFFFFF);
+
+ /* Initialize TMR_PRSC */
+ iowrite32be(output_clock_divisor, ®s->tmr_prsc);
+
+ /* Clear TMR_OFF */
+ fman_rtc_set_timer_offset(regs, 0);
+}
+
+bool fman_rtc_is_enabled(struct rtc_regs __iomem *regs)
+{
+ return (bool)(fman_rtc_get_timer_ctrl(regs) & FMAN_RTC_TMR_CTRL_TE);
+}
+
+void fman_rtc_enable(struct rtc_regs __iomem *regs, bool reset_clock)
+{
+ uint32_t tmr_ctrl = fman_rtc_get_timer_ctrl(regs);
+
+ /* TODO check that no timestamping MACs are working in this stage. */
+ if (reset_clock) {
+ fman_rtc_set_timer_ctrl(regs,
+ (tmr_ctrl | FMAN_RTC_TMR_CTRL_TMSR));
+
+ udelay(10);
+ /* Clear TMR_OFF */
+ fman_rtc_set_timer_offset(regs, 0);
+ }
+
+ fman_rtc_set_timer_ctrl(regs, (tmr_ctrl | FMAN_RTC_TMR_CTRL_TE));
+}
+
+void fman_rtc_disable(struct rtc_regs __iomem *regs)
+{
+ fman_rtc_set_timer_ctrl(regs,
+ (fman_rtc_get_timer_ctrl(regs) &
+ ~(FMAN_RTC_TMR_CTRL_TE)));
+}
+
+void fman_rtc_clear_periodic_pulse(struct rtc_regs __iomem *regs, int id)
+{
+ uint32_t tmp_reg;
+
+ if (id == 0)
+ tmp_reg = FMAN_RTC_TMR_TEVENT_PP1;
+ else
+ tmp_reg = FMAN_RTC_TMR_TEVENT_PP2;
+ fman_rtc_disable_interrupt(regs, tmp_reg);
+
+ tmp_reg = fman_rtc_get_timer_ctrl(regs);
+ if (tmp_reg & FMAN_RTC_TMR_CTRL_FS)
+ fman_rtc_set_timer_ctrl(regs, tmp_reg & ~FMAN_RTC_TMR_CTRL_FS);
+
+ fman_rtc_set_timer_fiper(regs, id, 0xFFFFFFFF);
+}
+
+void fman_rtc_clear_external_trigger(struct rtc_regs __iomem *regs, int id)
+{
+ uint32_t tmp_reg, tmp_ctrl;
+
+ if (id == 0)
+ tmp_reg = FMAN_RTC_TMR_TEVENT_ETS1;
+ else
+ tmp_reg = FMAN_RTC_TMR_TEVENT_ETS2;
+ fman_rtc_disable_interrupt(regs, tmp_reg);
+
+ if (id == 0)
+ tmp_reg = FMAN_RTC_TMR_CTRL_PP1L;
+ else
+ tmp_reg = FMAN_RTC_TMR_CTRL_PP2L;
+ tmp_ctrl = fman_rtc_get_timer_ctrl(regs);
+ if (tmp_ctrl & tmp_reg)
+ fman_rtc_set_timer_ctrl(regs, tmp_ctrl & ~tmp_reg);
+}
+
+void fman_rtc_set_alarm(struct rtc_regs __iomem *regs, int id, uint32_t val,
+ bool enable)
+{
+ uint32_t tmp_reg;
+
+ fman_rtc_set_timer_alarm(regs, id, val);
+ if (enable) {
+ if (id == 0)
+ tmp_reg = FMAN_RTC_TMR_TEVENT_ALM1;
+ else
+ tmp_reg = FMAN_RTC_TMR_TEVENT_ALM2;
+ fman_rtc_enable_interrupt(regs, tmp_reg);
+ }
+}
+
+void fman_rtc_set_periodic_pulse(struct rtc_regs __iomem *regs, int id,
+ uint32_t val, bool enable)
+{
+ uint32_t tmp_reg;
+
+ fman_rtc_set_timer_fiper(regs, id, val);
+ if (enable) {
+ if (id == 0)
+ tmp_reg = FMAN_RTC_TMR_TEVENT_PP1;
+ else
+ tmp_reg = FMAN_RTC_TMR_TEVENT_PP2;
+ fman_rtc_enable_interrupt(regs, tmp_reg);
+ }
+}
+
+void fman_rtc_set_ext_trigger(struct rtc_regs __iomem *regs, int id,
+ bool enable, bool use_pulse_as_input)
+{
+ uint32_t tmp_reg;
+
+ if (enable) {
+ if (id == 0)
+ tmp_reg = FMAN_RTC_TMR_TEVENT_ETS1;
+ else
+ tmp_reg = FMAN_RTC_TMR_TEVENT_ETS2;
+ fman_rtc_enable_interrupt(regs, tmp_reg);
+ }
+ if (use_pulse_as_input) {
+ if (id == 0)
+ tmp_reg = FMAN_RTC_TMR_CTRL_PP1L;
+ else
+ tmp_reg = FMAN_RTC_TMR_CTRL_PP2L;
+ fman_rtc_set_timer_ctrl(regs,
+ fman_rtc_get_timer_ctrl(regs) |
+ tmp_reg);
+ }
+}
--
2.3.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 7/7] soc/fman: Add the FMan SP FLIB
2015-03-05 5:45 [PATCH 0/7] Freescale DPAA FMan FLIB(s) Emil Medve
` (5 preceding siblings ...)
2015-03-05 5:45 ` [PATCH 6/7] soc/fman: Add the FMan RTC FLIB Emil Medve
@ 2015-03-05 5:45 ` Emil Medve
2015-03-05 12:32 ` [PATCH 0/7] Freescale DPAA FMan FLIB(s) Jamal Hadi Salim
7 siblings, 0 replies; 15+ messages in thread
From: Emil Medve @ 2015-03-05 5:45 UTC (permalink / raw)
To: linuxppc-dev, netdev, linux-kernel; +Cc: Igal Liberman
From: Igal Liberman <Igal.Liberman@freescale.com>
Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
---
drivers/soc/fsl/fman/Makefile | 1 +
drivers/soc/fsl/fman/sp/Makefile | 13 +++
drivers/soc/fsl/fman/sp/fman_sp.c | 204 ++++++++++++++++++++++++++++++++++++++
3 files changed, 218 insertions(+)
create mode 100644 drivers/soc/fsl/fman/sp/Makefile
create mode 100644 drivers/soc/fsl/fman/sp/fman_sp.c
diff --git a/drivers/soc/fsl/fman/Makefile b/drivers/soc/fsl/fman/Makefile
index f415188..4a854b3 100644
--- a/drivers/soc/fsl/fman/Makefile
+++ b/drivers/soc/fsl/fman/Makefile
@@ -14,5 +14,6 @@ obj-$(CONFIG_FSL_FMAN_PORT) += port/
obj-$(CONFIG_FSL_FMAN_MAC) += mac/
obj-$(CONFIG_FSL_FMAN_PCD) += pcd/
obj-$(CONFIG_FSL_FMAN_RTC) += rtc/
+obj-$(CONFIG_FSL_FMAN) += sp/
endif
diff --git a/drivers/soc/fsl/fman/sp/Makefile b/drivers/soc/fsl/fman/sp/Makefile
new file mode 100644
index 0000000..4655c11
--- /dev/null
+++ b/drivers/soc/fsl/fman/sp/Makefile
@@ -0,0 +1,13 @@
+ccflags-y += -DVERSION=\"\"
+
+ifeq ($(CONFIG_FSL_FMAN),y)
+
+FMAN = $(srctree)/drivers/soc/fsl/fman
+
+ccflags-y += -I$(FMAN)/flib
+
+obj-$(CONFIG_FSL_FMAN) += fsl_fman_sp.o
+
+fsl_fman_sp-objs := fman_sp.o
+
+endif
diff --git a/drivers/soc/fsl/fman/sp/fman_sp.c b/drivers/soc/fsl/fman/sp/fman_sp.c
new file mode 100644
index 0000000..e11413d
--- /dev/null
+++ b/drivers/soc/fsl/fman/sp/fman_sp.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2008-2015 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_fman_sp.h"
+
+uint32_t fman_vsp_get_statistics(struct fm_pcd_storage_profile_regs *regs,
+ uint16_t index)
+{
+ struct fm_pcd_storage_profile_regs *sp_regs;
+
+ sp_regs = ®s[index];
+ return ioread32be(&sp_regs->fm_sp_acnt);
+}
+
+void fman_vsp_set_statistics(struct fm_pcd_storage_profile_regs *regs,
+ uint16_t index, uint32_t value)
+{
+ struct fm_pcd_storage_profile_regs *sp_regs;
+
+ sp_regs = ®s[index];
+ iowrite32be(value, &sp_regs->fm_sp_acnt);
+}
+
+void fman_vsp_defconfig(struct fm_storage_profile_params *cfg)
+{
+ cfg->dma_swap_data = DEFAULT_FMAN_SP_DMA_SWAP_DATA;
+ cfg->int_context_cache_attr =
+ DEFAULT_FMAN_SP_DMA_INT_CONTEXT_CACHE_ATTR;
+ cfg->header_cache_attr = DEFAULT_FMAN_SP_DMA_HEADER_CACHE_ATTR;
+ cfg->scatter_gather_cache_attr =
+ DEFAULT_FMAN_SP_DMA_SCATTER_GATHER_CACHE_ATTR;
+ cfg->dma_write_optimize = DEFAULT_FMAN_SP_DMA_WRITE_OPTIMIZE;
+ cfg->no_scather_gather = DEFAULT_FMAN_SP_NO_SCATTER_GATHER;
+}
+
+static inline uint32_t calc_vec_dep(int max_pools, bool *pools,
+ struct fman_ext_pools *ext_buf_pools,
+ uint32_t mask)
+{
+ int i, j;
+ uint32_t vector = 0;
+
+ for (i = 0; i < max_pools; i++)
+ if (pools[i])
+ for (j = 0; j < ext_buf_pools->num_pools_used; j++)
+ if (i == ext_buf_pools->ext_buf_pool[j].id) {
+ vector |= mask >> j;
+ break;
+ }
+ return vector;
+}
+
+void fman_vsp_init(struct fm_pcd_storage_profile_regs *regs,
+ uint16_t index,
+ struct fm_storage_profile_params *fm_vsp_params,
+ int port_max_num_of_ext_pools, int bm_max_num_of_pools,
+ int max_num_of_pfc_priorities)
+{
+ int i = 0, j = 0;
+ struct fm_pcd_storage_profile_regs *sp_regs;
+ uint32_t tmp_reg, vector;
+ struct fman_ext_pools *ext_buf_pools = &fm_vsp_params->fm_ext_pools;
+ struct fman_buf_pool_depletion *buf_pool_depletion =
+ &fm_vsp_params->buf_pool_depletion;
+ struct fman_backup_bm_pools *backup_pools =
+ &fm_vsp_params->backup_pools;
+ struct fman_sp_int_context_data_copy *int_context_data_copy =
+ fm_vsp_params->int_context;
+ struct fman_sp_buf_margins *external_buffer_margins =
+ fm_vsp_params->buf_margins;
+ bool no_scather_gather = fm_vsp_params->no_scather_gather;
+ uint16_t liodn_offset = fm_vsp_params->liodn_offset;
+
+ sp_regs = ®s[index];
+
+ /* fill external buffers manager pool information register */
+ for (i = 0; i < ext_buf_pools->num_pools_used; i++) {
+ tmp_reg = FMAN_SP_EXT_BUF_POOL_VALID |
+ FMAN_SP_EXT_BUF_POOL_EN_COUNTER;
+ tmp_reg |= ((uint32_t)ext_buf_pools->ext_buf_pool[i].id <<
+ FMAN_SP_EXT_BUF_POOL_ID_SHIFT);
+ tmp_reg |= ext_buf_pools->ext_buf_pool[i].size;
+ /* functionality available only for some deriviatives
+ * (limited by config)
+ **/
+ for (j = 0; j < backup_pools->num_backup_pools; j++)
+ if (ext_buf_pools->ext_buf_pool[i].id ==
+ backup_pools->pool_ids[j]) {
+ tmp_reg |= FMAN_SP_EXT_BUF_POOL_BACKUP;
+ break;
+ }
+ iowrite32be(tmp_reg, &sp_regs->fm_sp_ebmpi[i]);
+ }
+
+ /* clear unused pools */
+ for (i = ext_buf_pools->num_pools_used;
+ i < port_max_num_of_ext_pools; i++)
+ iowrite32be(0, &sp_regs->fm_sp_ebmpi[i]);
+
+ /* fill pool depletion register */
+ tmp_reg = 0;
+ if (buf_pool_depletion->buf_pool_depletion_enabled &&
+ buf_pool_depletion->pools_grp_mode_enable) {
+ /* calculate vector for number of pools depletion */
+ vector =
+ calc_vec_dep(bm_max_num_of_pools,
+ buf_pool_depletion->pools_to_consider,
+ ext_buf_pools, 0x80000000);
+
+ /* configure num of pools and vector for number of pools mode */
+ tmp_reg |= (((uint32_t)buf_pool_depletion->num_pools - 1) <<
+ FMAN_SP_POOL_DEP_NUM_OF_POOLS_SHIFT);
+ tmp_reg |= vector;
+ }
+
+ if (buf_pool_depletion->buf_pool_depletion_enabled &&
+ buf_pool_depletion->single_pool_mode_enable) {
+ /* calculate vector for number of pools depletion */
+ vector =
+ calc_vec_dep(bm_max_num_of_pools,
+ buf_pool_depletion->
+ pools_to_consider_for_single_mode,
+ ext_buf_pools, 0x00000080);
+
+ /* configure num of pools and vector for number of pools mode */
+ tmp_reg |= vector;
+ }
+
+ /* fill QbbPEV */
+ if (buf_pool_depletion->buf_pool_depletion_enabled) {
+ vector = 0;
+ for (i = 0; i < max_num_of_pfc_priorities; i++)
+ if (buf_pool_depletion->pfc_priorities_en[i])
+ vector |= 0x00000100 << i;
+ tmp_reg |= vector;
+ }
+ iowrite32be(tmp_reg, &sp_regs->fm_sp_mpd);
+
+ /* fill dma attributes register */
+ tmp_reg = 0;
+ tmp_reg |= (uint32_t)fm_vsp_params->dma_swap_data <<
+ FMAN_SP_DMA_ATTR_SWP_SHIFT;
+ tmp_reg |= (uint32_t)fm_vsp_params->int_context_cache_attr <<
+ FMAN_SP_DMA_ATTR_IC_CACHE_SHIFT;
+ tmp_reg |= (uint32_t)fm_vsp_params->header_cache_attr <<
+ FMAN_SP_DMA_ATTR_HDR_CACHE_SHIFT;
+ tmp_reg |= (uint32_t)fm_vsp_params->scatter_gather_cache_attr <<
+ FMAN_SP_DMA_ATTR_SG_CACHE_SHIFT;
+ if (fm_vsp_params->dma_write_optimize)
+ tmp_reg |= FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE;
+ iowrite32be(tmp_reg, &sp_regs->fm_sp_da);
+
+ /* IC parameters - fill internal context parameters register */
+ tmp_reg = 0;
+ tmp_reg |= (((uint32_t)int_context_data_copy->ext_buf_offset /
+ OFFSET_UNITS) << FMAN_SP_IC_TO_EXT_SHIFT);
+ tmp_reg |= (((uint32_t)int_context_data_copy->int_context_offset /
+ OFFSET_UNITS) << FMAN_SP_IC_FROM_INT_SHIFT);
+ tmp_reg |= (((uint32_t)int_context_data_copy->size / OFFSET_UNITS) <<
+ FMAN_SP_IC_SIZE_SHIFT);
+ iowrite32be(tmp_reg, &sp_regs->fm_sp_icp);
+
+ /* buffer margins - fill external buffer margins register */
+ tmp_reg = 0;
+ tmp_reg |= (((uint32_t)external_buffer_margins->start_margins) <<
+ FMAN_SP_EXT_BUF_MARG_START_SHIFT);
+ tmp_reg |= (((uint32_t)external_buffer_margins->end_margins) <<
+ FMAN_SP_EXT_BUF_MARG_END_SHIFT);
+ if (no_scather_gather)
+ tmp_reg |= FMAN_SP_SG_DISABLE;
+ iowrite32be(tmp_reg, &sp_regs->fm_sp_ebm);
+
+ /* buffer margins - fill spliodn register */
+ iowrite32be(liodn_offset, &sp_regs->fm_sp_spliodn);
+}
--
2.3.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 0/7] Freescale DPAA FMan FLIB(s)
2015-03-05 5:45 [PATCH 0/7] Freescale DPAA FMan FLIB(s) Emil Medve
` (6 preceding siblings ...)
2015-03-05 5:45 ` [PATCH 7/7] soc/fman: Add the FMan SP FLIB Emil Medve
@ 2015-03-05 12:32 ` Jamal Hadi Salim
2015-03-05 13:48 ` Emil Medve
7 siblings, 1 reply; 15+ messages in thread
From: Jamal Hadi Salim @ 2015-03-05 12:32 UTC (permalink / raw)
To: Emil Medve, linuxppc-dev, netdev, linux-kernel; +Cc: Igal Liberman
On 03/05/15 00:45, Emil Medve wrote:
> From: Igal Liberman <Igal.Liberman@freescale.com>
>
> The Freescale Data Path Acceleration Architecture (DPAA) is a set of
> hardware components on specific QorIQ P and T series multicore processors.
> This architecture provides the infrastructure to support simplified
> sharing of networking interfaces and accelerators by multiple CPU cores,
> and the accelerators themselves.
>
> One of the DPAA accelerators is the Frame Manager (FMan), which
> combines the Ethernet network interfaces with packet distribution
> logic to provide intelligent distribution and queuing decisions for
> incoming traffic at line rate.
>
> This patch presents the FMan Foundation Libraries (FLIB) headers.
> The FMan FLIB suite adds basic support for the DPAA FMan hardware register access.
> The FMan FLIB suite is used in Freescale's SDK Releases.
>
Is this intended to merely enable your sdk? How are you planning to
add support for your classifiers, queue schedulers etc? Is that a patch
on top of this or it is something that sits on user space?
cheers,
jamal
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 0/7] Freescale DPAA FMan FLIB(s)
2015-03-05 12:32 ` [PATCH 0/7] Freescale DPAA FMan FLIB(s) Jamal Hadi Salim
@ 2015-03-05 13:48 ` Emil Medve
2015-03-05 14:35 ` Jamal Hadi Salim
0 siblings, 1 reply; 15+ messages in thread
From: Emil Medve @ 2015-03-05 13:48 UTC (permalink / raw)
To: Jamal Hadi Salim, linuxppc-dev, netdev, linux-kernel; +Cc: Igal Liberman
Hello Jamal,
On 03/05/2015 06:32 AM, Jamal Hadi Salim wrote:
> On 03/05/15 00:45, Emil Medve wrote:
>> From: Igal Liberman <Igal.Liberman@freescale.com>
>>
>> The Freescale Data Path Acceleration Architecture (DPAA) is a set of
>> hardware components on specific QorIQ P and T series multicore
>> processors.
>> This architecture provides the infrastructure to support simplified
>> sharing of networking interfaces and accelerators by multiple CPU cores,
>> and the accelerators themselves.
>>
>> One of the DPAA accelerators is the Frame Manager (FMan), which
>> combines the Ethernet network interfaces with packet distribution
>> logic to provide intelligent distribution and queuing decisions for
>> incoming traffic at line rate.
>>
>> This patch presents the FMan Foundation Libraries (FLIB) headers.
>> The FMan FLIB suite adds basic support for the DPAA FMan hardware
>> register access.
>> The FMan FLIB suite is used in Freescale's SDK Releases.
>>
>
> Is this intended to merely enable your sdk?
The intent is to upstream the entire suite of the DPAA drivers. All the
drivers are still WIP, but B/QMan have been already presented to the
upstream community and this is the first attempt to publish (some low
level code of) the FMan driver. As we go through our internal checklist
and in the same time address community feedback we'll soon get the
drivers to be acceptable for the upstream trees
The first version of the actual Ethernet driver will follow imminently
SDK enablement is a side-effect
> How are you planning to
> add support for your classifiers, queue schedulers etc?
Yes
> Is that a patch
> on top of this or it is something that sits on user space?
Both. Full DPAA/Ethernet enablement will be present in the kernel. We
also have support for user-space based approach. I'm unsure where/when
we might publish that. Of course the SDK is always a place you can turn
to for all the code we have (in whatever state it might be)
Cheers.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/7] Freescale DPAA FMan FLIB(s)
2015-03-05 13:48 ` Emil Medve
@ 2015-03-05 14:35 ` Jamal Hadi Salim
2015-03-05 15:04 ` Emil Medve
0 siblings, 1 reply; 15+ messages in thread
From: Jamal Hadi Salim @ 2015-03-05 14:35 UTC (permalink / raw)
To: Emil Medve, linuxppc-dev, netdev, linux-kernel; +Cc: Igal Liberman
Hi Emil,
On 03/05/15 08:48, Emil Medve wrote:
> The intent is to upstream the entire suite of the DPAA drivers. All the
> drivers are still WIP, but B/QMan have been already presented to the
> upstream community and this is the first attempt to publish (some low
> level code of) the FMan driver. As we go through our internal checklist
> and in the same time address community feedback we'll soon get the
> drivers to be acceptable for the upstream trees
>
> The first version of the actual Ethernet driver will follow imminently
>
> SDK enablement is a side-effect
>
Meaning? Let me ask the question differently:
Do i need your sdk to use the features exposed or can i use something
like tc to set up the deficit rr or wred or the exposed classifiers
and associated actions?
Would your sdk (via user space direct programming) benefit because you
have pushed these pieces into the kernel?
>> How are you planning to
>> add support for your classifiers, queue schedulers etc?
>
> Yes
>
Yes as in these will be available via linux kernel or via your sdk?
>> Is that a patch
>> on top of this or it is something that sits on user space?
>
> Both. Full DPAA/Ethernet enablement will be present in the kernel. We
> also have support for user-space based approach. I'm unsure where/when
> we might publish that. Of course the SDK is always a place you can turn
> to for all the code we have (in whatever state it might be)
>
the sdk is open source?
cheers,
jamal
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/7] Freescale DPAA FMan FLIB(s)
2015-03-05 14:35 ` Jamal Hadi Salim
@ 2015-03-05 15:04 ` Emil Medve
2015-03-06 15:09 ` Jamal Hadi Salim
0 siblings, 1 reply; 15+ messages in thread
From: Emil Medve @ 2015-03-05 15:04 UTC (permalink / raw)
To: Jamal Hadi Salim, linuxppc-dev, netdev, linux-kernel; +Cc: Igal Liberman
Hello Jamal,
On 03/05/2015 08:35 AM, Jamal Hadi Salim wrote:
> Hi Emil,
>
> On 03/05/15 08:48, Emil Medve wrote:
>
>> The intent is to upstream the entire suite of the DPAA drivers. All the
>> drivers are still WIP, but B/QMan have been already presented to the
>> upstream community and this is the first attempt to publish (some low
>> level code of) the FMan driver. As we go through our internal checklist
>> and in the same time address community feedback we'll soon get the
>> drivers to be acceptable for the upstream trees
>>
>> The first version of the actual Ethernet driver will follow imminently
>>
>> SDK enablement is a side-effect
>
> Meaning? Let me ask the question differently:
> Do i need your sdk to use the features exposed
No. All the kernel drivers/code we want to upstream is meant to stand on
its own and be used the "normal" Linux/Unix way
> or can i use something
> like tc to set up the deficit rr or wred or the exposed classifiers
> and associated actions?
The SDK doesn't currently support the enablement of any HW QoS features
via standard Linux user-space tools. The SDK contains some FSL tools for
that. As a time moving target we intend to support lots of the DPAA
features via standard kernel/user-space means: ethtool, iptables,
iproute2, etc.
> Would your sdk (via user space direct programming) benefit because you
> have pushed these pieces into the kernel?
Not specifically because of the kernel drivers. In support for the
user-space DPAA the kernel will have some UIO/VFIO drivers to allow the
user-space to "mmap" these devices (portals, ports, MAC(s), etc.). The
intent is to use the same driver sources for the kernel- and user-space
drivers
>>> How are you planning to
>>> add support for your classifiers, queue schedulers etc?
>>
>> Yes
>
> Yes as in these will be available via linux kernel or via your sdk?
As in these will be available via familiar kernel-/user-space tools
>>> Is that a patch
>>> on top of this or it is something that sits on user space?
>>
>> Both. Full DPAA/Ethernet enablement will be present in the kernel. We
>> also have support for user-space based approach. I'm unsure where/when
>> we might publish that. Of course the SDK is always a place you can turn
>> to for all the code we have (in whatever state it might be)
>
> the sdk is open source?
I'm uncertain about *all* the licenses included, but you can look into
it and download the SDK via git.freescale.com and/or
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=SDKLINUX
Cheers,
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/7] Freescale DPAA FMan FLIB(s)
2015-03-05 15:04 ` Emil Medve
@ 2015-03-06 15:09 ` Jamal Hadi Salim
0 siblings, 0 replies; 15+ messages in thread
From: Jamal Hadi Salim @ 2015-03-06 15:09 UTC (permalink / raw)
To: Emil Medve, linuxppc-dev, netdev, linux-kernel; +Cc: Igal Liberman
Hi Emil,
On 03/05/15 10:04, Emil Medve wrote:
> Hello Jamal,
>
>
> On 03/05/2015 08:35 AM, Jamal Hadi Salim wrote:
>> Hi Emil,
>>
>
> No. All the kernel drivers/code we want to upstream is meant to stand on
> its own and be used the "normal" Linux/Unix way
>
Ok, thanks - that was my only concern.
Note there is a lot of offload efforts going on in Linux right now.
Take a look at the proceedings from netdev01. You should take advantage
of that to shape the direction of your patches.
I have suffered at the hands of the sdk for this processor in the past;
it is just a bad idea to keep these SDKs around when Linux can express
the features sufficiently.
Note: The main thing i'd be interested in is when you get to offloading
the classifier/scheduler etc. I know you are focussing on just the
ethernet level at the moment,
cheers,
jamal
^ permalink raw reply [flat|nested] 15+ messages in thread