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From: Christophe Leroy <christophe.leroy@csgroup.eu>
To: Herve Codina <herve.codina@bootlin.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,
	Mark Brown <broonie@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH v2 12/36] soc: fsl: cpm1: tsa: Isolate specific CPM1 part from tsa_serial_{dis}connect()
Date: Fri, 23 Aug 2024 10:07:47 +0200	[thread overview]
Message-ID: <551f4c3d-a57f-47ea-a477-c502fbd61251@csgroup.eu> (raw)
In-Reply-To: <20240808071132.149251-13-herve.codina@bootlin.com>



Le 08/08/2024 à 09:11, Herve Codina a écrit :
> Current code handles the CPM1 version of TSA. Connecting and
> disconnecting the SCC to/from the TSA consists in handling SICR register
> which is CPM1 specific. The connection and disconnection operation in
> the QUICC Engine (QE) version are slightly different.
> 
> In order to prepare the support for the QE version, clearly identify
> SICR register as specific to CPM1 and isolate its handling done in
> connect and disconnect functions.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>

Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>


> ---
>   drivers/soc/fsl/qe/tsa.c | 103 ++++++++++++++++-----------------------
>   1 file changed, 43 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c
> index 239b71187e07..48a176cece86 100644
> --- a/drivers/soc/fsl/qe/tsa.c
> +++ b/drivers/soc/fsl/qe/tsa.c
> @@ -67,34 +67,34 @@
>   #define   TSA_CPM1_SIGMR_RDM_DYN_TDMAB		FIELD_PREP_CONST(TSA_CPM1_SIGMR_RDM_MASK, 0x3)
>   
>   /* SI clock route register (32 bits) */
> -#define TSA_SICR	0x0C
> -#define   TSA_SICR_SCC2_MASK		GENMASK(15, 8)
> -#define   TSA_SICR_SCC2(x)		FIELD_PREP(TSA_SICR_SCC2_MASK, x)
> -#define   TSA_SICR_SCC3_MASK		GENMASK(23, 16)
> -#define   TSA_SICR_SCC3(x)		FIELD_PREP(TSA_SICR_SCC3_MASK, x)
> -#define   TSA_SICR_SCC4_MASK		GENMASK(31, 24)
> -#define   TSA_SICR_SCC4(x)		FIELD_PREP(TSA_SICR_SCC4_MASK, x)
> -#define     TSA_SICR_SCC_MASK		GENMASK(7, 0)
> -#define     TSA_SICR_SCC_GRX		BIT(7)
> -#define     TSA_SICR_SCC_SCX_TSA	BIT(6)
> -#define     TSA_SICR_SCC_RXCS_MASK	GENMASK(5, 3)
> -#define       TSA_SICR_SCC_RXCS_BRG1	FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x0)
> -#define       TSA_SICR_SCC_RXCS_BRG2	FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x1)
> -#define       TSA_SICR_SCC_RXCS_BRG3	FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x2)
> -#define       TSA_SICR_SCC_RXCS_BRG4	FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x3)
> -#define       TSA_SICR_SCC_RXCS_CLK15	FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x4)
> -#define       TSA_SICR_SCC_RXCS_CLK26	FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x5)
> -#define       TSA_SICR_SCC_RXCS_CLK37	FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x6)
> -#define       TSA_SICR_SCC_RXCS_CLK48	FIELD_PREP_CONST(TSA_SICR_SCC_RXCS_MASK, 0x7)
> -#define     TSA_SICR_SCC_TXCS_MASK	GENMASK(2, 0)
> -#define       TSA_SICR_SCC_TXCS_BRG1	FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x0)
> -#define       TSA_SICR_SCC_TXCS_BRG2	FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x1)
> -#define       TSA_SICR_SCC_TXCS_BRG3	FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x2)
> -#define       TSA_SICR_SCC_TXCS_BRG4	FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x3)
> -#define       TSA_SICR_SCC_TXCS_CLK15	FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x4)
> -#define       TSA_SICR_SCC_TXCS_CLK26	FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x5)
> -#define       TSA_SICR_SCC_TXCS_CLK37	FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x6)
> -#define       TSA_SICR_SCC_TXCS_CLK48	FIELD_PREP_CONST(TSA_SICR_SCC_TXCS_MASK, 0x7)
> +#define TSA_CPM1_SICR	0x0C
> +#define   TSA_CPM1_SICR_SCC2_MASK		GENMASK(15, 8)
> +#define   TSA_CPM1_SICR_SCC2(x)			FIELD_PREP(TSA_CPM1_SICR_SCC2_MASK, x)
> +#define   TSA_CPM1_SICR_SCC3_MASK		GENMASK(23, 16)
> +#define   TSA_CPM1_SICR_SCC3(x)			FIELD_PREP(TSA_CPM1_SICR_SCC3_MASK, x)
> +#define   TSA_CPM1_SICR_SCC4_MASK		GENMASK(31, 24)
> +#define   TSA_CPM1_SICR_SCC4(x)			FIELD_PREP(TSA_CPM1_SICR_SCC4_MASK, x)
> +#define     TSA_CPM1_SICR_SCC_MASK		GENMASK(7, 0)
> +#define     TSA_CPM1_SICR_SCC_GRX		BIT(7)
> +#define     TSA_CPM1_SICR_SCC_SCX_TSA		BIT(6)
> +#define     TSA_CPM1_SICR_SCC_RXCS_MASK		GENMASK(5, 3)
> +#define       TSA_CPM1_SICR_SCC_RXCS_BRG1	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_RXCS_MASK, 0x0)
> +#define       TSA_CPM1_SICR_SCC_RXCS_BRG2	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_RXCS_MASK, 0x1)
> +#define       TSA_CPM1_SICR_SCC_RXCS_BRG3	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_RXCS_MASK, 0x2)
> +#define       TSA_CPM1_SICR_SCC_RXCS_BRG4	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_RXCS_MASK, 0x3)
> +#define       TSA_CPM1_SICR_SCC_RXCS_CLK15	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_RXCS_MASK, 0x4)
> +#define       TSA_CPM1_SICR_SCC_RXCS_CLK26	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_RXCS_MASK, 0x5)
> +#define       TSA_CPM1_SICR_SCC_RXCS_CLK37	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_RXCS_MASK, 0x6)
> +#define       TSA_CPM1_SICR_SCC_RXCS_CLK48	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_RXCS_MASK, 0x7)
> +#define     TSA_CPM1_SICR_SCC_TXCS_MASK		GENMASK(2, 0)
> +#define       TSA_CPM1_SICR_SCC_TXCS_BRG1	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_TXCS_MASK, 0x0)
> +#define       TSA_CPM1_SICR_SCC_TXCS_BRG2	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_TXCS_MASK, 0x1)
> +#define       TSA_CPM1_SICR_SCC_TXCS_BRG3	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_TXCS_MASK, 0x2)
> +#define       TSA_CPM1_SICR_SCC_TXCS_BRG4	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_TXCS_MASK, 0x3)
> +#define       TSA_CPM1_SICR_SCC_TXCS_CLK15	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_TXCS_MASK, 0x4)
> +#define       TSA_CPM1_SICR_SCC_TXCS_CLK26	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_TXCS_MASK, 0x5)
> +#define       TSA_CPM1_SICR_SCC_TXCS_CLK37	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_TXCS_MASK, 0x6)
> +#define       TSA_CPM1_SICR_SCC_TXCS_CLK48	FIELD_PREP_CONST(TSA_CPM1_SICR_SCC_TXCS_MASK, 0x7)
>   
>   struct tsa_entries_area {
>   	void __iomem *entries_start;
> @@ -159,7 +159,7 @@ static inline void tsa_clrsetbits32(void __iomem *addr, u32 clr, u32 set)
>   	tsa_write32(addr, (tsa_read32(addr) & ~clr) | set);
>   }
>   
> -int tsa_serial_connect(struct tsa_serial *tsa_serial)
> +static int tsa_cpm1_serial_connect(struct tsa_serial *tsa_serial, bool connect)
>   {
>   	struct tsa *tsa = tsa_serial_get_tsa(tsa_serial);
>   	unsigned long flags;
> @@ -168,16 +168,16 @@ int tsa_serial_connect(struct tsa_serial *tsa_serial)
>   
>   	switch (tsa_serial->id) {
>   	case FSL_CPM_TSA_SCC2:
> -		clear = TSA_SICR_SCC2(TSA_SICR_SCC_MASK);
> -		set = TSA_SICR_SCC2(TSA_SICR_SCC_SCX_TSA);
> +		clear = TSA_CPM1_SICR_SCC2(TSA_CPM1_SICR_SCC_MASK);
> +		set = TSA_CPM1_SICR_SCC2(TSA_CPM1_SICR_SCC_SCX_TSA);
>   		break;
>   	case FSL_CPM_TSA_SCC3:
> -		clear = TSA_SICR_SCC3(TSA_SICR_SCC_MASK);
> -		set = TSA_SICR_SCC3(TSA_SICR_SCC_SCX_TSA);
> +		clear = TSA_CPM1_SICR_SCC3(TSA_CPM1_SICR_SCC_MASK);
> +		set = TSA_CPM1_SICR_SCC3(TSA_CPM1_SICR_SCC_SCX_TSA);
>   		break;
>   	case FSL_CPM_TSA_SCC4:
> -		clear = TSA_SICR_SCC4(TSA_SICR_SCC_MASK);
> -		set = TSA_SICR_SCC4(TSA_SICR_SCC_SCX_TSA);
> +		clear = TSA_CPM1_SICR_SCC4(TSA_CPM1_SICR_SCC_MASK);
> +		set = TSA_CPM1_SICR_SCC4(TSA_CPM1_SICR_SCC_SCX_TSA);
>   		break;
>   	default:
>   		dev_err(tsa->dev, "Unsupported serial id %u\n", tsa_serial->id);
> @@ -185,39 +185,22 @@ int tsa_serial_connect(struct tsa_serial *tsa_serial)
>   	}
>   
>   	spin_lock_irqsave(&tsa->lock, flags);
> -	tsa_clrsetbits32(tsa->si_regs + TSA_SICR, clear, set);
> +	tsa_clrsetbits32(tsa->si_regs + TSA_CPM1_SICR, clear,
> +			 connect ? set : 0);
>   	spin_unlock_irqrestore(&tsa->lock, flags);
>   
>   	return 0;
>   }
> +
> +int tsa_serial_connect(struct tsa_serial *tsa_serial)
> +{
> +	return tsa_cpm1_serial_connect(tsa_serial, true);
> +}
>   EXPORT_SYMBOL(tsa_serial_connect);
>   
>   int tsa_serial_disconnect(struct tsa_serial *tsa_serial)
>   {
> -	struct tsa *tsa = tsa_serial_get_tsa(tsa_serial);
> -	unsigned long flags;
> -	u32 clear;
> -
> -	switch (tsa_serial->id) {
> -	case FSL_CPM_TSA_SCC2:
> -		clear = TSA_SICR_SCC2(TSA_SICR_SCC_MASK);
> -		break;
> -	case FSL_CPM_TSA_SCC3:
> -		clear = TSA_SICR_SCC3(TSA_SICR_SCC_MASK);
> -		break;
> -	case FSL_CPM_TSA_SCC4:
> -		clear = TSA_SICR_SCC4(TSA_SICR_SCC_MASK);
> -		break;
> -	default:
> -		dev_err(tsa->dev, "Unsupported serial id %u\n", tsa_serial->id);
> -		return -EINVAL;
> -	}
> -
> -	spin_lock_irqsave(&tsa->lock, flags);
> -	tsa_clrsetbits32(tsa->si_regs + TSA_SICR, clear, 0);
> -	spin_unlock_irqrestore(&tsa->lock, flags);
> -
> -	return 0;
> +	return tsa_cpm1_serial_connect(tsa_serial, false);
>   }
>   EXPORT_SYMBOL(tsa_serial_disconnect);
>   


  reply	other threads:[~2024-08-23  8:07 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-08  7:10 [PATCH v2 00/36] soc: fsl: Add support for QUICC Engine TSA and QMC Herve Codina
2024-08-08  7:10 ` [PATCH v2 01/36] soc: fsl: cpm1: qmc: Update TRNSYNC only in transparent mode Herve Codina
2024-08-23  8:03   ` Christophe Leroy
2024-08-08  7:10 ` [PATCH v2 02/36] soc: fsl: cpm1: qmc: Enable TRNSYNC only when needed Herve Codina
2024-08-23  8:03   ` Christophe Leroy
2024-08-08  7:10 ` [PATCH v2 03/36] soc: fsl: cpm1: tsa: Fix tsa_write8() Herve Codina
2024-08-23  8:04   ` Christophe Leroy
2024-08-08  7:10 ` [PATCH v2 04/36] soc: fsl: cpm1: tsa: Use BIT(), GENMASK() and FIELD_PREP() macros Herve Codina
2024-08-23  8:04   ` Christophe Leroy
2024-08-08  7:10 ` [PATCH v2 05/36] soc: fsl: cpm1: tsa: Fix blank line and spaces Herve Codina
2024-08-23  8:04   ` Christophe Leroy
2024-08-08  7:10 ` [PATCH v2 06/36] soc: fsl: cpm1: tsa: Add missing spinlock comment Herve Codina
2024-08-23  8:05   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 07/36] dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine (QE) TSA controller Herve Codina
2024-08-13 19:01   ` Rob Herring (Arm)
2024-08-23  8:05   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 08/36] soc: fsl: cpm1: tsa: Remove unused registers offset definition Herve Codina
2024-08-23  8:05   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 09/36] soc: fsl: cpm1: tsa: Use ARRAY_SIZE() instead of hardcoded integer values Herve Codina
2024-08-23  8:05   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 10/36] soc: fsl: cpm1: tsa: Make SIRAM entries specific to CPM1 Herve Codina
2024-08-23  8:06   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 11/36] soc: fsl: cpm1: tsa: Introduce tsa_setup() and its CPM1 compatible version Herve Codina
2024-08-23  8:06   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 12/36] soc: fsl: cpm1: tsa: Isolate specific CPM1 part from tsa_serial_{dis}connect() Herve Codina
2024-08-23  8:07   ` Christophe Leroy [this message]
2024-08-08  7:11 ` [PATCH v2 13/36] soc: fsl: cpm1: tsa: Introduce tsa_version Herve Codina
2024-08-23  8:08   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 14/36] soc: fsl: cpm1: tsa: Add support for QUICC Engine (QE) implementation Herve Codina
2024-08-23  8:08   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 15/36] MAINTAINERS: Add QE files related to the Freescale TSA controller Herve Codina
2024-08-23  8:08   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 16/36] soc: fsl: cpm1: tsa: Introduce tsa_serial_get_num() Herve Codina
2024-08-23  8:09   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 17/36] soc: fsl: cpm1: qmc: Rename QMC_TSA_MASK Herve Codina
2024-08-23  8:09   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 18/36] soc: fsl: cpm1: qmc: Use BIT(), GENMASK() and FIELD_PREP() macros Herve Codina
2024-08-23  8:07   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 19/36] soc: fsl: cpm1: qmc: Fix blank line and spaces Herve Codina
2024-08-23  8:07   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 20/36] soc: fsl: cpm1: qmc: Remove unneeded parenthesis Herve Codina
2024-08-23  8:09   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 21/36] soc: fsl: cpm1: qmc: Fix 'transmiter' typo Herve Codina
2024-08-23  8:10   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 22/36] soc: fsl: cpm1: qmc: Add missing spinlock comment Herve Codina
2024-08-23  8:10   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 23/36] dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine (QE) QMC controller Herve Codina
2024-08-13 19:12   ` Rob Herring
2024-08-23  8:11   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 24/36] soc: fsl: cpm1: qmc: Introduce qmc_data structure Herve Codina
2024-08-23  8:11   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 25/36] soc: fsl: cpm1: qmc: Re-order probe() operations Herve Codina
2024-08-23  8:11   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 26/36] soc: fsl: cpm1: qmc: Introduce qmc_init_resource() and its CPM1 version Herve Codina
2024-08-23  8:11   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 27/36] soc: fsl: cpm1: qmc: Introduce qmc_{init,exit}_xcc() and their " Herve Codina
2024-08-23  8:12   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 28/36] soc: fsl: cpm1: qmc: Rename qmc_chan_command() Herve Codina
2024-08-23  8:12   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 29/36] soc: fsl: cpm1: qmc: Handle RPACK initialization Herve Codina
2024-08-23  8:13   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 30/36] soc: fsl: cpm1: qmc: Rename SCC_GSMRL_MODE_QMC Herve Codina
2024-08-23  8:13   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 31/36] soc: fsl: cpm1: qmc: Introduce qmc_version Herve Codina
2024-08-23  8:13   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 32/36] soc: fsl: qe: Add resource-managed muram allocators Herve Codina
2024-08-23  8:13   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 33/36] soc: fsl: qe: Add missing PUSHSCHED command Herve Codina
2024-08-23  8:14   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 34/36] soc: fsl: cpm1: qmc: Add support for QUICC Engine (QE) implementation Herve Codina
2024-08-23  8:14   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 35/36] soc: fsl: cpm1: qmc: Handle QUICC Engine (QE) soft-qmc firmware Herve Codina
2024-08-23  8:14   ` Christophe Leroy
2024-08-08  7:11 ` [PATCH v2 36/36] MAINTAINERS: Add QE files related to the Freescale QMC controller Herve Codina
2024-08-23  8:15   ` Christophe Leroy
2024-09-03  8:44 ` [PATCH v2 00/36] soc: fsl: Add support for QUICC Engine TSA and QMC Christophe Leroy

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