From: Laurentiu Tudor <b10716@freescale.com>
To: linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Cc: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>,
Scott Wood <scottwood@freescale.com>, <kvm-ppc@vger.kernel.org>
Subject: [PATCH] powerpc/e6500: add TMCFG0 register definition
Date: Wed, 23 Sep 2015 18:06:22 +0300 [thread overview]
Message-ID: <5602BFEE.7060708@freescale.com> (raw)
The register is not currently used in the base kernel
but will be in a forthcoming kvm patch.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
---
arch/powerpc/include/asm/reg_booke.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 16547ef..2fef74b 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -742,6 +742,12 @@
#define MMUBE1_VBE4 0x00000002
#define MMUBE1_VBE5 0x00000001
+#define TMRN_TMCFG0 16 /* Thread Management Configuration Register 0 */
+#define TMRN_TMCFG0_NPRIBITS 0x003f0000 /* Bits of thread priority */
+#define TMRN_TMCFG0_NPRIBITS_SHIFT 16
+#define TMRN_TMCFG0_NATHRD 0x00003f00 /* Number of active threads */
+#define TMRN_TMCFG0_NATHRD_SHIFT 8
+#define TMRN_TMCFG0_NTHRD 0x0000003f /* Number of threads */
#define TMRN_IMSR0 0x120 /* Initial MSR Register 0 (e6500) */
#define TMRN_IMSR1 0x121 /* Initial MSR Register 1 (e6500) */
#define TMRN_INIA0 0x140 /* Next Instruction Address Register 0 */
--
1.8.3.1
next reply other threads:[~2015-09-23 15:39 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-23 15:06 Laurentiu Tudor [this message]
2015-09-24 22:18 ` [PATCH] powerpc/e6500: add TMCFG0 register definition Scott Wood
2015-10-15 5:29 ` Paul Mackerras
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