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From: Laurentiu Tudor <b10716@freescale.com>
To: Scott Wood <scottwood@freescale.com>, <linuxppc-dev@lists.ozlabs.org>
Cc: Tiejun Chen <tiejun.chen@intel.com>, <kexec@lists.infradead.org>
Subject: Re: [PATCH v2 05/18] powerpc/85xx: Load all early TLB entries at once
Date: Wed, 7 Oct 2015 17:00:24 +0300	[thread overview]
Message-ID: <56152578.6070802@freescale.com> (raw)
In-Reply-To: <1444189702-17241-6-git-send-email-scottwood@freescale.com>

On 10/07/2015 06:48 AM, Scott Wood wrote:
> Use an AS=1 trampoline TLB entry to allow all normal TLB1 entries to
> be loaded at once.  This avoids the need to keep the translation that
> code is executing from in the same TLB entry in the final TLB
> configuration as during early boot, which in turn is helpful for
> relocatable kernels (e.g. kdump) where the kernel is not running from
> what would be the first TLB entry.
> 
> On e6500, we limit map_mem_in_cams() to the primary hwthread of a
> core (the boot cpu is always considered primary, as a kdump kernel
> can be entered on any cpu).  Each TLB only needs to be set up once,
> and when we do, we don't want another thread to be running when we
> create a temporary trampoline TLB1 entry.
> 
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
>  arch/powerpc/kernel/setup_64.c   |  8 +++++
>  arch/powerpc/mm/fsl_booke_mmu.c  | 15 ++++++++--
>  arch/powerpc/mm/mmu_decl.h       |  1 +
>  arch/powerpc/mm/tlb_nohash.c     | 19 +++++++++++-
>  arch/powerpc/mm/tlb_nohash_low.S | 63 ++++++++++++++++++++++++++++++++++++++++
>  5 files changed, 102 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
> index bdcbb71..505ec2c 100644
> --- a/arch/powerpc/kernel/setup_64.c
> +++ b/arch/powerpc/kernel/setup_64.c
> @@ -108,6 +108,14 @@ static void setup_tlb_core_data(void)
>  	for_each_possible_cpu(cpu) {
>  		int first = cpu_first_thread_sibling(cpu);
>  
> +		/*
> +		 * If we boot via kdump on a non-primary thread,
> +		 * make sure we point at the thread that actually
> +		 * set up this TLB.
> +		 */
> +		if (cpu_first_thread_sibling(boot_cpuid) == first)
> +			first = boot_cpuid;
> +
>  		paca[cpu].tcd_ptr = &paca[first].tcd;
>  
>  		/*
> diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
> index 354ba3c..36d3c55 100644
> --- a/arch/powerpc/mm/fsl_booke_mmu.c
> +++ b/arch/powerpc/mm/fsl_booke_mmu.c
> @@ -105,8 +105,9 @@ unsigned long p_mapped_by_tlbcam(phys_addr_t pa)
>   * an unsigned long (for example, 32-bit implementations cannot support a 4GB
>   * size).
>   */
> -static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
> -		unsigned long size, unsigned long flags, unsigned int pid)
> +static void preptlbcam(int index, unsigned long virt, phys_addr_t phys,
> +		       unsigned long size, unsigned long flags,
> +		       unsigned int pid)
>  {
>  	unsigned int tsize;
>  
> @@ -141,7 +142,13 @@ static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
>  	tlbcam_addrs[index].start = virt;
>  	tlbcam_addrs[index].limit = virt + size - 1;
>  	tlbcam_addrs[index].phys = phys;
> +}
>  
> +void settlbcam(int index, unsigned long virt, phys_addr_t phys,


Nit: shouldn't this be left static? Also, now with this bulk TLB1 loading is it still used? Maybe it can be dropped.

---
Best Regards, Laurentiu

  reply	other threads:[~2015-10-07 15:33 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-07  3:48 [PATCH v2 00/18] powerpc/fsl-book3e-64: kexec/kdump support Scott Wood
2015-10-07  3:48 ` [PATCH v2 01/18] powerpc/fsl-booke-64: Allow booting from the secondary thread Scott Wood
2015-10-07  3:48 ` [PATCH v2 02/18] powerpc/fsl-corenet: Disable coreint if kexec is enabled Scott Wood
2015-10-07  3:48 ` [PATCH v2 03/18] powerpc/85xx: Don't use generic timebase sync on 64-bit Scott Wood
2015-10-07  3:48 ` [PATCH v2 04/18] powerpc/fsl_pci: Don't set up inbound windows in kdump crash kernel Scott Wood
2015-10-07  3:48 ` [PATCH v2 05/18] powerpc/85xx: Load all early TLB entries at once Scott Wood
2015-10-07 14:00   ` Laurentiu Tudor [this message]
2015-10-07 19:57     ` Scott Wood
2015-10-07  3:48 ` [PATCH v2 06/18] powerpc/fsl-booke-64: Don't limit ppc64_rma_size to one TLB entry Scott Wood
2015-10-07  3:48 ` [PATCH v2 07/18] powerpc/85xx: Implement 64-bit kexec support Scott Wood
2015-10-07  3:48 ` [PATCH v2 08/18] powerpc/e6500: kexec: Handle hardware threads Scott Wood
2015-10-07  3:48 ` [PATCH v2 09/18] powerpc/book3e-64: rename interrupt_end_book3e with __end_interrupts Scott Wood
2015-10-07  3:48 ` [PATCH v2 10/18] powerpc/booke64: Fix args to copy_and_flush Scott Wood
2015-10-07  3:48 ` [PATCH v2 11/18] powerpc/book3e: support CONFIG_RELOCATABLE Scott Wood
2015-10-07  3:48 ` [PATCH v2 12/18] powerpc/book3e/kdump: Enable crash_kexec_wait_realmode Scott Wood
2015-10-07  3:48 ` [PATCH v2 13/18] powerpc/book3e-64: Don't limit paca to 256 MiB Scott Wood
2015-10-19 22:10   ` [PATCH v3 13/17] " Scott Wood
2015-10-07  3:48 ` [PATCH v2 14/18] powerpc/book3e-64/kexec: create an identity TLB mapping Scott Wood
2015-10-07  3:48 ` [PATCH v2 15/18] powerpc/book3e-64/kexec: Enable SMP release Scott Wood
2015-10-07  3:48 ` [PATCH v2 16/18] powerpc/booke: Only use VIRT_PHYS_OFFSET on booke32 Scott Wood
2015-10-07  3:48 ` [PATCH v2 17/18] powerpc/book3e-64/kexec: Set "r4 = 0" when entering spinloop Scott Wood
2015-10-07  3:48 ` [PATCH v2 18/18] powerpc/book3e-64: Enable kexec Scott Wood

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