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Date: Sun, 17 Jan 2016 02:01:05 +0100
From: "Maciej S. Szmigiero" <mail@maciej.szmigiero.name>
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To: Timur Tabi <timur@tabi.org>
CC: Fabio Estevam <festevam@gmail.com>,
 "alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
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 "linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
 linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/3] ASoC: fsl_ssi: remove register defaults
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On 17.01.2016 01:10, Timur Tabi wrote:
> Maciej S. Szmigiero wrote:
>> +static const struct regmap_config fsl_ssi_regconfig_imx21 = {
>> +    .max_register = CCSR_SSI_SRMSK,
>> +    .reg_bits = 32,
>> +    .val_bits = 32,
>> +    .reg_stride = 4,
>> +    .val_format_endian = REGMAP_ENDIAN_NATIVE,
>> +    .num_reg_defaults_raw = CCSR_SSI_SRMSK / 4 + 1,
>> +    .readable_reg = fsl_ssi_readable_reg,
>> +    .volatile_reg = fsl_ssi_volatile_reg,
>> +    .precious_reg = fsl_ssi_precious_reg,
>> +    .writeable_reg = fsl_ssi_writeable_reg,
>> +    .cache_type = REGCACHE_RBTREE,
>> +};
>> +
>>   static const struct regmap_config fsl_ssi_regconfig = {
>>       .max_register = CCSR_SSI_SACCDIS,
>>       .reg_bits = 32,
>>       .val_bits = 32,
>>       .reg_stride = 4,
>>       .val_format_endian = REGMAP_ENDIAN_NATIVE,
>> -    .reg_defaults = fsl_ssi_reg_defaults,
>> -    .num_reg_defaults = ARRAY_SIZE(fsl_ssi_reg_defaults),
>> +    .num_reg_defaults_raw = CCSR_SSI_SACCDIS / 4 + 1,
>>       .readable_reg = fsl_ssi_readable_reg,
>>       .volatile_reg = fsl_ssi_volatile_reg,
>>       .precious_reg = fsl_ssi_precious_reg,
> 
> Is this really necessary?  Why do we need separate register configs for one specific SOC?
> There are already too many "if (some_stupid_imx_variant)" blocks in this driver.

This is because (at least according to the datasheet) imx21-class SSI
registers end at CCSR_SSI_SRMSK (no SACC{ST,EN,DIS} regs), so
reading them for cache initialization may not be safe.

Also, a "MXC 91221 only" comment before these regs in FSL tree
(drivers/mxc/ssi/registers.h) seems to confirm that these registers
aren't present at least on some SSI (or SoC) models.

Best regards,
Maciej Szmigiero