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Violators will be prosecuted for from ; Wed, 20 Dec 2017 18:02:47 -0000 Subject: Re: [PATCH v4 2/2] cxl: read PHB indications from the device tree To: Philippe Bergheaud , linuxppc-dev@lists.ozlabs.org Cc: clombard@linux.vnet.ibm.com, benh@au1.ibm.com References: <20171215134818.23864-1-felix@linux.vnet.ibm.com> <20171215134818.23864-2-felix@linux.vnet.ibm.com> From: Frederic Barrat Date: Wed, 20 Dec 2017 19:02:42 +0100 MIME-Version: 1.0 In-Reply-To: <20171215134818.23864-2-felix@linux.vnet.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Message-Id: <57e40fbc-bc45-f69c-4442-fcaffa7dac9a@linux.vnet.ibm.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Le 15/12/2017 à 14:48, Philippe Bergheaud a écrit : > Configure the P9 XSL_DSNCTL register with PHB indications found > in the device tree, or else use legacy hard-coded values. > > Signed-off-by: Philippe Bergheaud > --- > Changelog: > > v2: New patch. Use the new device tree property "ibm,phb-indications". > > v3: No change. > > v4: No functional change. > Drop cosmetic fix in comment. > > This patch depends on the following skiboot prerequisite: > > https://patchwork.ozlabs.org/patch/849162/ > --- > drivers/misc/cxl/cxl.h | 2 +- > drivers/misc/cxl/cxllib.c | 2 +- > drivers/misc/cxl/pci.c | 40 +++++++++++++++++++++++++++++++++++----- > 3 files changed, 37 insertions(+), 7 deletions(-) > > diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h > index e46a4062904a..5a6e9a921c2b 100644 > --- a/drivers/misc/cxl/cxl.h > +++ b/drivers/misc/cxl/cxl.h > @@ -1062,7 +1062,7 @@ int cxl_psl_purge(struct cxl_afu *afu); > int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid, > u32 *phb_index, u64 *capp_unit_id); > int cxl_slot_is_switched(struct pci_dev *dev); > -int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg); > +int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg); > u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9); > > void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx); > diff --git a/drivers/misc/cxl/cxllib.c b/drivers/misc/cxl/cxllib.c > index dc9bc1807fdf..61f80d586279 100644 > --- a/drivers/misc/cxl/cxllib.c > +++ b/drivers/misc/cxl/cxllib.c > @@ -99,7 +99,7 @@ int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg) > if (rc) > return rc; > > - rc = cxl_get_xsl9_dsnctl(capp_unit_id, &cfg->dsnctl); > + rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &cfg->dsnctl); > if (rc) > return rc; > if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { > diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c > index 19969ee86d6f..c58fb28685af 100644 > --- a/drivers/misc/cxl/pci.c > +++ b/drivers/misc/cxl/pci.c > @@ -409,7 +409,36 @@ int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid, > return 0; > } > > -int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg) > +static u64 nbwind = 0; > +static u64 asnind = 0; > +static u64 capiind = 0; Could we avoid the globals and keep the static within get_phb_indications() and have the function return them as out parameters? It would seem cleaner to me. Fred > +static int get_phb_indications(struct pci_dev *dev) > +{ > + struct device_node *np; > + const __be32 *prop; > + > + if (capiind) > + return 0; > + > + if (!(np = pnv_pci_get_phb_node(dev))) > + return -1; > + > + prop = of_get_property(np, "ibm,phb-indications", NULL); > + if (!prop) { > + nbwind = 0x0300UL; /* legacy values */ > + asnind = 0x0400UL; > + capiind = 0x0200UL; > + } else { > + nbwind = (u64)be32_to_cpu(prop[2]); > + asnind = (u64)be32_to_cpu(prop[1]); > + capiind = (u64)be32_to_cpu(prop[0]); > + } > + of_node_put(np); > + return 0; > +} > + > +int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg) > { > u64 xsl_dsnctl; > > @@ -423,7 +452,8 @@ int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg) > * Tell XSL where to route data to. > * The field chipid should match the PHB CAPI_CMPM register > */ > - xsl_dsnctl = ((u64)0x2 << (63-7)); /* Bit 57 */ > + get_phb_indications(dev); > + xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */ > xsl_dsnctl |= (capp_unit_id << (63-15)); > > /* nMMU_ID Defaults to: b’000001001’*/ > @@ -437,14 +467,14 @@ int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg) > * nbwind=0x03, bits [57:58], must include capi indicator. > * Not supported on P9 DD1. > */ > - xsl_dsnctl |= ((u64)0x03 << (63-47)); > + xsl_dsnctl |= (nbwind << (63-55)); > > /* > * Upper 16b address bits of ASB_Notify messages sent to the > * system. Need to match the PHB’s ASN Compare/Mask Register. > * Not supported on P9 DD1. > */ > - xsl_dsnctl |= ((u64)0x04 << (63-55)); > + xsl_dsnctl |= asnind; > } > > *reg = xsl_dsnctl; > @@ -464,7 +494,7 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter, > if (rc) > return rc; > > - rc = cxl_get_xsl9_dsnctl(capp_unit_id, &xsl_dsnctl); > + rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl); > if (rc) > return rc; >