* powerpc/powernv: copy/paste - Mask XERS0 bit in CR
@ 2018-05-31 4:29 Haren Myneni
2018-06-03 10:48 ` Michael Ellerman
0 siblings, 1 reply; 4+ messages in thread
From: Haren Myneni @ 2018-05-31 4:29 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, sukadev
NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
which is not related to paste request. The current paste function
returns failure for the successful request when this bit is set.
So mask this bit and check the proper return status.
Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: Haren Myneni <haren@us.ibm.com>
diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
index c9a5036..82392e3 100644
--- a/arch/powerpc/platforms/powernv/copy-paste.h
+++ b/arch/powerpc/platforms/powernv/copy-paste.h
@@ -9,7 +9,8 @@
#include <asm/ppc-opcode.h>
#define CR0_SHIFT 28
-#define CR0_MASK 0xF
+#define CR0_MASK 0xE /* 3rd bit undefined or set for XER[SO] */
+
/*
* Copy/paste instructions:
*
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: powerpc/powernv: copy/paste - Mask XERS0 bit in CR
2018-05-31 4:29 powerpc/powernv: copy/paste - Mask XERS0 bit in CR Haren Myneni
@ 2018-06-03 10:48 ` Michael Ellerman
2018-06-04 2:15 ` Haren Myneni
0 siblings, 1 reply; 4+ messages in thread
From: Michael Ellerman @ 2018-06-03 10:48 UTC (permalink / raw)
To: Haren Myneni; +Cc: linuxppc-dev, sukadev
Hi Haren,
Haren Myneni <haren@linux.vnet.ibm.com> writes:
>
> NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
> which is not related to paste request. The current paste function
> returns failure for the successful request when this bit is set.
> So mask this bit and check the proper return status.
>
> Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
> Cc: stable@vger.kernel.org # v4.14+
> Signed-off-by: Haren Myneni <haren@us.ibm.com>
>
> diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
> index c9a5036..82392e3 100644
> --- a/arch/powerpc/platforms/powernv/copy-paste.h
> +++ b/arch/powerpc/platforms/powernv/copy-paste.h
> @@ -9,7 +9,8 @@
> #include <asm/ppc-opcode.h>
>
> #define CR0_SHIFT 28
> -#define CR0_MASK 0xF
> +#define CR0_MASK 0xE /* 3rd bit undefined or set for XER[SO] */
> +
> /*
> * Copy/paste instructions:
> *
Unfortunately this no longer applies to my next branch, because those
macros have been moved out of this header as part of an unrelated patch.
The following patch should work instead, can you please confirm by
testing it?
diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
index 3fa62de96d9c..c46a326776cf 100644
--- a/arch/powerpc/platforms/powernv/copy-paste.h
+++ b/arch/powerpc/platforms/powernv/copy-paste.h
@@ -41,5 +41,7 @@ static inline int vas_paste(void *paste_address, int offset)
: "b" (offset), "b" (paste_address)
: "memory", "cr0");
- return (cr >> CR0_SHIFT) & CR0_MASK;
+
+ /* We mask with 0xE to ignore SO */
+ return (cr >> CR0_SHIFT) & 0xE;
}
cheers
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: powerpc/powernv: copy/paste - Mask XERS0 bit in CR
2018-06-03 10:48 ` Michael Ellerman
@ 2018-06-04 2:15 ` Haren Myneni
2018-06-04 9:11 ` Michael Ellerman
0 siblings, 1 reply; 4+ messages in thread
From: Haren Myneni @ 2018-06-04 2:15 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, sukadev
On 06/03/2018 03:48 AM, Michael Ellerman wrote:
> Hi Haren,
>
> Haren Myneni <haren@linux.vnet.ibm.com> writes:
>>
>> NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
>> which is not related to paste request. The current paste function
>> returns failure for the successful request when this bit is set.
>> So mask this bit and check the proper return status.
>>
>> Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
>> Cc: stable@vger.kernel.org # v4.14+
>> Signed-off-by: Haren Myneni <haren@us.ibm.com>
>>
>> diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
>> index c9a5036..82392e3 100644
>> --- a/arch/powerpc/platforms/powernv/copy-paste.h
>> +++ b/arch/powerpc/platforms/powernv/copy-paste.h
>> @@ -9,7 +9,8 @@
>> #include <asm/ppc-opcode.h>
>>
>> #define CR0_SHIFT 28
>> -#define CR0_MASK 0xF
>> +#define CR0_MASK 0xE /* 3rd bit undefined or set for XER[SO] */
>> +
>> /*
>> * Copy/paste instructions:
>> *
>
> Unfortunately this no longer applies to my next branch, because those
> macros have been moved out of this header as part of an unrelated patch.
>
> The following patch should work instead, can you please confirm by
> testing it?
>
> diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
> index 3fa62de96d9c..c46a326776cf 100644
> --- a/arch/powerpc/platforms/powernv/copy-paste.h
> +++ b/arch/powerpc/platforms/powernv/copy-paste.h
> @@ -41,5 +41,7 @@ static inline int vas_paste(void *paste_address, int offset)
> : "b" (offset), "b" (paste_address)
> : "memory", "cr0");
>
> - return (cr >> CR0_SHIFT) & CR0_MASK;
> +
> + /* We mask with 0xE to ignore SO */
> + return (cr >> CR0_SHIFT) & 0xE;
> }
>
>
Tested with this patch and it works.
Thanks
Haren
> cheers
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: powerpc/powernv: copy/paste - Mask XERS0 bit in CR
2018-06-04 2:15 ` Haren Myneni
@ 2018-06-04 9:11 ` Michael Ellerman
0 siblings, 0 replies; 4+ messages in thread
From: Michael Ellerman @ 2018-06-04 9:11 UTC (permalink / raw)
To: Haren Myneni; +Cc: linuxppc-dev, sukadev
Haren Myneni <haren@linux.vnet.ibm.com> writes:
> On 06/03/2018 03:48 AM, Michael Ellerman wrote:
>> Haren Myneni <haren@linux.vnet.ibm.com> writes:
>>> NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
>>> which is not related to paste request. The current paste function
>>> returns failure for the successful request when this bit is set.
>>> So mask this bit and check the proper return status.
>>>
>>> Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
>>> Cc: stable@vger.kernel.org # v4.14+
>>> Signed-off-by: Haren Myneni <haren@us.ibm.com>
>>>
>>> diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
>>> index c9a5036..82392e3 100644
>>> --- a/arch/powerpc/platforms/powernv/copy-paste.h
>>> +++ b/arch/powerpc/platforms/powernv/copy-paste.h
>>> @@ -9,7 +9,8 @@
>>> #include <asm/ppc-opcode.h>
>>>
>>> #define CR0_SHIFT 28
>>> -#define CR0_MASK 0xF
>>> +#define CR0_MASK 0xE /* 3rd bit undefined or set for XER[SO] */
>>> +
>>> /*
>>> * Copy/paste instructions:
>>> *
>>
>> Unfortunately this no longer applies to my next branch, because those
>> macros have been moved out of this header as part of an unrelated patch.
>>
>> The following patch should work instead, can you please confirm by
>> testing it?
>>
>> diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
>> index 3fa62de96d9c..c46a326776cf 100644
>> --- a/arch/powerpc/platforms/powernv/copy-paste.h
>> +++ b/arch/powerpc/platforms/powernv/copy-paste.h
>> @@ -41,5 +41,7 @@ static inline int vas_paste(void *paste_address, int offset)
>> : "b" (offset), "b" (paste_address)
>> : "memory", "cr0");
>>
>> - return (cr >> CR0_SHIFT) & CR0_MASK;
>> +
>> + /* We mask with 0xE to ignore SO */
>> + return (cr >> CR0_SHIFT) & 0xE;
>> }
>
> Tested with this patch and it works.
Thanks. I sent a new version to the list and will apply that.
cheers
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-06-04 9:11 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2018-05-31 4:29 powerpc/powernv: copy/paste - Mask XERS0 bit in CR Haren Myneni
2018-06-03 10:48 ` Michael Ellerman
2018-06-04 2:15 ` Haren Myneni
2018-06-04 9:11 ` Michael Ellerman
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