From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from rv-out-0910.google.com (rv-out-0910.google.com [209.85.198.187]) by ozlabs.org (Postfix) with ESMTP id 44FA2DDE3E for ; Thu, 16 Aug 2007 07:12:42 +1000 (EST) Received: by rv-out-0910.google.com with SMTP id f5so28787rvb for ; Wed, 15 Aug 2007 14:12:40 -0700 (PDT) Message-ID: <5c9cd53b0708151412v2f5feb74v9e0b49d114b83021@mail.gmail.com> Date: Wed, 15 Aug 2007 17:12:40 -0400 From: "mike zheng" To: "Becky Bruce" Subject: Re: System crash on boot_e500.S on 2.4Kernel In-Reply-To: MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_5892_22188120.1187212360616" References: <5c9cd53b0708141321h62f0ddd1k3a57a37f52e93894@mail.gmail.com> <36201C92-F117-4273-9FA7-13665CF0C6DB@freescale.com> <5c9cd53b0708150659u2ba88a9as5055b42fb1e2be67@mail.gmail.com> Cc: linuxppc-embedded@ozlabs.org List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , ------=_Part_5892_22188120.1187212360616 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline Here is the PC value before the rfi: cds8458>halt Target CPU: : MPC85xx (e500v2 rev.1) Target state : halted Debug entry cause : instruction breakpoint Current PC : 0x0000015c Current CR : 0x24024022 Current MSR : 0x00012100 Current LR :0x00000148 Current CCSRBAR :0x0_e000000 After the rfi: #step timeout defected cds8458>halt Target CPU: : MPC85xx (e500v2 rev.1) Target state : halted Debug entry cause : COP halt Current PC : 0xfff81300 Current CR : 0x24024022 Current MSR : 0x00001000 Current LR :0x00000148 Current CCSRBAR :0x0_e000000 On 8/15/07, Becky Bruce wrote: > > > On Aug 15, 2007, at 8:59 AM, mike zheng wrote: > > > I use BDI to debug these two instructions. And here are the output > > of BDI just before the "rfi". The content of R6, R7 is different > > from SRR0(SPR26) and SRR1(SPR27). > > I see you have not printed the pc/nia once you stop. Are you sure > you're stopped where you think? Please check this. > > -B > > > > > cds8548>res run > > > > - TARGET: processing user reset request > > > > - BDI asserts HRESET > > > > - Reset JTAG controller passed > > > > - JTAG exists check passed > > > > - IDCODE is 0x0003901D > > > > - SVR is 0x80390011 > > > > - PVR is 0x80210010 > > > > - CCSRBAR is 0x0_ff700000 > > > > - BDI removes HRESET > > > > - TARGET: Target PVR is 0x80210010 > > > > - TARGET: resetting target passed > > > > cds8548>halt > > > > Target CPU : MPC85xx (e500v2 rev.1) > > > > Target state : halted > > > > Debug entry cause : COP halt > > > > Current PC : 0xfff82560 > > > > Current CR : 0x88000042 > > > > Current MSR : 0x00021200 > > > > Current LR : 0xfff8aa4c > > > > Current CCSRBAR : 0x0_e0000000 > > > > cds8548>ci > > > > cds8548>bi 0x0000015c > > > > Breakpoint identification is 0 > > > > cds8548>go > > > > - TARGET: stopped > > > > cds8548>rd > > > > GPR00: 00000000 0ffabd20 00000200 00000008 > > > > GPR04: 00000000 00000001 00000020 00000160 > > > > GPR08: 1f8b0808 00000148 0ffabace 0ffe08b0 > > > > GPR12: 00000006 764deddb 10000300 007fff00 > > > > GPR16: 00000001 ffffffff 007fff25 0ffff9d8 > > > > GPR20: 007ffeb0 00000000 0fffaa3c 0ffae490 > > > > GPR24: 00000000 00000003 02000040 007fff25 > > > > GPR28: 007fff00 0ffab3b8 0fcd6000 007ffeb0 > > > > CR : 24024022 MSR: 00021200 > > > > cds8548>rdspr 26 > > > > SPR 26 : 0xfff81300 - 519424 > > > > cds8548>rdspr 27 > > > > SPR 27 : 0x00001000 4096 > > > > cds8548> > > > > > > > > > > > > > > On 8/14/07, Andy Fleming wrote: > > On Aug 14, 2007, at 15:21, mike zheng wrote: > > > > > > > > Hi All, > > > > > > I am trying to bring up MPC8548 CDS board on 2.4 kernel. I have > > > problem in the head_e500.S. The "mtspr SRR0, r7; mtspr SRR1 r6" > > > does not work for me. The content of R7 and R6 are not moved to > > > SRR0 and SRR1. I am using the tool-chain from Freescale for 2.6 > > > kernel. > > > > > > Any idea on this issue? > > > > Just to check...how do you know it doesn't work? > > > > Andy > > > > _______________________________________________ > > Linuxppc-embedded mailing list > > Linuxppc-embedded@ozlabs.org > > https://ozlabs.org/mailman/listinfo/linuxppc-embedded > > ------=_Part_5892_22188120.1187212360616 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline
Here is the PC value before the rfi:
 
cds8458>halt
           Target CPU:           : MPC85xx (e500v2 rev.1)
           Target state            : halted
           Debug entry cause  : instruction breakpoint
           Current PC             : 0x0000015c
           Current CR             : 0x24024022
           Current MSR          : 0x00012100
           Current LR              :0x00000148
           Current CCSRBAR  :0x0_e000000
 
After the rfi:
 
#step timeout defected
cds8458>halt
           Target CPU:           : MPC85xx (e500v2 rev.1)
           Target state            : halted
           Debug entry cause  : COP halt
           Current PC             : 0xfff81300
           Current CR             : 0x24024022
           Current MSR          : 0x00001000
           Current LR              :0x00000148
           Current CCSRBAR  :0x0_e000000


 
On 8/15/07, Becky Bruce <becky.bruce@freescale.com> wrote:

On Aug 15, 2007, at 8:59 AM, mike zheng wrote:

> I use BDI to debug these two instructions. And here are the output
> of BDI just before the "rfi". The content of R6, R7 is different
> from SRR0(SPR26) and SRR1(SPR27).

I see you have not printed the pc/nia once you stop.  Are you sure
you're stopped where you think?  Please check this.

-B

>
> cds8548>res run
>
> - TARGET: processing user reset request
>
> - BDI asserts HRESET
>
> - Reset JTAG controller passed
>
> - JTAG exists check passed
>
> - IDCODE is 0x0003901D
>
> - SVR is 0x80390011
>
> - PVR is 0x80210010
>
> - CCSRBAR is 0x0_ff700000
>
> - BDI removes HRESET
>
> - TARGET: Target PVR is 0x80210010
>
> - TARGET: resetting target passed
>
> cds8548>halt
>
> Target CPU : MPC85xx (e500v2 rev.1)
>
> Target state : halted
>
> Debug entry cause : COP halt
>
> Current PC : 0xfff82560
>
> Current CR : 0x88000042
>
> Current MSR : 0x00021200
>
> Current LR : 0xfff8aa4c
>
> Current CCSRBAR : 0x0_e0000000
>
> cds8548>ci
>
> cds8548>bi 0x0000015c
>
> Breakpoint identification is 0
>
> cds8548>go
>
> - TARGET: stopped
>
> cds8548>rd
>
> GPR00: 00000000 0ffabd20 00000200 00000008
>
> GPR04: 00000000 00000001 00000020 00000160
>
> GPR08: 1f8b0808 00000148 0ffabace 0ffe08b0
>
> GPR12: 00000006 764deddb 10000300 007fff00
>
> GPR16: 00000001 ffffffff 007fff25 0ffff9d8
>
> GPR20: 007ffeb0 00000000 0fffaa3c 0ffae490
>
> GPR24: 00000000 00000003 02000040 007fff25
>
> GPR28: 007fff00 0ffab3b8 0fcd6000 007ffeb0
>
> CR : 24024022 MSR: 00021200
>
> cds8548>rdspr 26
>
> SPR 26 : 0xfff81300 - 519424
>
> cds8548>rdspr 27
>
> SPR 27 : 0x00001000 4096
>
> cds8548>
>
>
>
>
>
>
> On 8/14/07, Andy Fleming <afleming@freescale.com> wrote:
> On Aug 14, 2007, at 15:21, mike zheng wrote:
>
> >
> > Hi All,
> >
> > I am trying to bring up MPC8548 CDS board on 2.4 kernel. I have
> > problem in the head_e500.S. The "mtspr SRR0, r7; mtspr SRR1 r6"
> > does not work for me. The content of R7 and R6 are not moved to
> > SRR0 and SRR1.  I am using the tool-chain from Freescale for 2.6
> > kernel.
> >
> > Any idea on this issue?
>
> Just to check...how do you know it doesn't work?
>
> Andy
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded


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