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Tue, 21 Jul 2020 07:22:56 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9656711C058; Tue, 21 Jul 2020 07:22:55 +0000 (GMT) Received: from pomme.local (unknown [9.145.36.105]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 21 Jul 2020 07:22:55 +0000 (GMT) Subject: Re: [RFC PATCH] powerpc/pseries/svm: capture instruction faulting on MMIO access, in sprg0 register To: Segher Boessenkool References: <1594888333-9370-1-git-send-email-linuxram@us.ibm.com> <18e3bcee-8a3a-bd13-c995-8e4168471f74@linux.ibm.com> <20200720201041.GM30544@gate.crashing.org> <20200720202452.GN30544@gate.crashing.org> From: Laurent Dufour Message-ID: <5d912506-5834-db1a-60a1-1ccb213ff37a@linux.ibm.com> Date: Tue, 21 Jul 2020 09:22:55 +0200 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200720202452.GN30544@gate.crashing.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-21_02:2020-07-21, 2020-07-21 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 phishscore=0 clxscore=1011 impostorscore=0 bulkscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007210048 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aik@ozlabs.ru, Ram Pai , kvm-ppc@vger.kernel.org, bharata@linux.ibm.com, sathnaga@linux.vnet.ibm.com, sukadev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, bauerman@linux.ibm.com, david@gibson.dropbear.id.au Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Le 20/07/2020 à 22:24, Segher Boessenkool a écrit : > On Mon, Jul 20, 2020 at 03:10:41PM -0500, Segher Boessenkool wrote: >> On Mon, Jul 20, 2020 at 11:39:56AM +0200, Laurent Dufour wrote: >>> Le 16/07/2020 à 10:32, Ram Pai a écrit : >>>> + if (is_secure_guest()) { \ >>>> + __asm__ __volatile__("mfsprg0 %3;" \ >>>> + "lnia %2;" \ >>>> + "ld %2,12(%2);" \ >>>> + "mtsprg0 %2;" \ >>>> + "sync;" \ >>>> + #insn" %0,%y1;" \ >>>> + "twi 0,%0,0;" \ >>>> + "isync;" \ >>>> + "mtsprg0 %3" \ >>>> + : "=r" (ret) \ >>>> + : "Z" (*addr), "r" (0), "r" (0) \ >>> >>> I'm wondering if SPRG0 is restored to its original value. >>> You're using the same register (r0) for parameters 2 and 3, so when doing >>> lnia %2, you're overwriting the SPRG0 value you saved in r0 just earlier. >> >> It is putting the value 0 in the registers the compiler chooses for >> operands 2 and 3. But operand 3 is written, while the asm says it is an >> input. It needs an earlyclobber as well. Oh nice, I was not aware that compiler may choose registers this way. Good to know, thanks for the explanation. >>> It may be clearer to use explicit registers for %2 and %3 and to mark them >>> as modified for the compiler. >> >> That is not a good idea, imnsho. > > (The explicit register number part, I mean; operand 2 should be an > output as well, yes.) Sure if the compiler can choose the registers that's far better. Cheers, Laurent.