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[2003:cb:c706:b800:3757:baed:f95e:20ac]) by smtp.gmail.com with ESMTPSA id o25-20020a05600c511900b003dfe549da4fsm18407191wms.18.2023.02.28.07.55.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Feb 2023 07:55:42 -0800 (PST) Message-ID: <5d99c731-c47a-c525-76e5-4578d9dfc9ee@redhat.com> Date: Tue, 28 Feb 2023 16:55:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH mm-unstable v1 11/26] microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE To: Geert Uytterhoeven References: <20230113171026.582290-1-david@redhat.com> <20230113171026.582290-12-david@redhat.com> <9ed766a6-cf06-535d-3337-ea6ff25c2362@redhat.com> From: David Hildenbrand Organization: Red Hat In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-ia64@vger.kernel.org, linux-sh@vger.kernel.org, Yang Shi , Peter Xu , linux-mips@vger.kernel.org, linux-mm@kvack.org, Nadav Amit , sparclinux@vger.kernel.org, linux-riscv@lists.infradead.org, Andrea Arcangeli , linux-s390@vger.kernel.org, linux-hexagon@vger.kernel.org, x86@kernel.org, Hugh Dickins , linux-csky@vger.kernel.org, Mike Rapoport , Vlastimil Babka , Jason Gunthorpe , linux-snps-arc@lists.infradead.org, linux-xtensa@linux-xtensa.org, John Hubbard , linux-um@lists.infradead.org, linux-m68k@lists.linux-m68k.org, openrisc@lists.librecores.org, loongarch@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Michal Simek , linux-parisc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, Andrew Morton , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 27.02.23 20:46, Geert Uytterhoeven wrote: > Hi David, > > On Mon, Feb 27, 2023 at 6:01 PM David Hildenbrand wrote: >>>>>> /* >>>>>> * Externally used page protection values. >>>>>> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h >>>>>> index 42f5988e998b..7e3de54bf426 100644 >>>>>> --- a/arch/microblaze/include/asm/pgtable.h >>>>>> +++ b/arch/microblaze/include/asm/pgtable.h > >>>>>> * - All other bits of the PTE are loaded into TLBLO without >>>>>> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for >>>>>> * software PTE bits. We actually use bits 21, 24, 25, and >>>>>> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address); >>>>>> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ >>>>>> #define _PMD_PRESENT PAGE_MASK >>>>>> >>>>>> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */ >>>>>> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY >>>>> >>>>> _PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is >>>>> wrong? >>>> >>>> In the example, I use MSB-0 bit numbering (which I determined to be >>>> correct in microblaze context eventually, but I got confused a couple a >>>> times because it's very inconsistent). That should be MSB-0 bit 24. >>> >>> Thanks, TIL microblaze uses IBM bit numbering... >> >> I assume IBM bit numbering corresponds to MSB-0 bit numbering, correct? > > Correct, as seen in s370 and PowerPC manuals... Good, I have some solid s390x background, but thinking about the term "IBM PC" made me double-check that we're talking about the same thing ;) > >> I recall that I used the comment above "/* Definitions for MicroBlaze. >> */" as an orientation. >> >> 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 >> RPN..................... 0 0 EX WR ZSEL....... W I M G > > Indeed, that's where I noticed the "unconventional" numbering... > >> So ... either we adjust both or we leave it as is. (again, depends on >> what the right thing to to is -- which I don't know :) ) > > It depends whether you want to match the hardware documentation, > or the Linux BIT() macro and friends... The hardware documentation, so we should be good. Thanks! -- Thanks, David / dhildenb