RE: New MPC5200 Eratta/ATA Bugs

RE: New MPC5200 Eratta/ATA Bugs

[Stephen Warren]

Eric N. Johnson (ACD) wrote:
> Freescale just realeased a new version of the eratta (hardware bugs)=20
> document for the MPC5200.  It was posted last week, and adds some
pretty=20
> significant problems to the FEC Ethernet and IDE/ATA sections.
>
> Specifically, I'm wonder if Eratta ID 485 may be the cause of some of
the=20
> IDE issues we've been attributing to Bestcomm:
>=20
>   "During the concurrent access of ATA DMA READ and PCI or LPC the
>    ATA_ISOLATION signal can be incorrectly driven when ATA is paused."
>=20
> Unfortunately, their proposed workaround isn't appropriate for many=20
> cases.  They suggest that you not use "ATA_ISOLATION" and connect the
ATA=20
> device directly to the LP bus without any buffering.  This could lead
to=20
> serious bus integrity issues, especially if the ATA device is
connected by=20
> a ribbon cable.=20

Freescale certainly confirmed that was the issue we were up against.

Freescale have been working with us on a board work-around for the
problem. This basically involves deriving a substitute ATA_ISOLATION
signal from the regular ATA control signals, in some cases.

--=20
Stephen Warren, Software Engineer, NVIDIA, Fort Collins, CO
swarren@nvidia.com        http://www.nvidia.com/
swarren@wwwdotorg.org     http://www.wwwdotorg.org/pgp.html

RE: New MPC5200 Eratta/ATA Bugs

[Eric N. Johnson (ACD)]

At 02:35 PM 4/25/2005, Stephen Warren wrote:
>Freescale have been working with us on a board work-around for the
>problem. This basically involves deriving a substitute ATA_ISOLATION
>signal from the regular ATA control signals, in some cases.

Are you able to share the circuit they've recommended?  Is it as simple as:
   ISOLATION = ((ATA_CS1 or ATA_IOR) and (ATA_CS0 or ATA_IOR))

This seems like it would be in violation of the setup and hold time 
requirements for the data bus.

I've been told there's a new silicon revision of the MPC5200 due sometime 
later in the year, but the date keeps getting pushed back.

Eric

------------------------------------
Eric Johnson, Electrical Engineer
Advanced Communication Design
   7901 12th Avenue South
   Bloomington, MN 55425
Ph: 952-854-4000  Fax: 952-854-5774

RE: New MPC5200 Eratta/ATA Bugs

[Stephen Warren]

From: Eric N. Johnson (ACD) [mailto:ejohnson@acdstar.com]=20
> At 02:35 PM 4/25/2005, Stephen Warren wrote:
> >Freescale have been working with us on a board work-around for the
> >problem. This basically involves deriving a substitute ATA_ISOLATION
> >signal from the regular ATA control signals, in some cases.
>=20
> Are you able to share the circuit they've recommended?  Is it as
simple as:
>    ISOLATION =3D ((ATA_CS1 or ATA_IOR) and (ATA_CS0 or ATA_IOR))
>=20
> This seems like it would be in violation of the setup and hold time=20
> requirements for the data bus.

This was suggested:

>>> 2. ... beleives that to fix the ATA_ISOLATION with logic would be
>>>  something like this:
>>>  ATA_ISOLATION_TO_BUFFERS =3D MPC's_ATA_ISOLATION or (GPIO_UDMA and
ATA_DMA_ACK#)=20

The idea is that the errata only causes a problem for UDMA (not MDMA or
PIO). So, the kernel is modified to set a GPIO whenever UDMA is in
progress. This triggers the external logic to use ATA_DMA_ACK# to
trigger the bus drivers. ATA_DMA_ACK# is the signal that means an actual
DMA data transfer is in progress.

That said, various people are in the process of trying the above logic,
and the more explicit:

ATA_ISOLATION_TO_BUFFERS =3D \
    (~GPIO_UDMA and MPC's_ATA_ISOLATION) | \
    (GPIO_UDMA and ATA_DMA_ACK#)

(possibly with the extra ~'s in there to fix high v.s. low true...)

And neither of these approaches actually works for us.

If I recall correctly, one of the other errata means MDMA can't work
either...

> I've been told there's a new silicon revision of the MPC5200 due
sometime=20
> later in the year, but the date keeps getting pushed back.

We were told this too. Sounds like maybe sometime in the middle of the
year at the earliest.

--=20
Stephen Warren, Software Engineer, NVIDIA, Fort Collins, CO
swarren@nvidia.com        http://www.nvidia.com/
swarren@wwwdotorg.org     http://www.wwwdotorg.org/pgp.html

New MPC5200 Eratta/ATA Bugs

[Eric N. Johnson (ACD)]

Freescale just realeased a new version of the eratta (hardware bugs) 
document for the MPC5200.  It was posted last week, and adds some pretty 
significant problems to the FEC Ethernet and IDE/ATA sections.

Specifically, I'm wonder if Eratta ID 485 may be the cause of some of the 
IDE issues we've been attributing to Bestcomm:

  "During the concurrent access of ATA DMA READ and PCI or LPC the
   ATA_ISOLATION signal can be incorrectly driven when ATA is paused."

Unfortunately, their proposed workaround isn't appropriate for many 
cases.  They suggest that you not use "ATA_ISOLATION" and connect the ATA 
device directly to the LP bus without any buffering.  This could lead to 
serious bus integrity issues, especially if the ATA device is connected by 
a ribbon cable.

Eric
------------------------------------
Eric Johnson, Electrical Engineer
Advanced Communication Design
   7901 12th Avenue South
   Bloomington, MN 55425
Ph: 952-854-4000  Fax: 952-854-5774