From mboxrd@z Thu Jan  1 00:00:00 1970
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To: Michael Ellerman <michael@ellerman.id.au>
Subject: Re: [PATCH] powerpc: Fix =?UTF-8?Q?BPF=5FJIT=20code=20to=20link?=
 =?UTF-8?Q?=20with=20multiple=20TOCs?=
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Date: Fri, 22 Jun 2012 10:01:23 +0100
From: matt <matt@ozlabs.org>
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Whee!  Let's try that again with MUA configured better...

On 2012-06-22 04:50, Michael Ellerman wrote:
> If the kernel is big enough (eg. allyesconfig), the linker may need 
> to
> switch TOCs when calling from the BPF JIT code out to the external
> helpers (skb_copy_bits() & bpf_internal_load_pointer_neg_helper()).
>
> In order to do that we need to leave space after the bl for the 
> linker
> to insert a reload of our TOC pointer.
>
> Signed-off-by: Michael Ellerman <michael@ellerman.id.au>

Oops, x2, and

Acked-by: Matt Evans <matt@ozlabs.org>

:-)


> ---
>  arch/powerpc/net/bpf_jit_64.S |    2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/powerpc/net/bpf_jit_64.S 
> b/arch/powerpc/net/bpf_jit_64.S
> index 55ba385..7d3a3b5 100644
> --- a/arch/powerpc/net/bpf_jit_64.S
> +++ b/arch/powerpc/net/bpf_jit_64.S
> @@ -105,6 +105,7 @@ sk_load_byte_msh_positive_offset:
>  	mr	r4, r_addr;					\
>  	li	r6, SIZE;					\
>  	bl	skb_copy_bits;					\
> +	nop;							\
>  	/* R3 = 0 on success */					\
>  	addi	r1, r1, BPF_PPC_SLOWPATH_FRAME;			\
>  	ld	r0, 16(r1);					\
> @@ -156,6 +157,7 @@ bpf_slow_path_byte_msh:
>  	mr	r4, r_addr;					\
>  	li	r5, SIZE;					\
>  	bl	bpf_internal_load_pointer_neg_helper;		\
> +	nop;							\
>  	/* R3 != 0 on success */				\
>  	addi	r1, r1, BPF_PPC_SLOWPATH_FRAME;			\
>  	ld	r0, 16(r1);					\