From: Dan Williams <dan.j.williams@intel.com>
To: Terry Bowman <terry.bowman@amd.com>, <alison.schofield@intel.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<bwidawsk@kernel.org>, <dan.j.williams@intel.com>,
<dave.jiang@intel.com>, <Jonathan.Cameron@huawei.com>,
<linux-cxl@vger.kernel.org>
Cc: rrichter@amd.com, terry.bowman@amd.com,
linux-pci@vger.kernel.org,
Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
linux-kernel@vger.kernel.org,
Oliver O'Halloran <oohall@gmail.com>,
bhelgaas@google.com, linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v3 6/6] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
Date: Mon, 17 Apr 2023 19:37:45 -0700 [thread overview]
Message-ID: <643e0279392f_1b66294d7@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20230411180302.2678736-7-terry.bowman@amd.com>
Terry Bowman wrote:
> From: Robert Richter <rrichter@amd.com>
>
> RCEC AER corrected and uncorrectable internal errors (CIE/UIE) are
> disabled by default. [1][2] Enable them to receive CXL downstream port
> errors of a Restricted CXL Host (RCH).
>
> [1] CXL 3.0 Spec, 12.2.1.1 - RCH Downstream Port Detected Errors
> [2] PCIe Base Spec 6.0, 7.8.4.3 Uncorrectable Error Mask Register,
> 7.8.4.6 Correctable Error Mask Register
My comment on patch5 to make CXL link details a first class property of a
'struct pci_dev':
http://lore.kernel.org/r/643debf5af445_1b66294f4@dwillia2-xfh.jf.intel.com.notmuch/
...also applies here.
Other than that nothing more from me on this one beyond what Bjorn and
Jonathan have said. I do agree with Robert about being cautious about
only enabling this for CXL devices for now and not all internal errors
for all AER capable devices globally. The rationale being that CXL
devices are a new link on top of PCIe and abuse/reuse internal errors
when they are conceptually functionally equivalent to PCIe link errors.
prev parent reply other threads:[~2023-04-18 2:38 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230411180302.2678736-1-terry.bowman@amd.com>
2023-04-11 18:03 ` [PATCH v3 5/6] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-04-12 22:02 ` Bjorn Helgaas
2023-04-13 11:40 ` Robert Richter
2023-04-14 21:32 ` Bjorn Helgaas
2023-04-17 22:00 ` Robert Richter
2023-04-19 14:17 ` Robert Richter
2023-04-14 12:19 ` Jonathan Cameron
2023-04-14 14:35 ` Robert Richter
2023-04-17 16:54 ` Jonathan Cameron
2023-04-17 20:36 ` Robert Richter
2023-04-18 1:01 ` Dan Williams
2023-04-19 13:30 ` Robert Richter
2023-04-11 18:03 ` [PATCH v3 6/6] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-04-12 21:29 ` Bjorn Helgaas
2023-04-13 13:38 ` Robert Richter
2023-04-13 17:05 ` Jonathan Cameron
2023-04-14 11:58 ` Robert Richter
2023-04-14 21:49 ` Bjorn Helgaas
2023-04-13 17:01 ` Jonathan Cameron
2023-04-13 22:52 ` Ira Weiny
2023-04-14 11:21 ` Robert Richter
2023-04-14 11:55 ` Jonathan Cameron
2023-04-14 14:47 ` Robert Richter
2023-04-18 2:37 ` Dan Williams [this message]
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