From: Kumar Gala <galak@kernel.crashing.org>
To: bwarren@qstreams.com
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: GPIO endianness on MPC8349
Date: Mon, 10 Apr 2006 15:06:33 -0500 [thread overview]
Message-ID: <6518EE00-812C-4839-AF00-AA976C35E799@kernel.crashing.org> (raw)
In-Reply-To: <1144698501.972.103.camel@saruman.qstreams.net>
On Apr 10, 2006, at 2:48 PM, Ben Warren wrote:
> Hello,
>
> I'm a noobie to this CPU, and am utterly confused with how the bits
> are
> ordered on the GPIO ports. I imagine it's the same as all Freescale
> PPCs, but who knows. Anyway...
>
> Using an MPC8349MDS eval board, I have one LED to play with. From the
> schematic, it's connected to GPIO1[1]. From other processors that
> I've
> worked with, I would have expected to toggle it with either 0x40000000
> (IBM 405) or 0x00000002 (68360). Nope. To make this bit move, I mess
> with bit 0x00000040 in the appropriate DAT register. This leads me to
> believe that either the bit ordering is something
> like ...89abcdef01234567 (sorry for the confusing notation, but
> hopefully it makes sense) or the schematic has a typo. Since I'm
> trying
> to write a generic GPIO handler, I'd like to have a little
> confidence in
> my extrapolation from a single point.
>
> Can anybody shed some light on this?
This is because the Freescale docs are misleading. If you look at
the schematic you will see the LED is wired to GPIO1[5] which makes
sense for the 0x40 value you have to use.
- kumar
next prev parent reply other threads:[~2006-04-10 20:06 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-04-10 19:48 GPIO endianness on MPC8349 Ben Warren
2006-04-10 20:06 ` Kumar Gala [this message]
2006-04-10 20:20 ` Ben Warren
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