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[2003:cb:c706:f900:aa79:cd25:e0:32d1]) by smtp.gmail.com with ESMTPSA id k9-20020adfd849000000b00203d18bf389sm1341573wrl.17.2022.03.16.04.06.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Mar 2022 04:06:18 -0700 (PDT) Message-ID: <655640d5-3886-c4fb-6531-3148fd90e3d5@redhat.com> Date: Wed, 16 Mar 2022 12:06:16 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.6.2 Subject: Re: [PATCH v1 5/7] s390/pgtable: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE To: Gerald Schaefer References: <20220315141837.137118-1-david@redhat.com> <20220315141837.137118-6-david@redhat.com> <20220315172102.771bd2cf@thinkpad> <8b13b6c0-78d4-48e3-06f0-ec0680d013a9@redhat.com> <55b6b582-51ca-b869-2055-674fe4c563e6@redhat.com> <20220316115654.12823b78@thinkpad> From: David Hildenbrand Organization: Red Hat In-Reply-To: <20220316115654.12823b78@thinkpad> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=david@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: x86@kernel.org, Jan Kara , Catalin Marinas , Yang Shi , Dave Hansen , Peter Xu , Michal Hocko , linux-mm@kvack.org, Donald Dutile , Liang Zhang , Borislav Petkov , Alexander Gordeev , Will Deacon , Christoph Hellwig , Paul Mackerras , Andrea Arcangeli , linux-s390@vger.kernel.org, Vasily Gorbik , Rik van Riel , Hugh Dickins , Matthew Wilcox , Mike Rapoport , Ingo Molnar , linux-arm-kernel@lists.infradead.org, Jason Gunthorpe , David Rientjes , Christian Borntraeger , Pedro Gomes , Jann Horn , John Hubbard , Heiko Carstens , Shakeel Butt , Oleg Nesterov , Thomas Gleixner , Vlastimil Babka , Oded Gabbay , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Nadav Amit , Andrew Morton , Linus Torvalds , Roman Gushchin , "Kirill A . Shutemov" , Mike Kravetz Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 16.03.22 11:56, Gerald Schaefer wrote: > On Tue, 15 Mar 2022 18:12:16 +0100 > David Hildenbrand wrote: > >> On 15.03.22 17:58, David Hildenbrand wrote: >>> >>>>> This would mean that it is not OK to have bit 52 not zero for swap PTEs. >>>>> But if I read the POP correctly, all bits except for the DAT-protection >>>>> would be ignored for invalid PTEs, so maybe this comment needs some update >>>>> (for both bits 52 and also 55). >>>>> >>>>> Heiko might also have some more insight. >>>> >>>> Indeed, I wonder why we should get a specification exception when the >>>> PTE is invalid. I'll dig a bit into the PoP. >>> >>> SA22-7832-12 6-46 ("Translation-Specification Exception") is clearer >>> >>> "The page-table entry used for the translation is >>> valid, and bit position 52 does not contain zero." >>> >>> "The page-table entry used for the translation is >>> valid, EDAT-1 does not apply, the instruction-exe- >>> cution-protection facility is not installed, and bit >>> position 55 does not contain zero. It is model >>> dependent whether this condition is recognized." >>> >> >> I wonder if the following matches reality: >> >> diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h >> index 008a6c856fa4..6a227a8c3712 100644 >> --- a/arch/s390/include/asm/pgtable.h >> +++ b/arch/s390/include/asm/pgtable.h >> @@ -1669,18 +1669,16 @@ static inline int has_transparent_hugepage(void) >> /* >> * 64 bit swap entry format: >> * A page-table entry has some bits we have to treat in a special way. >> - * Bits 52 and bit 55 have to be zero, otherwise a specification >> - * exception will occur instead of a page translation exception. The >> - * specification exception has the bad habit not to store necessary >> - * information in the lowcore. >> * Bits 54 and 63 are used to indicate the page type. >> * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 >> - * This leaves the bits 0-51 and bits 56-62 to store type and offset. >> - * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 >> - * for the offset. >> - * | offset |01100|type |00| >> + * | offset |XX1XX|type |S0| >> * |0000000000111111111122222222223333333333444444444455|55555|55566|66| >> * |0123456789012345678901234567890123456789012345678901|23456|78901|23| >> + * >> + * Bits 0-51 store the offset. >> + * Bits 57-62 store the type. >> + * Bit 62 (S) is used for softdirty tracking. >> + * Bits 52, 53, 55 and 56 (X) are unused. >> */ >> >> #define __SWP_OFFSET_MASK ((1UL << 52) - 1) >> >> >> I'm not sure why bit 53 was indicated as "1" and bit 55 was indicated as >> "0". At least for 52 and 55 there was a clear description. > > Bit 53 is the invalid bit, and that is always 1 for swap ptes, in addition Ah, right, I missed the meaning of bot 53 because this documentation is just sub-optimal. > to protection bit 54. Bit 55, along with bit 52, has to be zero according > to the (potentially deprecated) comment. Yeah, that 52/55 comment is just wrong when dealing with invalid PTEs. > > It is interesting that bit 56 seems to be unused, at least according > to the comment, but that would also mention bit 62 as unused, so that > clearly needs some update. I currently have the following cleanup patch: >From a4a8db2920e035e90a410b9170829326bb1fab92 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Tue, 15 Mar 2022 18:14:09 +0100 Subject: [PATCH] s390/pgtable: cleanup description of swp pte layout Bit 52 and bit 55 don't have to be zero: they only trigger a translation-specifiation exception if the PTE is marked as valid, which is not the case for swap ptes. Document which bits are used for what, and which ones are unused. Signed-off-by: David Hildenbrand --- arch/s390/include/asm/pgtable.h | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index 008a6c856fa4..64fbe5fd3853 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -1669,18 +1669,17 @@ static inline int has_transparent_hugepage(void) /* * 64 bit swap entry format: * A page-table entry has some bits we have to treat in a special way. - * Bits 52 and bit 55 have to be zero, otherwise a specification - * exception will occur instead of a page translation exception. The - * specification exception has the bad habit not to store necessary - * information in the lowcore. - * Bits 54 and 63 are used to indicate the page type. + * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte + * as invalid. * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200 - * This leaves the bits 0-51 and bits 56-62 to store type and offset. - * We use the 5 bits from 57-61 for the type and the 52 bits from 0-51 - * for the offset. - * | offset |01100|type |00| + * | offset |X11XX|type |S0| * |0000000000111111111122222222223333333333444444444455|55555|55566|66| * |0123456789012345678901234567890123456789012345678901|23456|78901|23| + * + * Bits 0-51 store the offset. + * Bits 57-61 store the type. + * Bit 62 (S) is used for softdirty tracking. + * Bits 52, 55 and 56 (X) are unused. */ #define __SWP_OFFSET_MASK ((1UL << 52) - 1) -- 2.35.1 > > If bit 56 could be used for _PAGE_SWP_EXCLUSIVE, that would be better > than stealing a bit from the offset, or using potentially dangerous > bit 52. It is defined as _PAGE_UNUSED and only used for kvm, not sure > if this is also relevant for swap ptes, similar to bit 62. I don't think it is, and I also don't think there is anything wrong with reusing bit 52. > > Adding Christian on cc, maybe he has some insight on _PAGE_UNUSED > bit 56 and swap ptes. -- Thanks, David / dhildenb