---

From: Mike Hench
Sent: Wednesday, March 19, 2008 10:22 AM
To: 'mhench@wi.rr.com'
Subject: [PATCH] MPC813 NAND fixes

Fix a race condition in fsl_elbc_run_command

Declare a variable written by an interrupt volatile.

Added parentheses to make timeout non-zero

Fix incorrect usage of clearbits32 that bashed option register

Remove work around for bashed register

Signed-off-by: Mike Hench <mhench@elutions.com>

---

--- linux-2.6.25-rc5.orig/drivers/mtd/nand/fsl_elbc_nand.c   2008-03-10 00:22:27.000000000 -0500

+++ linux-2.6.25-rc5/drivers/mtd/nand/fsl_elbc_nand.c       2008-03-19 10:08:22.000000000 -0500

@@ -264,7 +264,7 @@ struct fsl_elbc_ctrl {

            struct elbc_regs __iomem *regs;

            int irq;

            wait_queue_head_t irq_wait;

-           unsigned int irq_status; /* status read from LTESR by irq handler */

+          volatile unsigned int irq_status; /* status read from LTESR by irq handler */

            u8 __iomem *addr;        /* Address of assigned FCM buffer        */

            unsigned int page;       /* Last page written to / read from      */

            unsigned int read_bytes; /* Number of bytes read during command   */

@@ -379,13 +379,13 @@ static int fsl_elbc_run_command(struct m

                     in_be32(&lbc->fbar), in_be32(&lbc->fpar),

                     in_be32(&lbc->fbcr), priv->bank);

+          ctrl->irq_status = 0;

            /* execute special operation */

            out_be32(&lbc->lsor, priv->bank);

            /* wait for FCM complete flag or timeout */

-           ctrl->irq_status = 0;

            wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,

-                              FCM_TIMEOUT_MSECS * HZ/1000);

+                             (FCM_TIMEOUT_MSECS * HZ)/1000);

            ctrl->status = ctrl->irq_status;

            /* store mdr value in case it was needed */

@@ -861,7 +861,7 @@ static int fsl_elbc_chip_init_tail(struc

            /* adjust Option Register and ECC to match Flash page size */

            if (mtd->writesize == 512) {

                        priv->page_size = 0;

-                       clrbits32(&lbc->bank[priv->bank].or, ~OR_FCM_PGS);

+                      clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);

            } else if (mtd->writesize == 2048) {

                        priv->page_size = 1;

                        setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);

@@ -882,11 +882,6 @@ static int fsl_elbc_chip_init_tail(struc

                        return -1;

            }

-           /* The default u-boot configuration on MPC8313ERDB causes errors;

-           * more delay is needed.  This should be safe for other boards

-           * as well.

-           */

-           setbits32(&lbc->bank[priv->bank].or, 0x70);

            return 0;

 }