From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from owa.engagenet.com (unknown [66.195.150.24]) by ozlabs.org (Postfix) with ESMTP id 39A20DDF28 for ; Thu, 20 Mar 2008 02:44:38 +1100 (EST) MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C889D5.DBA0B662" Subject: [PATCH] MPC813 NAND fixes Date: Wed, 19 Mar 2008 10:28:19 -0500 Message-ID: <6629C06B144F5C4098DFF95C4FF9DAF702BA1D02@mailsrv.engagenet.com> From: "Mike Hench" To: List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , This is a multi-part message in MIME format. ------_=_NextPart_001_01C889D5.DBA0B662 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable =20 =20 ________________________________ From: Mike Hench=20 Sent: Wednesday, March 19, 2008 10:22 AM To: 'mhench@wi.rr.com' Subject: [PATCH] MPC813 NAND fixes =20 Fix a race condition in fsl_elbc_run_command Declare a variable written by an interrupt volatile. Added parentheses to make timeout non-zero Fix incorrect usage of clearbits32 that bashed option register Remove work around for bashed register =20 Signed-off-by: Mike Hench =20 --- =20 --- linux-2.6.25-rc5.orig/drivers/mtd/nand/fsl_elbc_nand.c 2008-03-10 00:22:27.000000000 -0500 +++ linux-2.6.25-rc5/drivers/mtd/nand/fsl_elbc_nand.c 2008-03-19 10:08:22.000000000 -0500 @@ -264,7 +264,7 @@ struct fsl_elbc_ctrl { struct elbc_regs __iomem *regs; int irq; wait_queue_head_t irq_wait; - unsigned int irq_status; /* status read from LTESR by irq handler */ + volatile unsigned int irq_status; /* status read from LTESR by irq handler */ u8 __iomem *addr; /* Address of assigned FCM buffer */ unsigned int page; /* Last page written to / read from */ unsigned int read_bytes; /* Number of bytes read during command */ @@ -379,13 +379,13 @@ static int fsl_elbc_run_command(struct m in_be32(&lbc->fbar), in_be32(&lbc->fpar), in_be32(&lbc->fbcr), priv->bank); =20 + ctrl->irq_status =3D 0; /* execute special operation */ out_be32(&lbc->lsor, priv->bank); =20 /* wait for FCM complete flag or timeout */ - ctrl->irq_status =3D 0; wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, - FCM_TIMEOUT_MSECS * HZ/1000); + (FCM_TIMEOUT_MSECS * HZ)/1000); ctrl->status =3D ctrl->irq_status; =20 /* store mdr value in case it was needed */ @@ -861,7 +861,7 @@ static int fsl_elbc_chip_init_tail(struc /* adjust Option Register and ECC to match Flash page size */ if (mtd->writesize =3D=3D 512) { priv->page_size =3D 0; - clrbits32(&lbc->bank[priv->bank].or, ~OR_FCM_PGS); + clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); } else if (mtd->writesize =3D=3D 2048) { priv->page_size =3D 1; setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); @@ -882,11 +882,6 @@ static int fsl_elbc_chip_init_tail(struc return -1; } =20 - /* The default u-boot configuration on MPC8313ERDB causes errors; - * more delay is needed. This should be safe for other boards - * as well. - */ - setbits32(&lbc->bank[priv->bank].or, 0x70); return 0; } =20 ------_=_NextPart_001_01C889D5.DBA0B662 Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

 

 

From: Mike = Hench
Sent: Wednesday, March = 19, 2008 10:22 AM
To: 'mhench@wi.rr.com'
Subject: [PATCH] MPC813 = NAND fixes

 

Fix a race condition in = fsl_elbc_run_command

Declare a variable written by an interrupt = volatile.

Added parentheses to make timeout = non-zero

Fix incorrect usage of clearbits32 that bashed option register

Remove work around for bashed register

 

Signed-off-by: Mike = Hench <mhench@elutions.com>

 

---

 

--- linux-2.6.25-rc5.orig/drivers/mtd/nand/fsl_elbc_nand.c   = 2008-03-10 00:22:27.000000000 -0500

+++ linux-2.6.25-rc5/drivers/mtd/nand/fsl_elbc_nand.c    =    2008-03-19 10:08:22.000000000 -0500

@@ -264,7 +264,7 @@ struct fsl_elbc_ctrl = {

         =    struct elbc_regs __iomem *regs;

         =    int irq;

         =    wait_queue_head_t irq_wait;

-         = ;  unsigned int irq_status; /* status read from LTESR by irq handler = */

+         = ; volatile unsigned int irq_status; /* status read from LTESR by irq = handler */

         =    u8 __iomem *addr;        /* Address = of assigned FCM buffer        = */

         =    unsigned int page;       /* Last page = written to / read from      = */

         =    unsigned int read_bytes; /* Number of bytes read during = command   */

@@ -379,13 +379,13 @@ static int = fsl_elbc_run_command(struct m

         =             = in_be32(&lbc->fbar), in_be32(&lbc->fpar),

         =             = in_be32(&lbc->fbcr), priv->bank);

 

+         = ; ctrl->irq_status =3D 0;

         =    /* execute special operation */

         =    out_be32(&lbc->lsor, priv->bank);

 

         =    /* wait for FCM complete flag or timeout */

-         = ;  ctrl->irq_status =3D 0;

         =    wait_event_timeout(ctrl->irq_wait, = ctrl->irq_status,

-         = ;              &= nbsp;      FCM_TIMEOUT_MSECS * HZ/1000);

+         = ;             &= nbsp;      (FCM_TIMEOUT_MSECS * HZ)/1000);

         =    ctrl->status =3D ctrl->irq_status;

 

         =    /* store mdr value in case it was needed */

@@ -861,7 +861,7 @@ static int = fsl_elbc_chip_init_tail(struc

         =    /* adjust Option Register and ECC to match Flash page size = */

         =    if (mtd->writesize =3D=3D 512) {

         =             &= nbsp;  priv->page_size =3D 0;

-         = ;            =   clrbits32(&lbc->bank[priv->bank].or, = ~OR_FCM_PGS);

+         = ;            = clrbits32(&lbc->bank[priv->bank].or, = OR_FCM_PGS);

         =    } else if (mtd->writesize =3D=3D 2048) {

         =             &= nbsp;  priv->page_size =3D 1;

         =             &= nbsp;  setbits32(&lbc->bank[priv->bank].or, = OR_FCM_PGS);

@@ -882,11 +882,6 @@ static int = fsl_elbc_chip_init_tail(struc

         =             &= nbsp;  return -1;

         =    }

 

-         = ;  /* The default u-boot configuration on MPC8313ERDB causes = errors;

-         = ;  * more delay is needed.  This should be safe for other = boards

-         = ;  * as well.

-         = ;  */

-         = ;  setbits32(&lbc->bank[priv->bank].or, = 0x70);

         =    return 0;

 }

 

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