From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40QBbj1SqPzF21N for ; Tue, 17 Apr 2018 14:09:53 +1000 (AEST) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w3H48rBo071546 for ; Tue, 17 Apr 2018 00:09:50 -0400 Received: from e06smtp12.uk.ibm.com (e06smtp12.uk.ibm.com [195.75.94.108]) by mx0a-001b2d01.pphosted.com with ESMTP id 2hd491kphk-1 (version=TLSv1.2 cipher=AES256-SHA256 bits=256 verify=NOT) for ; Tue, 17 Apr 2018 00:09:50 -0400 Received: from localhost by e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 17 Apr 2018 05:09:48 +0100 Subject: Re: [PATCH 1/7] powerpc: Add TIDR CPU feature for Power9 To: "Alastair D'Silva" , linuxppc-dev@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, mikey@neuling.org, vaibhav@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com, malat@debian.org, felix@linux.vnet.ibm.com, pombredanne@nexb.com, sukadev@linux.vnet.ibm.com, npiggin@gmail.com, gregkh@linuxfoundation.org, arnd@arndb.de, fbarrat@linux.vnet.ibm.com, corbet@lwn.net, "Alastair D'Silva" References: <20180417020950.21446-1-alastair@au1.ibm.com> <20180417020950.21446-2-alastair@au1.ibm.com> From: Andrew Donnellan Date: Tue, 17 Apr 2018 14:09:41 +1000 MIME-Version: 1.0 In-Reply-To: <20180417020950.21446-2-alastair@au1.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Message-Id: <68ec9aff-b523-dd30-cd73-42dc8c792ba1@au1.ibm.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On 17/04/18 12:09, Alastair D'Silva wrote: > diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h > index be8c9fa23983..5b03d8a82409 100644 > --- a/arch/powerpc/include/asm/switch_to.h > +++ b/arch/powerpc/include/asm/switch_to.h > @@ -94,6 +94,5 @@ static inline void clear_task_ebb(struct task_struct *t) > extern int set_thread_uses_vas(void); > > extern int set_thread_tidr(struct task_struct *t); > -extern void clear_thread_tidr(struct task_struct *t); This hunk looks like it really belongs in patch 3. Apart from that, I'm not really familiar with the CPU features code but nothing seems overly wrong... Reviewed-by: Andrew Donnellan -- Andrew Donnellan OzLabs, ADL Canberra andrew.donnellan@au1.ibm.com IBM Australia Limited