Re: [PATCH v2] powerpc: Add force enable of DAWR on P9 option

["Cédric Le Goater" <clg@kaod.org>]

Hello Michael,


> --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> @@ -822,18 +822,21 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
>  	mtspr	SPRN_IAMR, r5
>  	mtspr	SPRN_PSPB, r6
>  	mtspr	SPRN_FSCR, r7
> -	ld	r5, VCPU_DAWR(r4)
> -	ld	r6, VCPU_DAWRX(r4)
> -	ld	r7, VCPU_CIABR(r4)
> -	ld	r8, VCPU_TAR(r4)
>  	/*
>  	 * Handle broken DAWR case by not writing it. This means we
>  	 * can still store the DAWR register for migration.
>  	 */
> -BEGIN_FTR_SECTION
> +	LOAD_REG_ADDR(r5, dawr_force_enable)
> +	lbz	r5, 0(r5)
> +	cmpdi	r5, 0
> +	beq	1f
> +	ld	r5, VCPU_DAWR(r4)
> +	ld	r6, VCPU_DAWRX(r4)
>  	mtspr	SPRN_DAWR, r5
>  	mtspr	SPRN_DAWRX, r6
> -END_FTR_SECTION_IFSET(CPU_FTR_DAWR)
> +1:
> +	ld	r7, VCPU_CIABR(r4)
> +	ld	r8, VCPU_TAR(r4)
>  	mtspr	SPRN_CIABR, r7
>  	mtspr	SPRN_TAR, r8
>  	ld	r5, VCPU_IC(r4)
> @@ -2513,11 +2516,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
>  	blr
>  
>  2:
> -BEGIN_FTR_SECTION
> -	/* POWER9 with disabled DAWR */
> +	LOAD_REG_ADDR(r11, dawr_force_enable)
> +	lbz	r11, 0(r11)
> +	cmpdi	r11, 0
>  	li	r3, H_HARDWARE
> -	blr
> -END_FTR_SECTION_IFCLR(CPU_FTR_DAWR)
> +	beqlr

Why is this a 'beqlr' ? Shouldn't it be a blr ? 

C.

>  	/* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
>  	rlwimi	r5, r4, 5, DAWRX_DR | DAWRX_DW
>  	rlwimi	r5, r4, 2, DAWRX_WT
>