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Tue, 22 Sep 2020 06:53:37 +0000 (GMT) Received: from localhost.localdomain (unknown [9.85.86.236]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Sep 2020 06:53:37 +0000 (GMT) Subject: Re: [PATCH V2] powerpc/perf: Exclude pmc5/6 from the irrelevant PMU group constraints To: Athira Rajeev , mpe@ellerman.id.au References: <1600672204-1610-1-git-send-email-atrajeev@linux.vnet.ibm.com> From: Madhavan Srinivasan Message-ID: <69661e2d-2e81-35f0-604d-905cbbc5f7de@linux.ibm.com> Date: Tue, 22 Sep 2020 12:23:36 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <1600672204-1610-1-git-send-email-atrajeev@linux.vnet.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-22_05:2020-09-21, 2020-09-22 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 adultscore=0 clxscore=1015 malwarescore=0 mlxscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2009220052 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: maddy@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 9/21/20 12:40 PM, Athira Rajeev wrote: > PMU counter support functions enforces event constraints for group of > events to check if all events in a group can be monitored. Incase of > event codes using PMC5 and PMC6 ( 500fa and 600f4 respectively ), > not all constraints are applicable, say the threshold or sample bits. > But current code includes pmc5 and pmc6 in some group constraints (like > IC_DC Qualifier bits) which is actually not applicable and hence results > in those events not getting counted when scheduled along with group of > other events. Patch fixes this by excluding PMC5/6 from constraints > which are not relevant for it. Changes looks fine to me. Reviewed-by: Madhavan Srinivasan we need to CC this in Stable too. > Fixes: 7ffd948 ("powerpc/perf: factor out power8 pmu functions") > Signed-off-by: Athira Rajeev > --- > Changes in v2: > - Added a block comment in the fix path explaining > why the change is needed. > > arch/powerpc/perf/isa207-common.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c > index 964437a..12153da 100644 > --- a/arch/powerpc/perf/isa207-common.c > +++ b/arch/powerpc/perf/isa207-common.c > @@ -288,6 +288,15 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) > > mask |= CNST_PMC_MASK(pmc); > value |= CNST_PMC_VAL(pmc); > + > + /* > + * PMC5 and PMC6 are used to count cycles and instructions > + * and these doesnot support most of the constraint bits. > + * Add a check to exclude PMC5/6 from most of the constraints > + * except for ebb/bhrb. > + */ > + if (pmc >= 5) > + goto ebb_bhrb; > } > > if (pmc <= 4) { > @@ -357,6 +366,7 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) > } > } > > +ebb_bhrb: > if (!pmc && ebb) > /* EBB events must specify the PMC */ > return -1;