[PATCH v2 3/9] 8641HPCN: Add PCI-Express link training status check

[PATCH v2 3/9] 8641HPCN: Add PCI-Express link training status check

[Jon Loeliger]

From: Zhang Wei <wei.zhang@freescale.com>

Avoid system halt while the link training is fault.

Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
---
 arch/powerpc/platforms/86xx/pci.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
index 7efae7c..07ff52c 100644
--- a/arch/powerpc/platforms/86xx/pci.c
+++ b/arch/powerpc/platforms/86xx/pci.c
@@ -122,7 +122,6 @@ static void __init
 mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
 {
 	u16 cmd;
-	unsigned int temps;
 
 	DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
 			pcie_offset, pcie_size);
@@ -140,6 +139,9 @@ int mpc86xx_exclude_device(u_char bus, u_char devfn)
 	return PCIBIOS_SUCCESSFUL;
 }
 
+#define PCIE_LTSSM	0x04000004	/* PCIe Link Training and Status */
+#define PCIE_LTSSM_L0	0x16		/* L0 state */
+
 int __init add_bridge(struct device_node *dev)
 {
 	int len;
@@ -148,12 +150,20 @@ int __init add_bridge(struct device_node *dev)
 	const int *bus_range;
 	int has_address = 0;
 	int primary = 0;
+	void *pcicfg_addr;
 
 	DBG("Adding PCIE host bridge %s\n", dev->full_name);
 
 	/* Fetch host bridge registers address */
 	has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
 
+	/* Probe the hose link training status */
+	pcicfg_addr = ioremap(rsrc.start, 0x1000);
+	out_be32(pcicfg_addr, 0x80000000 | PCIE_LTSSM);
+	if (in_le16(pcicfg_addr + 4) < PCIE_LTSSM_L0)
+		return -ENXIO;
+	iounmap(pcicfg_addr);
+
 	/* Get bus range if any */
 	bus_range = of_get_property(dev, "bus-range", &len);
 	if (bus_range == NULL || len < 2 * sizeof(int))
-- 
1.5.0.3

Re: [PATCH v2 3/9] 8641HPCN: Add PCI-Express link training status check

[Kumar Gala]

On Jun 4, 2007, at 5:30 PM, Jon Loeliger wrote:

> From: Zhang Wei <wei.zhang@freescale.com>
>
> Avoid system halt while the link training is fault.
>
> Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Jon Loeliger <jdl@freescale.com>
> ---
>  arch/powerpc/platforms/86xx/pci.c |   12 +++++++++++-
>  1 files changed, 11 insertions(+), 1 deletions(-)
>
> diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/ 
> platforms/86xx/pci.c
> index 7efae7c..07ff52c 100644
> --- a/arch/powerpc/platforms/86xx/pci.c
> +++ b/arch/powerpc/platforms/86xx/pci.c
> @@ -122,7 +122,6 @@ static void __init
>  mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset,  
> u32 pcie_size)
>  {
>  	u16 cmd;
> -	unsigned int temps;
>
>  	DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
>  			pcie_offset, pcie_size);
> @@ -140,6 +139,9 @@ int mpc86xx_exclude_device(u_char bus, u_char  
> devfn)
>  	return PCIBIOS_SUCCESSFUL;
>  }
>
> +#define PCIE_LTSSM	0x04000004	/* PCIe Link Training and Status */
> +#define PCIE_LTSSM_L0	0x16		/* L0 state */
> +
>  int __init add_bridge(struct device_node *dev)
>  {
>  	int len;
> @@ -148,12 +150,20 @@ int __init add_bridge(struct device_node *dev)
>  	const int *bus_range;
>  	int has_address = 0;
>  	int primary = 0;
> +	void *pcicfg_addr;
>
>  	DBG("Adding PCIE host bridge %s\n", dev->full_name);
>
>  	/* Fetch host bridge registers address */
>  	has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
>
> +	/* Probe the hose link training status */
> +	pcicfg_addr = ioremap(rsrc.start, 0x1000);
> +	out_be32(pcicfg_addr, 0x80000000 | PCIE_LTSSM);
> +	if (in_le16(pcicfg_addr + 4) < PCIE_LTSSM_L0)
> +		return -ENXIO;
> +	iounmap(pcicfg_addr);

Is there a reason we don't do this with early_read_config_word, while  
it requires we alloc the hose, it seems cleaner.  If this fails, I  
think the memory wasted on the hose is a minor concern.  (assuming my  
other patch to support extended regs in pci indirect).

- k