* [PATCH 1/3] PPC440EP SoC and Bamboo board support
@ 2005-03-15 17:17 Wade Farnsworth
2005-03-15 18:41 ` Eugene Surovegin
` (3 more replies)
0 siblings, 4 replies; 35+ messages in thread
From: Wade Farnsworth @ 2005-03-15 17:17 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 211 bytes --]
Hello all,
This adds support for the IBM/AMCC PPC440EP SoC and the Bamboo reference
board. Any comments would be appreciated.
Regards,
Wade Farnsworth
Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
[-- Attachment #2: ibm440ep-ppc.patch --]
[-- Type: text/x-patch, Size: 82336 bytes --]
diff -uprN linux-2.6.11-bk7/arch/ppc/boot/simple/Makefile linux-2.6.11-bk7-440ep/arch/ppc/boot/simple/Makefile
--- linux-2.6.11-bk7/arch/ppc/boot/simple/Makefile 2005-03-11 16:25:16.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/boot/simple/Makefile 2005-03-14 09:49:18.000000000 -0700
@@ -61,6 +61,12 @@ zimageinitrd-$(CONFIG_IBM_OPENBIOS) := z
end-$(CONFIG_EMBEDDEDBOOT) := embedded
misc-$(CONFIG_EMBEDDEDBOOT) := misc-embedded.o
+ zimage-$(CONFIG_BAMBOO) := zImage-TREE
+zimageinitrd-$(CONFIG_BAMBOO) := zImage.initrd-TREE
+ end-$(CONFIG_BAMBOO) := bamboo
+ entrypoint-$(CONFIG_BAMBOO) := 0x01000000
+ extra.o-$(CONFIG_BAMBOO) := pibs.o
+
zimage-$(CONFIG_EBONY) := zImage-TREE
zimageinitrd-$(CONFIG_EBONY) := zImage.initrd-TREE
end-$(CONFIG_EBONY) := ebony
diff -uprN linux-2.6.11-bk7/arch/ppc/boot/simple/pibs.c linux-2.6.11-bk7-440ep/arch/ppc/boot/simple/pibs.c
--- linux-2.6.11-bk7/arch/ppc/boot/simple/pibs.c 2005-03-02 00:38:08.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/boot/simple/pibs.c 2005-03-11 16:26:19.000000000 -0700
@@ -91,9 +91,11 @@ load_kernel(unsigned long load_addr, int
mac64 = simple_strtoull((char *)PIBS_MAC_BASE, 0, 16);
memcpy(hold_residual->bi_enetaddr, (char *)&mac64+2, 6);
-#ifdef CONFIG_440GX
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP)
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET), 0, 16);
memcpy(hold_residual->bi_enet1addr, (char *)&mac64+2, 6);
+#endif
+#ifdef CONFIG_440GX
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*2), 0, 16);
memcpy(hold_residual->bi_enet2addr, (char *)&mac64+2, 6);
mac64 = simple_strtoull((char *)(PIBS_MAC_BASE+PIBS_MAC_OFFSET*3), 0, 16);
diff -uprN linux-2.6.11-bk7/arch/ppc/configs/bamboo_defconfig linux-2.6.11-bk7-440ep/arch/ppc/configs/bamboo_defconfig
--- linux-2.6.11-bk7/arch/ppc/configs/bamboo_defconfig 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/configs/bamboo_defconfig 2005-03-11 16:26:19.000000000 -0700
@@ -0,0 +1,910 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.11-rc5
+# Wed Mar 2 16:46:31 2005
+#
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_HAVE_DEC_LOCK=y
+CONFIG_PPC=y
+CONFIG_PPC32=y
+CONFIG_GENERIC_NVRAM=y
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_CLEAN_COMPILE=y
+CONFIG_BROKEN_ON_SMP=y
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+# CONFIG_AUDIT is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_HOTPLUG is not set
+CONFIG_KOBJECT_UEVENT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_EMBEDDED=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SHMEM=y
+CONFIG_CC_ALIGN_FUNCTIONS=0
+CONFIG_CC_ALIGN_LABELS=0
+CONFIG_CC_ALIGN_LOOPS=0
+CONFIG_CC_ALIGN_JUMPS=0
+# CONFIG_TINY_SHMEM is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_OBSOLETE_MODPARM=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Processor
+#
+# CONFIG_6xx is not set
+# CONFIG_40x is not set
+CONFIG_44x=y
+# CONFIG_POWER3 is not set
+# CONFIG_POWER4 is not set
+# CONFIG_8xx is not set
+# CONFIG_E500 is not set
+CONFIG_BOOKE=y
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_CPU_FREQ is not set
+CONFIG_4xx=y
+
+#
+# IBM 4xx options
+#
+# CONFIG_EBONY is not set
+# CONFIG_LUAN is not set
+# CONFIG_OCOTEA is not set
+CONFIG_BAMBOO=y
+CONFIG_440EP=y
+CONFIG_440_FPU=y
+CONFIG_IBM440EP_ERR42=y
+CONFIG_IBM_OCP=y
+# CONFIG_PPC4xx_DMA is not set
+CONFIG_PPC_GEN550=y
+# CONFIG_PM is not set
+CONFIG_NOT_COHERENT_CACHE=y
+
+#
+# Platform options
+#
+# CONFIG_PC_KEYBOARD is not set
+# CONFIG_SMP is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="ip=on"
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCI_LEGACY_PROC is not set
+# CONFIG_PCI_NAMES is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x01000000
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_LBD is not set
+# CONFIG_CDROM_PKTCDVD is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=y
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+# CONFIG_IDEDMA_PCI_AUTO is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+CONFIG_BLK_DEV_CMD64X=y
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+# CONFIG_BLK_DEV_SD is not set
+CONFIG_CHR_DEV_ST=y
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+CONFIG_SCSI_QLA2XXX=y
+# CONFIG_SCSI_QLA21XX is not set
+# CONFIG_SCSI_QLA22XX is not set
+# CONFIG_SCSI_QLA2300 is not set
+# CONFIG_SCSI_QLA2322 is not set
+# CONFIG_SCSI_QLA6312 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+
+#
+# Networking support
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+# CONFIG_NETLINK_DEV is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_IP_TCPDIAG=y
+# CONFIG_IP_TCPDIAG_IPV6 is not set
+
+#
+# IP: Virtual Server Configuration
+#
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_CONNTRACK_MARK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+# CONFIG_NET_CLS_ROUTE is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_EMAC=y
+# CONFIG_IBM_EMAC_ERRMSG is not set
+CONFIG_IBM_EMAC_RXB=128
+CONFIG_IBM_EMAC_TXB=128
+CONFIG_IBM_EMAC_FGAP=8
+CONFIG_IBM_EMAC_SKBRES=0
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+CONFIG_EEPRO100=y
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+CONFIG_NATSEMI=y
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+# CONFIG_E1000_NAPI is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input I/O drivers
+#
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_BANDWIDTH is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_BLUETOOTH_TTY is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_STORAGE is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_AIPTEK is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_KBTAB is not set
+# CONFIG_USB_POWERMATE is not set
+# CONFIG_USB_MTOUCH is not set
+# CONFIG_USB_EGALAX is not set
+# CONFIG_USB_XPAD is not set
+# CONFIG_USB_ATI_REMOTE is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB Multimedia devices
+#
+# CONFIG_USB_DABUSB is not set
+
+#
+# Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+CONFIG_USB_PEGASUS=y
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGETKIT is not set
+# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_IDMOUSE is not set
+
+#
+# USB ATM/DSL drivers
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+
+#
+# XFS support
+#
+# CONFIG_XFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVPTS_FS_XATTR is not set
+# CONFIG_TMPFS is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_FS is not set
+# CONFIG_KGDB is not set
+# CONFIG_XMON is not set
+CONFIG_BDI_SWITCH=y
+# CONFIG_SERIAL_TEXT_DEBUG is not set
+CONFIG_PPC_OCP=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
diff -uprN linux-2.6.11-bk7/arch/ppc/kernel/cputable.c linux-2.6.11-bk7-440ep/arch/ppc/kernel/cputable.c
--- linux-2.6.11-bk7/arch/ppc/kernel/cputable.c 2005-03-11 16:25:16.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/kernel/cputable.c 2005-03-11 16:26:19.000000000 -0700
@@ -841,6 +841,26 @@ struct cpu_spec cpu_specs[] = {
#endif /* CONFIG_40x */
#ifdef CONFIG_44x
+ { /* 440EP Rev. A */
+ .pvr_mask = 0xf0000fff,
+ .pvr_value = 0x40000850,
+ .cpu_name = "440EP Rev. A",
+ .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB,
+ .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ },
+ { /* 440EP Rev. B */
+ .pvr_mask = 0xf0000fff,
+ .pvr_value = 0x400008d3,
+ .cpu_name = "440EP Rev. B",
+ .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
+ CPU_FTR_USE_TB,
+ .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ },
{ /* 440GP Rev. B */
.pvr_mask = 0xf0000fff,
.pvr_value = 0x40000440,
diff -uprN linux-2.6.11-bk7/arch/ppc/kernel/entry.S linux-2.6.11-bk7-440ep/arch/ppc/kernel/entry.S
--- linux-2.6.11-bk7/arch/ppc/kernel/entry.S 2005-03-02 00:38:25.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/kernel/entry.S 2005-03-11 16:26:19.000000000 -0700
@@ -216,6 +216,7 @@ syscall_dotrace_cont:
lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
mtlr r10
addi r9,r1,STACK_FRAME_OVERHEAD
+ PPC440EP_ERR42
blrl /* Call handler */
.globl ret_from_syscall
ret_from_syscall:
diff -uprN linux-2.6.11-bk7/arch/ppc/kernel/head_44x.S linux-2.6.11-bk7-440ep/arch/ppc/kernel/head_44x.S
--- linux-2.6.11-bk7/arch/ppc/kernel/head_44x.S 2005-03-02 00:37:51.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/kernel/head_44x.S 2005-03-11 16:26:19.000000000 -0700
@@ -228,6 +228,16 @@ skpinv: addi r4,r4,1 /* Increment */
lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
mtspr SPRN_IVPR,r4
+#ifdef CONFIG_440_FPU
+ /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */
+ mfspr r2,SPRN_CCR0
+ lis r3,0xffef
+ ori r3,r3,0xffff
+ and r2,r2,r3
+ mtspr SPRN_CCR0,r2
+ isync
+#endif /* CONFIG_440_FPU */
+
/*
* This is where the main kernel code starts.
*/
@@ -426,7 +436,16 @@ interrupt_base:
PROGRAM_EXCEPTION
/* Floating Point Unavailable Interrupt */
+#ifdef CONFIG_440_FPU
+ /* FPU code from arch/ppc/kernel/head.S */
+ START_EXCEPTION(FloatingPointUnavailable)
+ NORMAL_EXCEPTION_PROLOG
+ bne load_up_fpu
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ EXC_XFER_EE_LITE(0x2010, KernelFP)
+#else
EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
+#endif /* CONFIG_440_FPU */
/* System Call Interrupt */
START_EXCEPTION(SystemCall)
@@ -669,6 +688,85 @@ finish_tlb_load:
mfspr r10, SPRG0
rfi /* Force context change */
+#ifdef CONFIG_440_FPU
+/*
+ * This task wants to use the FPU now.
+ * On UP, disable FP for the task which had the FPU previously,
+ * and save its floating-point registers in its thread_struct.
+ * Load up this task's FP registers from its thread_struct,
+ * enable the FPU for the current task and return to the task.
+ */
+load_up_fpu:
+ mfmsr r5
+ ori r5,r5,MSR_FP
+ sync
+ mtmsr r5 /* enable use of fpu now */
+ isync
+
+ addi r6,0,0
+ addis r3,r6,last_task_used_math@ha
+ lwz r4,last_task_used_math@l(r3)
+ cmpwi 0,r4,0
+ beq 1f
+ add r4,r4,r6
+ addi r4,r4,THREAD /* want last_task_used_math->thread */
+ SAVE_32FPRS(0, r4)
+ mffs fr0
+ stfd fr0,THREAD_FPSCR-4(r4)
+ lwz r5,PT_REGS(r4)
+ add r5,r5,r6
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ li r10,MSR_FP|MSR_FE0|MSR_FE1
+ andc r4,r4,r10 /* disable FP for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+ /* enable use of FP after return */
+ mfspr r5,SPRG3 /* current task's THREAD (phys) */
+ lwz r4,THREAD_FPEXC_MODE(r5)
+ ori r9,r9,MSR_FP /* enable FP for current */
+ or r9,r9,r4
+ lfd fr0,THREAD_FPSCR-4(r5)
+ mtfsf 0xff,fr0
+ REST_32FPRS(0, r5)
+ subi r4,r5,THREAD
+ sub r4,r4,r6
+ stw r4,last_task_used_math@l(r3)
+
+ /* restore registers and return */
+ /* we haven't used ctr or xer or lr */
+ REST_4GPRS(3, r11)
+ lwz r10,_CCR(r11)
+ REST_GPR(1, r11)
+ mtcrf 0xff,r10
+ lwz r10,_LINK(r11)
+ mtlr r10
+ REST_GPR(10, r11)
+ mtspr SRR1,r9
+ mtspr SRR0,r12
+ REST_GPR(9, r11)
+ REST_GPR(12, r11)
+ lwz r11,GPR11(r11)
+ sync
+ rfi
+
+/*
+ * FP unavailable trap from kernel - print a message, but let
+ * the task use FP in the kernel until it returns to user mode.
+ */
+KernelFP:
+ lwz r3,_MSR(r1)
+ ori r3,r3,MSR_FP
+ stw r3,_MSR(r1) /* enable use of FP after return */
+ lis r3,86f@h
+ ori r3,r3,86f@l
+ mr r4,r2 /* current */
+ lwz r5,_NIP(r1)
+ bl printk
+ b ret_from_except
+86: .string "floating point used in kernel (task=%p, pc=%x)\n"
+ .align 4,0
+#endif /* CONFIG_440_FPU */
+
/*
* Global functions
*/
@@ -684,10 +782,37 @@ _GLOBAL(giveup_altivec)
/*
* extern void giveup_fpu(struct task_struct *prev)
*
- * The 44x core does not have an FPU.
+ * Disable FP for the task given as the argument,
+ * and save the floating-point registers in its thread_struct.
+ * Enables the FPU for use in the kernel on return.
*/
_GLOBAL(giveup_fpu)
+#ifdef CONFIG_440_FPU
+ mfmsr r5
+ ori r5,r5,MSR_FP
+ mtmsr r5 /* enable use of fpu now */
+ isync
+ cmpwi 0,r3,0
+ beqlr- /* if no previous owner, done */
+ addi r3,r3,THREAD /* want THREAD of task */
+ lwz r5,PT_REGS(r3)
+ cmpwi 0,r5,0
+ SAVE_32FPRS(0, r3)
+ mffs fr0
+ stfd fr0,THREAD_FPSCR-4(r3)
+ beq 1f
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ li r3,MSR_FP|MSR_FE0|MSR_FE1
+ andc r4,r4,r3 /* disable FP for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+ li r5,0
+ lis r4,last_task_used_math@ha
+ stw r5,last_task_used_math@l(r4)
+ blr
+#else
blr
+#endif /* CONFIG_440_FPU */
/*
* extern void abort(void)
diff -uprN linux-2.6.11-bk7/arch/ppc/kernel/misc.S linux-2.6.11-bk7-440ep/arch/ppc/kernel/misc.S
--- linux-2.6.11-bk7/arch/ppc/kernel/misc.S 2005-03-11 16:25:16.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/kernel/misc.S 2005-03-11 16:26:19.000000000 -0700
@@ -1147,6 +1147,7 @@ _GLOBAL(kernel_thread)
stwu r0,-16(r1)
mtlr r30 /* fn addr in lr */
mr r3,r31 /* load arg and call fn */
+ PPC440EP_ERR42
blrl
li r0,__NR_exit /* exit if function returns */
li r3,0
diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/Kconfig linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/Kconfig
--- linux-2.6.11-bk7/arch/ppc/platforms/4xx/Kconfig 2005-03-02 00:37:48.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/Kconfig 2005-03-11 16:26:19.000000000 -0700
@@ -83,6 +83,11 @@ config OCOTEA
help
This option enables support for the IBM PPC440GX evaluation board.
+config BAMBOO
+ bool "Bamboo"
+ help
+ This option enables support for the IBM PPC440EP evaluation board.
+
endchoice
config EP405PC
@@ -113,6 +118,11 @@ config 440SP
depends on LUAN
default y
+config 440EP
+ bool
+ depends on BAMBOO
+ default y
+
config 440
bool
depends on 440GP || 440SP
@@ -123,6 +133,16 @@ config 440A
depends on 440GX
default y
+config 440_FPU
+ bool
+ depends on 440EP
+ default y
+
+config IBM440EP_ERR42
+ bool
+ depends on 440EP
+ default y
+
# All 405-based cores up until the 405GPR and 405EP have this errata.
config IBM405_ERR77
bool
@@ -142,7 +162,7 @@ config BOOKE
config IBM_OCP
bool
- depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
+ depends on ASH || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT || BAMBOO
default y
config XILINX_OCP
diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/Makefile linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/Makefile
--- linux-2.6.11-bk7/arch/ppc/platforms/4xx/Makefile 2005-03-02 00:38:25.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/Makefile 2005-03-11 16:26:19.000000000 -0700
@@ -2,6 +2,7 @@
# Makefile for the PowerPC 4xx linux kernel.
obj-$(CONFIG_ASH) += ash.o
+obj-$(CONFIG_BAMBOO) += bamboo.o
obj-$(CONFIG_CPCI405) += cpci405.o
obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_EP405) += ep405.o
@@ -22,6 +23,7 @@ obj-$(CONFIG_REDWOOD_6) += ibmstbx25.o
obj-$(CONFIG_440GP) += ibm440gp.o
obj-$(CONFIG_440GX) += ibm440gx.o
obj-$(CONFIG_440SP) += ibm440sp.o
+obj-$(CONFIG_440EP) += ibm440ep.o
obj-$(CONFIG_405EP) += ibm405ep.o
obj-$(CONFIG_405GPR) += ibm405gpr.o
obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o
diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/bamboo.c linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/bamboo.c
--- linux-2.6.11-bk7/arch/ppc/platforms/4xx/bamboo.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/bamboo.c 2005-03-14 15:33:16.000000000 -0700
@@ -0,0 +1,451 @@
+/*
+ * arch/ppc/platforms/4xx/bamboo.c
+ *
+ * Bamboo board specific routines
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright 2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/major.h>
+#include <linux/blkdev.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+#include <linux/initrd.h>
+#include <linux/irq.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/ethtool.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ocp.h>
+#include <asm/pci-bridge.h>
+#include <asm/time.h>
+#include <asm/todc.h>
+#include <asm/bootinfo.h>
+#include <asm/ppc4xx_pic.h>
+#include <asm/ppcboot.h>
+
+#include <syslib/gen550.h>
+#include <syslib/ibm440gx_common.h>
+#include <syslib/ibm440ep_common.h>
+
+/*
+ * This is a horrible kludge, we eventually need to abstract this
+ * generic PHY stuff, so the standard phy mode defines can be
+ * easily used from arch code.
+ */
+#include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
+
+bd_t __res;
+
+static struct ibm44x_clocks clocks __initdata;
+
+/*
+ * Bamboo external IRQ triggering/polarity settings
+ */
+unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
+ (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
+};
+
+static void __init
+bamboo_calibrate_decr(void)
+{
+ unsigned int freq;
+
+ if (mfspr(SPRN_CCR1) & CCR1_TCS)
+ freq = BAMBOO_TMRCLK;
+ else
+ freq = clocks.cpu;
+
+ ibm44x_calibrate_decr(freq);
+
+}
+
+static int
+bamboo_show_cpuinfo(struct seq_file *m)
+{
+ seq_printf(m, "vendor\t\t: IBM\n");
+ seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
+
+ return 0;
+}
+
+static inline int
+bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ { 28, 28, 28, 28 }, /* IDSEL 1 - PCI Slot 0 */
+ { 27, 27, 27, 27 }, /* IDSEL 2 - PCI Slot 1 */
+ { 26, 26, 26, 26 }, /* IDSEL 3 - PCI Slot 2 */
+ { 25, 25, 25, 25 }, /* IDSEL 4 - PCI Slot 3 */
+ };
+
+ const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static void __init bamboo_set_emacdata(void)
+{
+ unsigned char * selection1_base;
+ struct ocp_def *def;
+ struct ocp_func_emac_data *emacdata;
+ u8 selection1_val;
+ int mode;
+
+ selection1_base = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
+ selection1_val = readb(selection1_base);
+ iounmap((void *) selection1_base);
+ if (BAMBOO_SEL_MII(selection1_val))
+ mode = PHY_MODE_MII;
+ else if (BAMBOO_SEL_RMII(selection1_val))
+ mode = PHY_MODE_RMII;
+ else
+ mode = PHY_MODE_SMII;
+
+ /* Set mac_addr and phy mode for each EMAC */
+
+ def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
+ emacdata = def->additions;
+ memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
+ emacdata->phy_mode = mode;
+
+ def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
+ emacdata = def->additions;
+ memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
+ emacdata->phy_mode = mode;
+}
+
+static int
+bamboo_exclude_device(unsigned char bus, unsigned char devfn)
+{
+ return (bus == 0 && devfn == 0);
+}
+
+static unsigned long
+bamboo_ptm1_memory(unsigned long in_size)
+{
+ if (in_size == PPC44x_MEM_SIZE_8M)
+ return PPC44x_MEM_SIZE_8M;
+
+ if ((in_size > PPC44x_MEM_SIZE_8M) && (in_size <= PPC44x_MEM_SIZE_16M))
+ return PPC44x_MEM_SIZE_16M;
+
+ if ((in_size > PPC44x_MEM_SIZE_16M) && (in_size <= PPC44x_MEM_SIZE_32M))
+ return PPC44x_MEM_SIZE_32M;
+
+ if ((in_size > PPC44x_MEM_SIZE_32M) && (in_size <= PPC44x_MEM_SIZE_64M))
+ return PPC44x_MEM_SIZE_64M;
+
+ if ((in_size > PPC44x_MEM_SIZE_64M) && (in_size <= PPC44x_MEM_SIZE_128M))
+ return PPC44x_MEM_SIZE_128M;
+
+ if ((in_size > PPC44x_MEM_SIZE_128M) && (in_size <= PPC44x_MEM_SIZE_256M))
+ return PPC44x_MEM_SIZE_256M;
+ if ((in_size > PPC44x_MEM_SIZE_256M) && (in_size <= PPC44x_MEM_SIZE_512M))
+ return PPC44x_MEM_SIZE_512M;
+
+ return 0;
+}
+
+#define PCI_READW(offset) \
+ (readw((void *)((u32)pci_reg_base+offset)))
+
+#define PCI_WRITEW(value, offset) \
+ (writew(value, (void *)((u32)pci_reg_base+offset)))
+
+#define PCI_WRITEL(value, offset) \
+ (writel(value, (void *)((u32)pci_reg_base+offset)))
+
+static void __init
+bamboo_setup_pci(void)
+{
+ void *pci_reg_base;
+ unsigned long memory_size;
+ memory_size = ppc_md.find_end_of_memory();
+
+ pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
+
+ /* Enable PCI I/O, Mem, and Busmaster cycles */
+ PCI_WRITEW(PCI_READW(PCI_COMMAND) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCI_COMMAND);
+
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA); /* Disable region first */
+ PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA); /* PLB starting addr: 0x00000000A0000000 */
+ PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA); /* PCI start addr, 0xA0000000 (PCI Address) */
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
+ PCI_WRITEL(((0xffffffff -
+ (BAMBOO_PCI_UPPER_MEM -
+ BAMBOO_PCI_MEM_BASE)) | 0x01), BAMBOO_PCIL0_PMM0MA);/* Enable no pre-fetch, enable region */
+ //PCI_WRITEL(0xFC000001, BAMBOO_PCIL0_PMM0MA); /* 64 MB, Enable no pre-fetch, enable region */
+
+ /* Disable region one */
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
+
+ /* Disable region two */
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
+ PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
+
+ /* Now configure the PCI->PLB windows, we only use PTM1
+ *
+ * For Inbound flow, set the window size to all available memory
+ * This is required because if size is smaller,
+ * then Eth/PCI DD would fail as PCI card not able to access
+ * the memory allocated by DD.
+ */
+
+ PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS); /* disabled region 1 */
+ PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA); /* begin of address map */
+ memory_size = bamboo_ptm1_memory(memory_size) | 0x00000001;
+ PCI_WRITEL(memory_size, BAMBOO_PCIL0_PTM1MS); /* Size low + Enabled */
+
+ eieio();
+ iounmap(pci_reg_base);
+}
+
+static void __init
+bamboo_setup_hose(void)
+{
+ unsigned int bar_response, bar;
+ struct pci_controller *hose;
+
+ bamboo_setup_pci();
+
+ hose = pcibios_alloc_controller();
+
+ if (!hose)
+ return;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
+
+ pci_init_resource(&hose->io_resource,
+ BAMBOO_PCI_LOWER_IO,
+ BAMBOO_PCI_UPPER_IO,
+ IORESOURCE_IO,
+ "PCI host bridge");
+
+ pci_init_resource(&hose->mem_resources[0],
+ BAMBOO_PCI_LOWER_MEM,
+ BAMBOO_PCI_UPPER_MEM,
+ IORESOURCE_MEM,
+ "PCI host bridge");
+
+ ppc_md.pci_exclude_device = bamboo_exclude_device;
+
+ hose->io_space.start = BAMBOO_PCI_LOWER_IO;
+ hose->io_space.end = BAMBOO_PCI_UPPER_IO;
+ hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
+ hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
+ isa_io_base =
+ (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
+ hose->io_base_virt = (void *)isa_io_base;
+
+ setup_indirect_pci(hose,
+ BAMBOO_PCI_CFGA_PLB32,
+ BAMBOO_PCI_CFGD_PLB32);
+ hose->set_cfg_type = 1;
+
+ /* Zero config bars */
+ for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
+ early_write_config_dword(hose, hose->first_busno,
+ PCI_FUNC(hose->first_busno), bar,
+ 0x00000000);
+ early_read_config_dword(hose, hose->first_busno,
+ PCI_FUNC(hose->first_busno), bar,
+ &bar_response);
+ }
+
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = bamboo_map_irq;
+}
+
+TODC_ALLOC();
+
+static void __init
+bamboo_early_serial_map(void)
+{
+ struct uart_port port;
+
+ /* Setup ioremapped serial port access */
+ memset(&port, 0, sizeof(port));
+ port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
+ port.irq = 0;
+ port.uartclk = clocks.uart0;
+ port.regshift = 0;
+ port.iotype = SERIAL_IO_MEM;
+ port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+ port.line = 0;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 0 failed\n");
+ }
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+ /* Configure debug serial access */
+ gen550_init(0, &port);
+#endif
+
+ port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
+ port.irq = 1;
+ port.uartclk = clocks.uart1;
+ port.line = 1;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 1 failed\n");
+ }
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+ /* Configure debug serial access */
+ gen550_init(1, &port);
+#endif
+
+ port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
+ port.irq = 3;
+ port.uartclk = clocks.uart2;
+ port.line = 2;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 2 failed\n");
+ }
+
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+ /* Configure debug serial access */
+ gen550_init(2, &port);
+#endif
+
+ port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
+ port.irq = 4;
+ port.uartclk = clocks.uart3;
+ port.line = 3;
+
+ if (early_serial_setup(&port) != 0) {
+ printk("Early serial init of port 3 failed\n");
+ }
+}
+
+static void __init
+bamboo_setup_arch(void)
+{
+
+ bamboo_set_emacdata();
+
+ /*
+ * Determine various clocks.
+ * To be completely correct we should get SysClk
+ * from FPGA, because it can be changed by on-board switches
+ * --ebs
+ */
+ ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+ ocp_sys_info.opb_bus_freq = clocks.opb;
+
+ /* Setup TODC access */
+ TODC_INIT(TODC_TYPE_DS1743,
+ 0,
+ 0,
+ ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
+ 8);
+
+ /* init to some ~sane value until calibrate_delay() runs */
+ loops_per_jiffy = 50000000/HZ;
+
+ /* Setup PCI host bridge */
+ bamboo_setup_hose();
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
+#endif
+#ifdef CONFIG_ROOT_NFS
+ ROOT_DEV = Root_NFS;
+#else
+ ROOT_DEV = Root_HDA1;
+#endif
+
+ bamboo_early_serial_map();
+
+ /* Identify the system */
+ printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
+}
+
+void __init platform_init(unsigned long r3, unsigned long r4,
+ unsigned long r5, unsigned long r6, unsigned long r7)
+{
+ parse_bootinfo(find_bootinfo());
+
+ /*
+ * If we were passed in a board information, copy it into the
+ * residual data area.
+ */
+ if (r3)
+ __res = *(bd_t *)(r3 + KERNELBASE);
+
+ ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+ ocp_sys_info.opb_bus_freq = clocks.opb;
+
+ ibm44x_platform_init();
+
+ ppc_md.setup_arch = bamboo_setup_arch;
+ ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
+ ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
+
+ ppc_md.calibrate_decr = bamboo_calibrate_decr;
+ ppc_md.time_init = todc_time_init;
+ ppc_md.set_rtc_time = todc_set_rtc_time;
+ ppc_md.get_rtc_time = todc_get_rtc_time;
+
+ ppc_md.nvram_read_val = todc_direct_read_val;
+ ppc_md.nvram_write_val = todc_direct_write_val;
+#ifdef CONFIG_KGDB
+ ppc_md.early_serial_map = bamboo_early_serial_map;
+#endif
+}
+
diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/bamboo.h linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/bamboo.h
--- linux-2.6.11-bk7/arch/ppc/platforms/4xx/bamboo.h 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/bamboo.h 2005-03-11 16:26:19.000000000 -0700
@@ -0,0 +1,141 @@
+/*
+ * arch/ppc/platforms/bamboo.h
+ *
+ * Bamboo board definitions
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_BAMBOO_H__
+#define __ASM_BAMBOO_H__
+
+#include <linux/config.h>
+#include <platforms/4xx/ibm440ep.h>
+
+/* F/W TLB mapping used in bootloader glue to reset EMAC */
+#define PPC44x_EMAC0_MR0 0x0EF600E00
+
+#define PIBS_FLASH_BASE 0xfff00000
+#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xc0400)
+#define PIBS_MAC_SIZE 0x200
+#define PIBS_MAC_OFFSET 0x100
+
+/* Default clock rate */
+#define BAMBOO_SYSCLK 33333333
+#define BAMBOO_OPBCLK 66666666
+#define BAMBOO_TMRCLK 25000000
+
+/* RTC/NVRAM location */
+#define BAMBOO_RTC_ADDR 0x80000000
+#define BAMBOO_RTC_SIZE 0x2000
+
+/* FPGA Registers */
+#define BAMBOO_FPGA_ADDR 0x80002000
+
+#define BAMBOO_FPGA_CONFIG1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x0)
+
+#define BAMBOO_FPGA_CONFIG2_REG_ADDR (BAMBOO_FPGA_ADDR + 0x1)
+#define BAMBOO_FULL_DUPLEX_EN(x) (x & 0x8)
+#define BAMBOO_FORCE_100Mbps(x) (x & 0x4)
+#define BAMBOO_AUTONEG(x) (x & 0x2)
+
+#define BAMBOO_FPGA_CLOCKING_REG_ADDR (BAMBOO_FPGA_ADDR + 0x2)
+
+#define BAMBOO_FPGA_SETTING_REG_ADDR (BAMBOO_FPGA_ADDR + 0x3)
+#define BAMBOO_BOOT_SMALL_FLASH(x) (!(x & 0x80))
+#define BAMBOO_LARGE_FLASH_EN(x) (!(x & 0x40))
+#define BAMBOO_BOOT_NAND_FLASH(x) (!(x & 0x20))
+
+#define BAMBOO_FPGA_SELECTION1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x4)
+#define BAMBOO_SEL_MII(x) (x & 0x80)
+#define BAMBOO_SEL_RMII(x) (x & 0x40)
+#define BAMBOO_SEL_SMII(x) (x & 0x20)
+
+#define BAMBOO_FPGA_SELECTION2_REG_ADDR (BAMBOO_FPGA_ADDR + 0x5)
+#define BAMBOO_FPGA_SELECTION3_REG_ADDR (BAMBOO_FPGA_ADDR + 0x6)
+#define BAMBOO_FPGA_RESET_REG_ADDR (BAMBOO_FPGA_ADDR + 0x7)
+
+
+/* Flash */
+#define BAMBOO_SMALL_FLASH_LOW 0x087f00000
+#define BAMBOO_SMALL_FLASH_HIGH 0x0fff00000
+#define BAMBOO_SMALL_FLASH_SIZE 0x100000
+#define BAMBOO_LARGE_FLASH_LOW 0x087800000
+#define BAMBOO_LARGE_FLASH_HIGH1 0x0ff800000
+#define BAMBOO_LARGE_FLASH_HIGH2 0x0ffc00000
+#define BAMBOO_LARGE_FLASH_SIZE 0x400000
+#define BAMBOO_NAND_FLASH_ADDR 0x090000000
+#define BAMBOO_NAND_FLASH_SIZE 0x6400000
+
+/*
+ * Serial port defines
+ */
+
+#define UART0_IO_BASE 0xEF600300
+#define UART1_IO_BASE 0xEF600400
+#define UART2_IO_BASE 0xEF600500
+#define UART3_IO_BASE 0xEF600600
+
+#define BASE_BAUD 33177600/3/16
+#define UART0_INT 0
+#define UART1_INT 1
+#define UART2_INT 3
+#define UART3_INT 4
+
+#define STD_UART_OP(num) \
+ { 0, BASE_BAUD, 0, UART##num##_INT, \
+ (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
+ iomem_base: UART##num##_IO_BASE, \
+ io_type: SERIAL_IO_MEM},
+
+#define SERIAL_PORT_DFNS \
+ STD_UART_OP(0) \
+ STD_UART_OP(1) \
+ STD_UART_OP(2) \
+ STD_UART_OP(3)
+
+/* PCI support */
+#define BAMBOO_PCI_CFGA_PLB32 0xeec00000
+#define BAMBOO_PCI_CFGD_PLB32 0xeec00004
+
+#define BAMBOO_PCI_IO_BASE 0x00000000e8000000
+#define BAMBOO_PCI_IO_SIZE 0x00010000
+#define BAMBOO_PCI_MEM_OFFSET 0x00000000
+#define BAMBOO_PCI_PHY_MEM_BASE 0x00000000A0000000
+
+#define BAMBOO_PCI_LOWER_IO 0x00000000
+#define BAMBOO_PCI_UPPER_IO 0x0000ffff
+#define BAMBOO_PCI_LOWER_MEM 0xa0000000
+#define BAMBOO_PCI_UPPER_MEM 0xafffffff
+#define BAMBOO_PCI_MEM_BASE 0xA0000000
+
+#define BAMBOO_PCIL0_BASE 0x00000000ef400000
+#define BAMBOO_PCIL0_SIZE 0x40
+
+#define BAMBOO_PCIL0_PMM0LA 0x000
+#define BAMBOO_PCIL0_PMM0MA 0x004
+#define BAMBOO_PCIL0_PMM0PCILA 0x008
+#define BAMBOO_PCIL0_PMM0PCIHA 0x00C
+#define BAMBOO_PCIL0_PMM1LA 0x010
+#define BAMBOO_PCIL0_PMM1MA 0x014
+#define BAMBOO_PCIL0_PMM1PCILA 0x018
+#define BAMBOO_PCIL0_PMM1PCIHA 0x01C
+#define BAMBOO_PCIL0_PMM2LA 0x020
+#define BAMBOO_PCIL0_PMM2MA 0x024
+#define BAMBOO_PCIL0_PMM2PCILA 0x028
+#define BAMBOO_PCIL0_PMM2PCIHA 0x02C
+#define BAMBOO_PCIL0_PTM1MS 0x030
+#define BAMBOO_PCIL0_PTM1LA 0x034
+#define BAMBOO_PCIL0_PTM2MS 0x038
+#define BAMBOO_PCIL0_PTM2LA 0x03C
+
+#endif /* __ASM_BAMBOO_H__ */
+#endif /* __KERNEL__ */
diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.c linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.c
--- linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.c 2005-03-11 16:26:19.000000000 -0700
@@ -0,0 +1,176 @@
+/*
+ * arch/ppc/platforms/4xx/ibm440ep.c
+ *
+ * PPC440EP I/O descriptions
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright 2004 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <platforms/4xx/ibm440ep.h>
+#include <asm/ocp.h>
+
+static struct ocp_func_emac_data ibm440ep_emac0_def = {
+ .rgmii_idx = -1, /* No RGMII */
+ .rgmii_mux = -1, /* No RGMII */
+ .zmii_idx = 0, /* ZMII device index */
+ .zmii_mux = 0, /* ZMII input of this EMAC */
+ .mal_idx = 0, /* MAL device index */
+ .mal_rx_chan = 0, /* MAL rx channel number */
+ .mal_tx_chan = 0, /* MAL tx channel number */
+ .wol_irq = 61, /* WOL interrupt number */
+ .mdio_idx = -1, /* No shared MDIO */
+ .tah_idx = -1, /* No TAH */
+};
+
+static struct ocp_func_emac_data ibm440ep_emac1_def = {
+ .rgmii_idx = -1, /* No RGMII */
+ .rgmii_mux = -1, /* No RGMII */
+ .zmii_idx = 0, /* ZMII device index */
+ .zmii_mux = 1, /* ZMII input of this EMAC */
+ .mal_idx = 0, /* MAL device index */
+ .mal_rx_chan = 1, /* MAL rx channel number */
+ .mal_tx_chan = 2, /* MAL tx channel number */
+ .wol_irq = 63, /* WOL interrupt number */
+ .mdio_idx = -1, /* No shared MDIO */
+ .tah_idx = -1, /* No TAH */
+};
+OCP_SYSFS_EMAC_DATA()
+
+static struct ocp_func_mal_data ibm440ep_mal0_def = {
+ .num_tx_chans = 4, /* Number of TX channels */
+ .num_rx_chans = 2, /* Number of RX channels */
+ .txeob_irq = 10, /* TX End Of Buffer IRQ */
+ .rxeob_irq = 11, /* RX End Of Buffer IRQ */
+ .txde_irq = 33, /* TX Descriptor Error IRQ */
+ .rxde_irq = 34, /* RX Descriptor Error IRQ */
+ .serr_irq = 32, /* MAL System Error IRQ */
+};
+OCP_SYSFS_MAL_DATA()
+
+static struct ocp_func_iic_data ibm440ep_iic0_def = {
+ .fast_mode = 0, /* Use standad mode (100Khz) */
+};
+
+static struct ocp_func_iic_data ibm440ep_iic1_def = {
+ .fast_mode = 0, /* Use standad mode (100Khz) */
+};
+OCP_SYSFS_IIC_DATA()
+
+struct ocp_def core_ocp[] = {
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_OPB,
+ .index = 0,
+ .paddr = 0xEF600000,
+ .irq = OCP_IRQ_NA,
+ .pm = OCP_CPM_NA,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_16550,
+ .index = 0,
+ .paddr = PPC440EP_UART0_ADDR,
+ .irq = UART0_INT,
+ .pm = IBM_CPM_UART0,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_16550,
+ .index = 1,
+ .paddr = PPC440EP_UART1_ADDR,
+ .irq = UART1_INT,
+ .pm = IBM_CPM_UART1,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_16550,
+ .index = 2,
+ .paddr = PPC440EP_UART2_ADDR,
+ .irq = UART2_INT,
+ .pm = IBM_CPM_UART2,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_16550,
+ .index = 3,
+ .paddr = PPC440EP_UART3_ADDR,
+ .irq = UART3_INT,
+ .pm = IBM_CPM_UART3,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_IIC,
+ .index = 0,
+ .paddr = PPC440EP_IIC0_ADDR,
+ .irq = IIC0_IRQ,
+ .pm = IBM_CPM_IIC0,
+ .additions = &ibm440ep_iic0_def,
+ .show = &ocp_show_iic_data
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_IIC,
+ .index = 1,
+ .paddr = PPC440EP_IIC1_ADDR,
+ .irq = IIC1_IRQ,
+ .pm = IBM_CPM_IIC1,
+ .additions = &ibm440ep_iic1_def,
+ .show = &ocp_show_iic_data
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_GPIO,
+ .index = 0,
+ .paddr = PPC440EP_GPIO0_ADDR,
+ .irq = OCP_IRQ_NA,
+ .pm = IBM_CPM_GPIO0,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_GPIO,
+ .index = 1,
+ .paddr = PPC440EP_GPIO1_ADDR,
+ .irq = OCP_IRQ_NA,
+ .pm = OCP_CPM_NA,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_MAL,
+ .paddr = OCP_PADDR_NA,
+ .irq = OCP_IRQ_NA,
+ .pm = OCP_CPM_NA,
+ .additions = &ibm440ep_mal0_def,
+ .show = &ocp_show_mal_data,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_EMAC,
+ .index = 0,
+ .paddr = PPC440EP_EMAC0_ADDR,
+ .irq = BL_MAC_ETH0,
+ .pm = OCP_CPM_NA,
+ .additions = &ibm440ep_emac0_def,
+ .show = &ocp_show_emac_data,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_EMAC,
+ .index = 1,
+ .paddr = PPC440EP_EMAC1_ADDR,
+ .irq = BL_MAC_ETH1,
+ .pm = OCP_CPM_NA,
+ .additions = &ibm440ep_emac1_def,
+ .show = &ocp_show_emac_data,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_ZMII,
+ .paddr = PPC440EP_ZMII_ADDR,
+ .irq = OCP_IRQ_NA,
+ .pm = OCP_CPM_NA,
+ },
+ { .vendor = OCP_VENDOR_IBM,
+ .function = OCP_FUNC_USB,
+ .paddr = PPC440EP_USB1HOST_ADDR,
+ .irq = USB0_IRQ,
+ .pm = IBM_CPM_USB1H,
+ },
+ { .vendor = OCP_VENDOR_INVALID
+ }
+};
+
diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.h linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.h
--- linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.h 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.h 2005-03-11 16:26:19.000000000 -0700
@@ -0,0 +1,224 @@
+/*
+ * arch/ppc/platforms/4xx/ibm440ep.h
+ *
+ * PPC440EP definitions
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ *
+ * Copyright 2002 Roland Dreier
+ * Copyright 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __PPC_PLATFORMS_IBM440EP_H
+#define __PPC_PLATFORMS_IBM440EP_H
+
+#include <linux/config.h>
+
+/* GPT */
+#define PPC440EP_GPT_ADDR 0x0EF600000
+#define PPC440EP_GPT_SIZE 0x200
+#define GPT_NUMS 1
+
+/* UART */
+#define PPC440EP_UART0_ADDR 0x0EF600300
+#define PPC440EP_UART1_ADDR 0x0EF600400
+#define PPC440EP_UART2_ADDR 0x0EF600500
+#define PPC440EP_UART3_ADDR 0x0EF600600
+#define PPC440EP_UART_SIZE 0x08
+#define UART_NUMS 4
+
+/* EMAC */
+#define PPC440EP_EMAC0_ADDR 0x0EF600E00
+#define PPC440EP_EMAC1_ADDR 0x0EF600F00
+#define PPC440EP_EMAC_SIZE 0x100
+#define EMAC_NUMS 2
+
+/* EMAC IRQ's */
+#define BL_MAC_WOL 61 /* WOL */
+#define BL_MAC_WOL1 63 /* WOL */
+#define BL_MAL_SERR 32 /* MAL SERR */
+#define BL_MAL_TXDE 33 /* MAL TXDE */
+#define BL_MAL_RXDE 34 /* MAL RXDE */
+#define BL_MAL_TXEOB 10 /* MAL TX EOB */
+#define BL_MAL_RXEOB 11 /* MAL RX EOB */
+#define BL_MAC_ETH0 60 /* MAC */
+#define BL_MAC_ETH1 62 /* MAC */
+
+/* ZMII */
+#define PPC440EP_ZMII_ADDR 0x0EF600D00
+#define PPC440EP_ZMII_SIZE 0x10
+#define ZMII_NUMS 1
+
+/* IIC */
+#define PPC440EP_IIC0_ADDR 0x0EF600700
+#define PPC440EP_IIC1_ADDR 0x0EF600800
+#define PPC440EP_IIC_SIZE 0x20
+#define IIC0_IRQ 2
+#define IIC1_IRQ 7
+#define IIC_NUMS 2
+
+/* SPI */
+#define PPC440EP_SPI_ADDR 0x0EF600900
+#define PPC440EP_SPI_SIZE 0x06
+#define SPI_NUMS 1
+
+/* GPIO */
+#define PPC440EP_GPIO0_ADDR 0x0EF600B00
+#define PPC440EP_GPIO1_ADDR 0x0EF600C00
+#define PPC440EP_GPIO_SIZE 0x80
+#define GPIO_NUMS 2
+
+/* USB1HOST */
+#define PPC440EP_USB1HOST_ADDR 0x0EF601000
+#define PPC440EP_USB1HOST_SIZE 0x80
+#define USB1HOST_IRQ 40
+#define USB1HOST_NUMS 1
+
+/* USB 1.1 Host constants for usb-ocp-ohci.c */
+#define USB0_IRQ USB1HOST_IRQ
+#define USB0_BASE PPC440EP_USB1HOST_ADDR
+#define USB0_SIZE PPC440EP_USB1HOST_SIZE
+#define USB0_EXTENT 4096
+
+/* NDFC Registers */
+#define PPC440EP_NDFC_REG_BASE 0x090000000
+#define PPC440EP_NDFC_REG_SIZE 0x2000
+
+/* Clock and Power Management */
+#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
+#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
+#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
+#define IBM_CPM_USB1H 0x08000000 /* USB 1.1 Host */
+#define IBM_CPM_FPU 0x04000000 /* floating point unit */
+#define IBM_CPM_CPU 0x02000000 /* processor core */
+#define IBM_CPM_DMA 0x01000000 /* DMA controller */
+#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
+#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
+#define IBM_CPM_EBC 0x00200000 /* External Bus Controller */
+#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
+#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
+#define IBM_CPM_PLB4 0x00040000 /* PLB4 bus arbiter */
+#define IBM_CPM_PLB4x3 0x00020000 /* PLB4 to PLB3 bridge controller */
+#define IBM_CPM_PLB3x4 0x00010000 /* PLB3 to PLB4 bridge controller */
+#define IBM_CPM_PLB3 0x00008000 /* PLB3 bus arbiter */
+#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
+#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
+#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
+#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
+#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
+#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
+#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
+#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
+#define IBM_CPM_EMAC0 0x00000020 /* ethernet port 0 */
+#define IBM_CPM_EMAC1 0x00000010 /* ethernet port 1 */
+#define IBM_CPM_UART2 0x00000008 /* serial port 2 */
+#define IBM_CPM_UART3 0x00000004 /* serial port 3 */
+#define IBM_CPM_USB2D 0x00000002 /* USB 2.0 Device */
+#define IBM_CPM_USB2H 0x00000001 /* USB 2.0 Host */
+
+#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
+ | IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
+ | IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
+ | IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
+ | IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
+ | IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
+/*
+ * Serial port defines
+ */
+#define RS_TABLE_SIZE 4
+
+#include <asm/ibm44x.h>
+#include <syslib/ibm440ep_common.h>
+
+/*
+ * DCRs (the common ones will be defined in ibm44x.h)
+ */
+
+/* Base DCR address values for all peripheral cores in the 440EP */
+
+#define CPR0_DCR_BASE 0x00C /* Clock and Power Reset */
+#define SDR0_DCR_BASE 0x00E /* chip control registers */
+
+/* DMA */
+
+#define MAX_DMA_PLB4_CHANNELS 4
+
+/* Base DCRNs */
+#define DCRN_DMA0_PLB4_BASE 0x300 /* DMA to PL4 Channel 0 */
+#define DCRN_DMA1_PLB4_BASE 0x308 /* DMA to PL4 Channel 1 */
+#define DCRN_DMA2_PLB4_BASE 0x310 /* DMA to PL4 Channel 2 */
+#define DCRN_DMA3_PLB4_BASE 0x318 /* DMA to PL4 Channel 3 */
+#define DCRN_DMASR_PLB4_BASE 0x320 /* DMA to PL4 status Register */
+
+#define DCRN_DMACR0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x0) /* DMA Channel Control 0 */
+#define DCRN_DMACT0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x1) /* DMA Count 0 */
+#define DCRN_DMASAH0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x2) /* DMA Src Addr High 0 */
+#define DCRN_DMASA0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x3) /* DMA Src Addr Low 0 */
+#define DCRN_DMADAH0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x4) /* DMA Dest Addr High 0 */
+#define DCRN_DMADA0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x5) /* DMA Dest Addr Low 0 */
+#define DCRN_ASGH0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 0 */
+#define DCRN_ASG0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
+
+#define DCRN_DMACR1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x0) /* DMA Channel Control 1 */
+#define DCRN_DMACT1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x1) /* DMA Count 1 */
+#define DCRN_DMASAH1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x2) /* DMA Src Addr High 1 */
+#define DCRN_DMASA1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x3) /* DMA Src Addr Low 1 */
+#define DCRN_DMADAH1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x4) /* DMA Dest Addr High 1 */
+#define DCRN_DMADA1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x5) /* DMA Dest Addr Low 1 */
+#define DCRN_ASGH1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 1 */
+#define DCRN_ASG1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 1 */
+
+#define DCRN_DMACR2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x0) /* DMA Channel Control 2 */
+#define DCRN_DMACT2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x1) /* DMA Count 2 */
+#define DCRN_DMASAH2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x2) /* DMA Src Addr High 2 */
+#define DCRN_DMASA2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x3) /* DMA Src Addr Low 2 */
+#define DCRN_DMADAH2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x4) /* DMA Dest Addr High 2 */
+#define DCRN_DMADA2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x5) /* DMA Dest Addr Low 2 */
+#define DCRN_ASGH2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 2 */
+#define DCRN_ASG2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
+
+#define DCRN_DMACR3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x0) /* DMA Channel Control 3 */
+#define DCRN_DMACT3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x1) /* DMA Count 3 */
+#define DCRN_DMASAH3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x2) /* DMA Src Addr High 3 */
+#define DCRN_DMASA3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x3) /* DMA Src Addr Low 3 */
+#define DCRN_DMADAH3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x4) /* DMA Dest Addr High 3 */
+#define DCRN_DMADA3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x5) /* DMA Dest Addr Low 3 */
+#define DCRN_ASGH3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 3 */
+#define DCRN_ASG3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
+
+#define DCRN_DMASR_PLB4 (DCRN_DMASR_PLB4_BASE + 0x0) /* DMA Status Register */
+#define DCRN_ASGC_PLB4 (DCRN_DMASR_PLB4_BASE + 0x3) /* DMA Scatter/Gather Command */
+#define DCRN_SLP_PLB4 (DCRN_DMASR_PLB4_BASE + 0x5) /* DMA Sleep Register */
+#define DCRN_POL_PLB4 (DCRN_DMASR_PLB4_BASE + 0x6) /* DMA Polarity Register */
+
+#define DMA_CE_ENABLE_PLB4 0x80000000
+#define DMA_CIE_ENABLE_PLB4 0x40000000
+#define DMA_TD_PLB4 0x20000000
+#define DMA_PL_PLB4 0x10000000
+#define DMA_PW_WORD 0x04000000
+#define DMA_DAI_PLB4 0x01000000
+#define DMA_SAI_PLB4 0x00800000
+#define DMA_BUFFER_ENABLED_PLB4 0x00400000
+#define DMA_MTM_HARDWARE_START_PLB4 0x00300000
+#define DMA_TS_IS_OUTPUT_PLB4 0x00000100
+#define DMA_STOP_AT_TC_PLB4 0x00000080
+#define DMA_PRIORITY_HIGH_PLB4 0x00000060
+
+#define DMA_TCIE_ENABLED_PLB4 0x20000000
+#define DMA_ETIE_ENABLED_PLB4 0x10000000
+#define DMA_EIE_ENABLED_PLB4 0x08000000
+#define DMA_BURST_ENABLED_PLB4 0x00800000
+#define DMA_BURST_SIZE_8_PLB4 0x00400000
+
+/* SDR0 */
+#define SDR0_USB 0x0320 /* Selection of USB2.0 and USB1.1 Device */
+
+#endif /* __PPC_PLATFORMS_IBM440EP_H */
+#endif /* __KERNEL__ */
diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/Makefile linux-2.6.11-bk7-440ep/arch/ppc/syslib/Makefile
--- linux-2.6.11-bk7/arch/ppc/syslib/Makefile 2005-03-11 16:25:17.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/Makefile 2005-03-14 14:59:52.000000000 -0700
@@ -11,6 +11,7 @@ obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram
obj-$(CONFIG_PPC_OCP) += ocp.o
obj-$(CONFIG_IBM_OCP) += ibm_ocp.o
obj-$(CONFIG_44x) += ibm44x_common.o
+obj-$(CONFIG_440EP) += ibm440gx_common.o ibm440ep_common.o
obj-$(CONFIG_440GP) += ibm440gp_common.o
obj-$(CONFIG_440GX) += ibm440gx_common.o
obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
@@ -44,6 +45,7 @@ obj-$(CONFIG_PPC_CHRP) += open_pic.o in
obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o
obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
todc_time.o
+obj-$(CONFIG_BAMBOO) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/ibm440ep_common.c linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440ep_common.c
--- linux-2.6.11-bk7/arch/ppc/syslib/ibm440ep_common.c 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440ep_common.c 2005-03-14 13:49:37.000000000 -0700
@@ -0,0 +1,334 @@
+/*
+ * arch/ppc/kernel/ibm440ep_common.c
+ *
+ * PPC440EP system library
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <asm/ibm44x.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <syslib/ibm440ep_common.h>
+#include <linux/module.h>
+
+/* DMA functions reserved for DMA to PLB4 (used for USB2.0 Device) */
+
+/*
+ * * Clear DMA Status Register (DMA2P40_SR)
+ * */
+void clear_dma2pl4_status(void)
+{
+ mtdcr(DCRN_DMASR_PLB4, 0xffffffff);
+}
+
+/*
+ * * Get the DMA to PLB4 status Register (DMA2P40_SR)
+ * */
+int get_dma2pl4_status(void)
+{
+ return (mfdcr(DCRN_DMASR_PLB4));
+}
+
+/*
+ * * Get the DMA to PLB4 ADDRESS DEST (DMA2P40_DA)
+ * */
+unsigned long get_dma2pl4_dst_addr(unsigned int dmanr)
+{
+ unsigned long dst_addr;
+
+ switch (dmanr) {
+ case 0:
+ dst_addr = mfdcr(DCRN_DMADA0_PLB4);
+ break;
+
+ case 1:
+ dst_addr = mfdcr(DCRN_DMADA1_PLB4);
+ break;
+
+ case 2:
+ dst_addr = mfdcr(DCRN_DMADA2_PLB4);
+ break;
+
+ case 3:
+ dst_addr = mfdcr(DCRN_DMADA3_PLB4);
+ break;
+
+ default:
+ dst_addr = 0;
+ if (dmanr >= MAX_DMA_PLB4_CHANNELS)
+ printk("get_dma2pl4_dst_addr: bad channel: %d\n", dmanr);
+ }
+ return dst_addr;
+}
+
+/*
+ * Set the source address
+ */
+void set_src_addr_dma2pl4(unsigned int dmanr, phys_addr_t src_addr)
+{
+ switch (dmanr) {
+
+ case 0:
+ mtdcr(DCRN_DMASAH0_PLB4, (u32)(src_addr >> 32));
+ mtdcr(DCRN_DMASA0_PLB4, (u32)src_addr);
+ break;
+
+ case 1:
+ mtdcr(DCRN_DMASAH1_PLB4, (u32)(src_addr >> 32));
+ mtdcr(DCRN_DMASA1_PLB4, (u32)src_addr);
+ break;
+
+ case 2:
+ mtdcr(DCRN_DMASAH2_PLB4, (u32)(src_addr >> 32));
+ mtdcr(DCRN_DMASA2_PLB4, (u32)src_addr);
+ break;
+
+ case 3:
+ mtdcr(DCRN_DMASAH3_PLB4, (u32)(src_addr >> 32));
+ mtdcr(DCRN_DMASA3_PLB4, (u32)src_addr);
+ break;
+
+ default:
+ if (dmanr >= MAX_DMA_PLB4_CHANNELS)
+ printk("set_src_addr_dma2pl4: bad channel: %d\n", dmanr);
+ }
+}
+
+/*
+ * Set the destimation address
+ */
+void set_dst_addr_dma2pl4(unsigned int dmanr, phys_addr_t dst_addr)
+{
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMADAH0_PLB4, (u32)(dst_addr >> 32));
+ mtdcr(DCRN_DMADA0_PLB4, (u32)dst_addr);
+ break;
+ case 1:
+ mtdcr(DCRN_DMADAH1_PLB4, (u32)(dst_addr >> 32));
+ mtdcr(DCRN_DMADA1_PLB4, (u32)dst_addr);
+ break;
+ case 2:
+ mtdcr(DCRN_DMADAH2_PLB4, (u32)(dst_addr >> 32));
+ mtdcr(DCRN_DMADA2_PLB4, (u32)dst_addr);
+ break;
+ case 3:
+ mtdcr(DCRN_DMADAH3_PLB4, (u32)(dst_addr >> 32));
+ mtdcr(DCRN_DMADA3_PLB4, (u32)dst_addr);
+ break;
+ default:
+ if (dmanr >= MAX_DMA_PLB4_CHANNELS)
+ printk("set_dst_addr_dma2pl4: bad channel: %d\n", dmanr);
+ }
+}
+
+/*
+ * Enable the DMA to PLB4 Peripheral to Memory
+ */
+void enable_dma2pl4_peripheral_to_memory(unsigned int dmanr,
+ phys_addr_t srcAddr,
+ phys_addr_t destAddr,
+ unsigned int count)
+{
+ unsigned int control = 0x00;
+
+ control |= DMA_CIE_ENABLE_PLB4; /* Channel Interrupt Enable */
+ control |= DMA_TD_PLB4; /* Transfers are from peripheral-to-memory */
+ control |= DMA_PL_PLB4; /* Device located on the OPB */
+ control |= DMA_PW_WORD; /* Peripheral Width (32 bits) */
+ control |= DMA_DAI_PLB4; /* Destination Address Increment */
+ control |= 0x00; /* Do not increment Source Address */
+ control |= DMA_BUFFER_ENABLED_PLB4; /* Enable DMA Buffer */
+ control |= DMA_MTM_HARDWARE_START_PLB4; /* Transfert mode: Device spaced memory-to-memory */
+ control |= 0x00; /* Peripheral Setup Cycles:000 */
+ control |= DMA_TS_IS_OUTPUT_PLB4; /* End of transfert Terminal/Count */
+ control |= DMA_STOP_AT_TC_PLB4; /* Stop at TC */
+ control |= DMA_PRIORITY_HIGH_PLB4; /* Channel priority High */
+
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMACR0_PLB4, control);
+ break;
+ case 1:
+ mtdcr(DCRN_DMACR1_PLB4, control);
+ break;
+ case 2:
+ mtdcr(DCRN_DMACR2_PLB4, control);
+ break;
+ case 3:
+ mtdcr(DCRN_DMACR3_PLB4, control);
+ break;
+ default:
+ printk("enable_dma: bad channel: %d\n", dmanr);
+ }
+
+ /*
+ * Clear the CS, TS, RI bits for the channel from DMASR. This
+ * has been observed to happen correctly only after the mode and
+ * ETD/DCE bits in DMACRx are set above. Must do this before
+ * enabling the channel.
+ */
+ mtdcr(DCRN_DMASR_PLB4, 0xffffffff);
+
+ /* peripheral to memory */
+ set_src_addr_dma2pl4(dmanr, srcAddr);
+ set_dst_addr_dma2pl4(dmanr, destAddr);
+
+ count |= DMA_TCIE_ENABLED_PLB4;
+ count |= DMA_ETIE_ENABLED_PLB4;
+ count |= DMA_EIE_ENABLED_PLB4;
+ count |= DMA_BURST_ENABLED_PLB4;
+ count |= DMA_BURST_SIZE_8_PLB4;
+
+ /* Set the number of bytes to transfer */
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMACT0_PLB4, count);
+ break;
+ case 1:
+ mtdcr(DCRN_DMACT1_PLB4, count);
+ break;
+ case 2:
+ mtdcr(DCRN_DMACT2_PLB4, count);
+ break;
+ case 3:
+ mtdcr(DCRN_DMACT3_PLB4, count);
+ break;
+ default:
+ printk("enable_dma: bad channel: %d\n", dmanr);
+ }
+
+ /*
+ * Now enable the channel.
+ */
+ control |= DMA_CE_ENABLE_PLB4;
+
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMACR0_PLB4, control);
+ break;
+ case 1:
+ mtdcr(DCRN_DMACR1_PLB4, control);
+ break;
+ case 2:
+ mtdcr(DCRN_DMACR2_PLB4, control);
+ break;
+ case 3:
+ mtdcr(DCRN_DMACR3_PLB4, control);
+ break;
+ default:
+ printk("enable_dma: bad channel: %d\n", dmanr);
+ }
+}
+
+/*
+ * * Enable the DMA to PLB4 Memory to Peripheral
+ * */
+void enable_dma2pl4_memory_to_peripheral(unsigned int dmanr,
+ phys_addr_t srcAddr,
+ phys_addr_t destAddr,
+ unsigned int count)
+{
+ unsigned int control = 0x00;
+
+ control |= DMA_CIE_ENABLE_PLB4; /* Channel Interrupt Enable */
+ control |= 0x00; /* Transfers are from memory_to_peripheral */
+ control |= DMA_PL_PLB4; /* Device located on the OPB */
+ control |= DMA_PW_WORD; /* Peripheral Width (32 bits) */
+ control |= 0x00; /* Do not increment Destination Address */
+ control |= DMA_SAI_PLB4; /* Source Address Increment */
+ control |= DMA_BUFFER_ENABLED_PLB4; /* Enable DMA Buffer */
+ control |= DMA_MTM_HARDWARE_START_PLB4; /* Transfert mode: Device spaced memory-to-memory */
+ control |= 0x00; /* Peripheral Setup Cycles:000 */
+ control |= DMA_TS_IS_OUTPUT_PLB4; /* End of transfert Terminal/Count */
+ control |= DMA_STOP_AT_TC_PLB4; /* Stop at TC */
+ control |= DMA_PRIORITY_HIGH_PLB4; /* Channel priority High */
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMACR0_PLB4, control);
+ break;
+ case 1:
+ mtdcr(DCRN_DMACR1_PLB4, control);
+ break;
+ case 2:
+ mtdcr(DCRN_DMACR2_PLB4, control);
+ break;
+ case 3:
+ mtdcr(DCRN_DMACR3_PLB4, control);
+ break;
+ default:
+ printk("enable_dma: bad channel: %d\n", dmanr);
+ }
+ /*
+ * Clear the CS, TS, RI bits for the channel from DMASR. This
+ * has been observed to happen correctly only after the mode and
+ * ETD/DCE bits in DMACRx are set above. Must do this before
+ * enabling the channel.
+ */
+ mtdcr(DCRN_DMASR_PLB4, 0xffffffff);
+
+ /* peripheral to memory */
+ set_src_addr_dma2pl4(dmanr, srcAddr);
+ set_dst_addr_dma2pl4(dmanr, destAddr);
+ count |= DMA_TCIE_ENABLED_PLB4;
+ count |= DMA_ETIE_ENABLED_PLB4;
+ count |= DMA_EIE_ENABLED_PLB4;
+ count |= DMA_BURST_ENABLED_PLB4;
+ count |= DMA_BURST_SIZE_8_PLB4;
+
+ /* Set the number of bytes to transfer */
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMACT0_PLB4, count);
+ break;
+ case 1:
+ mtdcr(DCRN_DMACT1_PLB4, count);
+ break;
+ case 2:
+ mtdcr(DCRN_DMACT2_PLB4, count);
+ break;
+ case 3:
+ mtdcr(DCRN_DMACT3_PLB4, count);
+ break;
+ default:
+ printk("enable_dma: bad channel: %d\n", dmanr);
+ }
+
+ /*
+ * Now enable the channel.
+ */
+ control |= DMA_CE_ENABLE_PLB4;
+
+ switch (dmanr) {
+ case 0:
+ mtdcr(DCRN_DMACR0_PLB4, control);
+ break;
+ case 1:
+ mtdcr(DCRN_DMACR1_PLB4, control);
+ break;
+ case 2:
+ mtdcr(DCRN_DMACR2_PLB4, control);
+ break;
+ case 3:
+ mtdcr(DCRN_DMACR3_PLB4, control);
+ break;
+ default:
+ printk("enable_dma: bad channel: %d\n", dmanr);
+ }
+}
+
+EXPORT_SYMBOL(get_dma2pl4_status);
+EXPORT_SYMBOL(clear_dma2pl4_status);
+EXPORT_SYMBOL(get_dma2pl4_dst_addr);
+EXPORT_SYMBOL(enable_dma2pl4_peripheral_to_memory);
+EXPORT_SYMBOL(enable_dma2pl4_memory_to_peripheral);
diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/ibm440ep_common.h linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440ep_common.h
--- linux-2.6.11-bk7/arch/ppc/syslib/ibm440ep_common.h 1969-12-31 17:00:00.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440ep_common.h 2005-03-11 16:26:19.000000000 -0700
@@ -0,0 +1,54 @@
+/*
+ * arch/ppc/kernel/ibm440ep_common.h
+ *
+ * PPC440EP system library
+ *
+ * Wade Farnsworth <wfarnsworth@mvista.com>
+ * Copyright 2004 MontaVista Software, Inc.
+ *
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2003 Zultys Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#ifdef __KERNEL__
+#ifndef __PPC_SYSLIB_IBM440EP_COMMON_H
+#define __PPC_SYSLIB_IBM440EP_COMMON_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <syslib/ibm44x_common.h>
+#include <asm/mmu.h>
+
+/*
+ * Please, refer to the Figure 15.1 in 440EP user manual
+ *
+ * if internal UART clock is used, ser_clk is ignored
+ */
+void ibm440ep_get_clocks(struct ibm44x_clocks*, unsigned int sys_clk,
+ unsigned int ser_clk) __init;
+
+/*
+ * The DMA API are in ibm440ep_common.c
+ */
+int get_dma2pl4_status(void);
+void clear_dma2pl4_status(void);
+unsigned long get_dma2pl4_dst_addr(unsigned int dmanr);
+void enable_dma2pl4_peripheral_to_memory(unsigned int dmanr,
+ phys_addr_t srcAddr,
+ phys_addr_t destAddr,
+ unsigned int count);
+void enable_dma2pl4_memory_to_peripheral(unsigned int dmanr,
+ phys_addr_t srcAddr,
+ phys_addr_t destAddr,
+ unsigned int count);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __PPC_SYSLIB_IBM440EP_COMMON_H */
+#endif /* __KERNEL__ */
diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/ibm440gx_common.c linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440gx_common.c
--- linux-2.6.11-bk7/arch/ppc/syslib/ibm440gx_common.c 2005-03-02 00:38:25.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440gx_common.c 2005-03-14 13:52:45.000000000 -0700
@@ -34,6 +34,10 @@ void __init ibm440gx_get_clocks(struct i
u32 plld = CPR_READ(DCRN_CPR_PLLD);
u32 uart0 = SDR_READ(DCRN_SDR_UART0);
u32 uart1 = SDR_READ(DCRN_SDR_UART1);
+#ifdef CONFIG_440EP
+ u32 uart2 = SDR_READ(DCRN_SDR_UART2);
+ u32 uart3 = SDR_READ(DCRN_SDR_UART3);
+#endif
/* Dividers */
u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
@@ -96,6 +100,19 @@ bypass:
p->uart1 = ser_clk;
else
p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
+
+#ifdef CONFIG_440EP
+ if (uart2 & 0x00800000)
+ p->uart1 = ser_clk;
+ else
+ p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
+
+ if (uart3 & 0x00800000)
+ p->uart1 = ser_clk;
+ else
+ p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256);
+#endif
+
}
/* Issue L2C diagnostic command */
diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/ibm44x_common.h linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm44x_common.h
--- linux-2.6.11-bk7/arch/ppc/syslib/ibm44x_common.h 2005-03-02 00:37:50.000000000 -0700
+++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm44x_common.h 2005-03-14 13:48:19.000000000 -0700
@@ -29,6 +29,11 @@ struct ibm44x_clocks {
unsigned int ebc; /* PerClk */
unsigned int uart0;
unsigned int uart1;
+#ifdef CONFIG_440EP
+ /* The IBM 440EP eval board has four uarts */
+ unsigned int uart2;
+ unsigned int uart3;
+#endif
};
/* common 44x platform init */
diff -uprN linux-2.6.11-bk7/include/asm-ppc/ibm44x.h linux-2.6.11-bk7-440ep/include/asm-ppc/ibm44x.h
--- linux-2.6.11-bk7/include/asm-ppc/ibm44x.h 2005-03-02 00:38:38.000000000 -0700
+++ linux-2.6.11-bk7-440ep/include/asm-ppc/ibm44x.h 2005-03-11 16:26:19.000000000 -0700
@@ -35,8 +35,10 @@
#define PPC44x_LOW_SLOT 63
/* LS 32-bits of UART0 physical address location for early serial text debug */
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
#define UART0_PHYS_IO_BASE 0xf0000200
+#elif defined(CONFIG_440EP)
+#define UART0_PHYS_IO_BASE 0xe0000000
#else
#define UART0_PHYS_IO_BASE 0x40000200
#endif
@@ -49,11 +51,16 @@
/*
* Standard 4GB "page" definitions
*/
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
#define PPC44x_IO_PAGE 0x0000000100000000ULL
#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
+#elif defined(CONFIG_440EP)
+#define PPC44x_IO_PAGE 0x0000000000000000ULL
+#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
+#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
+#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL
#else
#define PPC44x_IO_PAGE 0x0000000100000000ULL
#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
@@ -64,7 +71,7 @@
/*
* 36-bit trap ranges
*/
-#ifdef CONFIG_440SP
+#if defined(CONFIG_440SP)
#define PPC44x_IO_LO 0xf0000000UL
#define PPC44x_IO_HI 0xf0000fffUL
#define PPC44x_PCI0CFG_LO 0x0ec00000UL
@@ -75,6 +82,13 @@
#define PPC44x_PCI2CFG_HI 0x2ec00007UL
#define PPC44x_PCIMEM_LO 0x80000000UL
#define PPC44x_PCIMEM_HI 0xdfffffffUL
+#elif defined(CONFIG_440EP)
+#define PPC44x_IO_LO 0xef500000
+#define PPC44x_IO_HI 0xefffffff
+#define PPC44x_PCI0CFG_LO 0xeec00000
+#define PPC44x_PCI0CFG_HI 0xeecfffff
+#define PPC44x_PCIMEM_LO 0xa0000000
+#define PPC44x_PCIMEM_HI 0xdfffffff
#else
#define PPC44x_IO_LO 0x40000000UL
#define PPC44x_IO_HI 0x40000fffUL
@@ -151,7 +165,21 @@
#define DCRN_SDR_MFR_E3RXFH 0x00000001
#define DCRN_SDR_UART0 0x0120
#define DCRN_SDR_UART1 0x0121
+#endif /* CONFIG_440GX */
+#ifdef CONFIG_440EP
+#define DCRN_SDR_CONFIG_ADDR 0xe
+#define DCRN_SDR_CONFIG_DATA 0xf
+#define DCRN_SDR_PFC0 0x4100
+#define DCRN_SDR_PFC1 0x4101
+#define DCRN_SDR_MFR 0x4300
+#define DCRN_SDR_UART0 0x0120
+#define DCRN_SDR_UART1 0x0121
+#define DCRN_SDR_UART2 0x0122
+#define DCRN_SDR_UART3 0x0123
+#endif
+
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP)
/* SDR read/write helper macros */
#define SDR_READ(offset) ({\
mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
@@ -169,6 +197,14 @@
#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
#define DCRN_MAL_BASE 0x180
+#ifdef CONFIG_440EP
+#define DCRN_DMA2P40_BASE 0x300
+#define DCRN_DMA2P41_BASE 0x308
+#define DCRN_DMA2P42_BASE 0x310
+#define DCRN_DMA2P43_BASE 0x318
+#define DCRN_DMA2P4SR_BASE 0x320
+#endif
+
/* UIC */
#define DCRN_UIC0_BASE 0xc0
#define DCRN_UIC1_BASE 0xd0
diff -uprN linux-2.6.11-bk7/include/asm-ppc/ibm4xx.h linux-2.6.11-bk7-440ep/include/asm-ppc/ibm4xx.h
--- linux-2.6.11-bk7/include/asm-ppc/ibm4xx.h 2005-03-02 00:38:09.000000000 -0700
+++ linux-2.6.11-bk7-440ep/include/asm-ppc/ibm4xx.h 2005-03-11 16:26:19.000000000 -0700
@@ -109,6 +109,10 @@ void ppc4xx_init(unsigned long r3, unsig
#include <platforms/4xx/ocotea.h>
#endif
+#if defined(CONFIG_BAMBOO)
+#include <platforms/4xx/bamboo.h>
+#endif
+
#ifndef __ASSEMBLY__
#ifdef CONFIG_40x
/*
diff -uprN linux-2.6.11-bk7/include/asm-ppc/ppc_asm.h linux-2.6.11-bk7-440ep/include/asm-ppc/ppc_asm.h
--- linux-2.6.11-bk7/include/asm-ppc/ppc_asm.h 2005-03-02 00:37:48.000000000 -0700
+++ linux-2.6.11-bk7-440ep/include/asm-ppc/ppc_asm.h 2005-03-11 16:26:19.000000000 -0700
@@ -184,6 +184,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
#define PPC405_ERR77_SYNC
#endif
+#ifdef CONFIG_IBM440EP_ERR42
+#define PPC440EP_ERR42 isync
+#else
+#define PPC440EP_ERR42
+#endif
+
/* The boring bits... */
/* Condition Register Bit Fields */
diff -uprN linux-2.6.11-bk7/include/asm-ppc/reg.h linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h
--- linux-2.6.11-bk7/include/asm-ppc/reg.h 2005-03-11 16:25:22.000000000 -0700
+++ linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h 2005-03-14 10:05:47.000000000 -0700
@@ -449,6 +449,8 @@
#define PVR_STB03XXX 0x40310000
#define PVR_NP405H 0x41410000
#define PVR_NP405L 0x41610000
+#define PVR_440EP_RA 0x42221850
+#define PVR_440EP_RB 0x422218D3
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC1 0x40120481
#define PVR_440GP_RC2 0x40200481
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
2005-03-15 17:17 [PATCH 1/3] PPC440EP SoC and Bamboo board support Wade Farnsworth
@ 2005-03-15 18:41 ` Eugene Surovegin
2005-03-15 19:08 ` Wade Farnsworth
2005-03-15 18:47 ` [PATCH 2/3] PPC440EP: ibm_emac phy mode bug fix Wade Farnsworth
` (2 subsequent siblings)
3 siblings, 1 reply; 35+ messages in thread
From: Eugene Surovegin @ 2005-03-15 18:41 UTC (permalink / raw)
To: Wade Farnsworth; +Cc: linuxppc-embedded
On Tue, Mar 15, 2005 at 10:17:19AM -0700, Wade Farnsworth wrote:
> Hello all,
>
> This adds support for the IBM/AMCC PPC440EP SoC and the Bamboo reference
> board. Any comments would be appreciated.
[snip]
> diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.c linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.c
> --- linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.c 1969-12-31 17:00:00.000000000 -0700
> +++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.c 2005-03-11 16:26:19.000000000 -0700
> @@ -0,0 +1,176 @@
> +/*
> + * arch/ppc/platforms/4xx/ibm440ep.c
> + *
> + * PPC440EP I/O descriptions
> + *
> + * Wade Farnsworth <wfarnsworth@mvista.com>
> + * Copyright 2004 MontaVista Software Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + */
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <platforms/4xx/ibm440ep.h>
> +#include <asm/ocp.h>
> +
> +static struct ocp_func_emac_data ibm440ep_emac0_def = {
> + .rgmii_idx = -1, /* No RGMII */
> + .rgmii_mux = -1, /* No RGMII */
> + .zmii_idx = 0, /* ZMII device index */
> + .zmii_mux = 0, /* ZMII input of this EMAC */
> + .mal_idx = 0, /* MAL device index */
> + .mal_rx_chan = 0, /* MAL rx channel number */
> + .mal_tx_chan = 0, /* MAL tx channel number */
> + .wol_irq = 61, /* WOL interrupt number */
> + .mdio_idx = -1, /* No shared MDIO */
> + .tah_idx = -1, /* No TAH */
> +};
> +
> +static struct ocp_func_emac_data ibm440ep_emac1_def = {
> + .rgmii_idx = -1, /* No RGMII */
> + .rgmii_mux = -1, /* No RGMII */
> + .zmii_idx = 0, /* ZMII device index */
> + .zmii_mux = 1, /* ZMII input of this EMAC */
> + .mal_idx = 0, /* MAL device index */
> + .mal_rx_chan = 1, /* MAL rx channel number */
> + .mal_tx_chan = 2, /* MAL tx channel number */
> + .wol_irq = 63, /* WOL interrupt number */
> + .mdio_idx = -1, /* No shared MDIO */
> + .tah_idx = -1, /* No TAH */
> +};
> +OCP_SYSFS_EMAC_DATA()
> +
> +static struct ocp_func_mal_data ibm440ep_mal0_def = {
> + .num_tx_chans = 4, /* Number of TX channels */
> + .num_rx_chans = 2, /* Number of RX channels */
> + .txeob_irq = 10, /* TX End Of Buffer IRQ */
> + .rxeob_irq = 11, /* RX End Of Buffer IRQ */
> + .txde_irq = 33, /* TX Descriptor Error IRQ */
> + .rxde_irq = 34, /* RX Descriptor Error IRQ */
> + .serr_irq = 32, /* MAL System Error IRQ */
> +};
> +OCP_SYSFS_MAL_DATA()
> +
> +static struct ocp_func_iic_data ibm440ep_iic0_def = {
> + .fast_mode = 0, /* Use standad mode (100Khz) */
> +};
> +
> +static struct ocp_func_iic_data ibm440ep_iic1_def = {
> + .fast_mode = 0, /* Use standad mode (100Khz) */
> +};
> +OCP_SYSFS_IIC_DATA()
> +
> +struct ocp_def core_ocp[] = {
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_OPB,
> + .index = 0,
> + .paddr = 0xEF600000,
> + .irq = OCP_IRQ_NA,
> + .pm = OCP_CPM_NA,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_16550,
> + .index = 0,
> + .paddr = PPC440EP_UART0_ADDR,
> + .irq = UART0_INT,
> + .pm = IBM_CPM_UART0,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_16550,
> + .index = 1,
> + .paddr = PPC440EP_UART1_ADDR,
> + .irq = UART1_INT,
> + .pm = IBM_CPM_UART1,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_16550,
> + .index = 2,
> + .paddr = PPC440EP_UART2_ADDR,
> + .irq = UART2_INT,
> + .pm = IBM_CPM_UART2,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_16550,
> + .index = 3,
> + .paddr = PPC440EP_UART3_ADDR,
> + .irq = UART3_INT,
> + .pm = IBM_CPM_UART3,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_IIC,
> + .index = 0,
> + .paddr = PPC440EP_IIC0_ADDR,
Do we need PPC440EP_IIC0_ADDR define? I think not, please, don't
introduce useless defines which are only used in one file. Use numbers
directly, it helps readability. Please, look at how this is
handled in other 4xx platform files.
> + .irq = IIC0_IRQ,
Ditto
> + .pm = IBM_CPM_IIC0,
> + .additions = &ibm440ep_iic0_def,
> + .show = &ocp_show_iic_data
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_IIC,
> + .index = 1,
> + .paddr = PPC440EP_IIC1_ADDR,
Ditto.
> + .irq = IIC1_IRQ,
> + .pm = IBM_CPM_IIC1,
> + .additions = &ibm440ep_iic1_def,
> + .show = &ocp_show_iic_data
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_GPIO,
> + .index = 0,
> + .paddr = PPC440EP_GPIO0_ADDR,
Ditto.
> + .irq = OCP_IRQ_NA,
> + .pm = IBM_CPM_GPIO0,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_GPIO,
> + .index = 1,
> + .paddr = PPC440EP_GPIO1_ADDR,
Ditto.
> + .irq = OCP_IRQ_NA,
> + .pm = OCP_CPM_NA,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_MAL,
> + .paddr = OCP_PADDR_NA,
> + .irq = OCP_IRQ_NA,
> + .pm = OCP_CPM_NA,
> + .additions = &ibm440ep_mal0_def,
> + .show = &ocp_show_mal_data,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_EMAC,
> + .index = 0,
> + .paddr = PPC440EP_EMAC0_ADDR,
Ditto
> + .irq = BL_MAC_ETH0,
Ditto.
> + .pm = OCP_CPM_NA,
> + .additions = &ibm440ep_emac0_def,
> + .show = &ocp_show_emac_data,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_EMAC,
> + .index = 1,
> + .paddr = PPC440EP_EMAC1_ADDR,
> + .irq = BL_MAC_ETH1,
> + .pm = OCP_CPM_NA,
> + .additions = &ibm440ep_emac1_def,
> + .show = &ocp_show_emac_data,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_ZMII,
> + .paddr = PPC440EP_ZMII_ADDR,
> + .irq = OCP_IRQ_NA,
> + .pm = OCP_CPM_NA,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_USB,
> + .paddr = PPC440EP_USB1HOST_ADDR,
> + .irq = USB0_IRQ,
> + .pm = IBM_CPM_USB1H,
> + },
> + { .vendor = OCP_VENDOR_INVALID
> + }
> +};
> +
> diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.h linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.h
> --- linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.h 1969-12-31 17:00:00.000000000 -0700
> +++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.h 2005-03-11 16:26:19.000000000 -0700
> @@ -0,0 +1,224 @@
> +/*
> + * arch/ppc/platforms/4xx/ibm440ep.h
> + *
> + * PPC440EP definitions
> + *
> + * Wade Farnsworth <wfarnsworth@mvista.com>
> + *
> + * Copyright 2002 Roland Dreier
> + * Copyright 2004 MontaVista Software, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + */
> +
> +#ifdef __KERNEL__
> +#ifndef __PPC_PLATFORMS_IBM440EP_H
> +#define __PPC_PLATFORMS_IBM440EP_H
> +
> +#include <linux/config.h>
> +
> +/* GPT */
> +#define PPC440EP_GPT_ADDR 0x0EF600000
> +#define PPC440EP_GPT_SIZE 0x200
> +#define GPT_NUMS 1
> +
> +/* UART */
> +#define PPC440EP_UART0_ADDR 0x0EF600300
> +#define PPC440EP_UART1_ADDR 0x0EF600400
> +#define PPC440EP_UART2_ADDR 0x0EF600500
> +#define PPC440EP_UART3_ADDR 0x0EF600600
> +#define PPC440EP_UART_SIZE 0x08
> +#define UART_NUMS 4
> +
> +/* EMAC */
> +#define PPC440EP_EMAC0_ADDR 0x0EF600E00
> +#define PPC440EP_EMAC1_ADDR 0x0EF600F00
> +#define PPC440EP_EMAC_SIZE 0x100
> +#define EMAC_NUMS 2
> +
> +/* EMAC IRQ's */
> +#define BL_MAC_WOL 61 /* WOL */
> +#define BL_MAC_WOL1 63 /* WOL */
> +#define BL_MAL_SERR 32 /* MAL SERR */
> +#define BL_MAL_TXDE 33 /* MAL TXDE */
> +#define BL_MAL_RXDE 34 /* MAL RXDE */
> +#define BL_MAL_TXEOB 10 /* MAL TX EOB */
> +#define BL_MAL_RXEOB 11 /* MAL RX EOB */
> +#define BL_MAC_ETH0 60 /* MAC */
> +#define BL_MAC_ETH1 62 /* MAC */
We don't need these defines.
> +
> +/* ZMII */
> +#define PPC440EP_ZMII_ADDR 0x0EF600D00
> +#define PPC440EP_ZMII_SIZE 0x10
> +#define ZMII_NUMS 1
And these
> +
> +/* IIC */
> +#define PPC440EP_IIC0_ADDR 0x0EF600700
> +#define PPC440EP_IIC1_ADDR 0x0EF600800
> +#define PPC440EP_IIC_SIZE 0x20
> +#define IIC0_IRQ 2
> +#define IIC1_IRQ 7
> +#define IIC_NUMS 2
> +
> +/* SPI */
> +#define PPC440EP_SPI_ADDR 0x0EF600900
> +#define PPC440EP_SPI_SIZE 0x06
> +#define SPI_NUMS 1
> +
> +/* GPIO */
> +#define PPC440EP_GPIO0_ADDR 0x0EF600B00
> +#define PPC440EP_GPIO1_ADDR 0x0EF600C00
> +#define PPC440EP_GPIO_SIZE 0x80
> +#define GPIO_NUMS 2
And these....
> +
> +/* USB1HOST */
> +#define PPC440EP_USB1HOST_ADDR 0x0EF601000
> +#define PPC440EP_USB1HOST_SIZE 0x80
> +#define USB1HOST_IRQ 40
> +#define USB1HOST_NUMS 1
> +
> +/* USB 1.1 Host constants for usb-ocp-ohci.c */
> +#define USB0_IRQ USB1HOST_IRQ
> +#define USB0_BASE PPC440EP_USB1HOST_ADDR
> +#define USB0_SIZE PPC440EP_USB1HOST_SIZE
> +#define USB0_EXTENT 4096
> +
> +/* NDFC Registers */
> +#define PPC440EP_NDFC_REG_BASE 0x090000000
> +#define PPC440EP_NDFC_REG_SIZE 0x2000
> +
> +/* Clock and Power Management */
> +#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
> +#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
> +#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
> +#define IBM_CPM_USB1H 0x08000000 /* USB 1.1 Host */
> +#define IBM_CPM_FPU 0x04000000 /* floating point unit */
> +#define IBM_CPM_CPU 0x02000000 /* processor core */
> +#define IBM_CPM_DMA 0x01000000 /* DMA controller */
> +#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
> +#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
> +#define IBM_CPM_EBC 0x00200000 /* External Bus Controller */
> +#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
> +#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
> +#define IBM_CPM_PLB4 0x00040000 /* PLB4 bus arbiter */
> +#define IBM_CPM_PLB4x3 0x00020000 /* PLB4 to PLB3 bridge controller */
> +#define IBM_CPM_PLB3x4 0x00010000 /* PLB3 to PLB4 bridge controller */
> +#define IBM_CPM_PLB3 0x00008000 /* PLB3 bus arbiter */
> +#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
> +#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
> +#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
> +#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
> +#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
> +#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
> +#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
> +#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
> +#define IBM_CPM_EMAC0 0x00000020 /* ethernet port 0 */
> +#define IBM_CPM_EMAC1 0x00000010 /* ethernet port 1 */
> +#define IBM_CPM_UART2 0x00000008 /* serial port 2 */
> +#define IBM_CPM_UART3 0x00000004 /* serial port 3 */
> +#define IBM_CPM_USB2D 0x00000002 /* USB 2.0 Device */
> +#define IBM_CPM_USB2H 0x00000001 /* USB 2.0 Host */
> +
> +#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
> + | IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
> + | IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
> + | IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
> + | IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
> + | IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
> +/*
> + * Serial port defines
> + */
> +#define RS_TABLE_SIZE 4
> +
> +#include <asm/ibm44x.h>
> +#include <syslib/ibm440ep_common.h>
> +
> +/*
> + * DCRs (the common ones will be defined in ibm44x.h)
> + */
> +
> +/* Base DCR address values for all peripheral cores in the 440EP */
> +
> +#define CPR0_DCR_BASE 0x00C /* Clock and Power Reset */
> +#define SDR0_DCR_BASE 0x00E /* chip control registers */
> +
> +/* DMA */
> +
> +#define MAX_DMA_PLB4_CHANNELS 4
> +
> +/* Base DCRNs */
> +#define DCRN_DMA0_PLB4_BASE 0x300 /* DMA to PL4 Channel 0 */
> +#define DCRN_DMA1_PLB4_BASE 0x308 /* DMA to PL4 Channel 1 */
> +#define DCRN_DMA2_PLB4_BASE 0x310 /* DMA to PL4 Channel 2 */
> +#define DCRN_DMA3_PLB4_BASE 0x318 /* DMA to PL4 Channel 3 */
> +#define DCRN_DMASR_PLB4_BASE 0x320 /* DMA to PL4 status Register */
> +
> +#define DCRN_DMACR0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x0) /* DMA Channel Control 0 */
> +#define DCRN_DMACT0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x1) /* DMA Count 0 */
> +#define DCRN_DMASAH0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x2) /* DMA Src Addr High 0 */
> +#define DCRN_DMASA0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x3) /* DMA Src Addr Low 0 */
> +#define DCRN_DMADAH0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x4) /* DMA Dest Addr High 0 */
> +#define DCRN_DMADA0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x5) /* DMA Dest Addr Low 0 */
> +#define DCRN_ASGH0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 0 */
> +#define DCRN_ASG0_PLB4 (DCRN_DMA0_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
> +
> +#define DCRN_DMACR1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x0) /* DMA Channel Control 1 */
> +#define DCRN_DMACT1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x1) /* DMA Count 1 */
> +#define DCRN_DMASAH1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x2) /* DMA Src Addr High 1 */
> +#define DCRN_DMASA1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x3) /* DMA Src Addr Low 1 */
> +#define DCRN_DMADAH1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x4) /* DMA Dest Addr High 1 */
> +#define DCRN_DMADA1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x5) /* DMA Dest Addr Low 1 */
> +#define DCRN_ASGH1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 1 */
> +#define DCRN_ASG1_PLB4 (DCRN_DMA1_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 1 */
> +
> +#define DCRN_DMACR2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x0) /* DMA Channel Control 2 */
> +#define DCRN_DMACT2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x1) /* DMA Count 2 */
> +#define DCRN_DMASAH2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x2) /* DMA Src Addr High 2 */
> +#define DCRN_DMASA2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x3) /* DMA Src Addr Low 2 */
> +#define DCRN_DMADAH2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x4) /* DMA Dest Addr High 2 */
> +#define DCRN_DMADA2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x5) /* DMA Dest Addr Low 2 */
> +#define DCRN_ASGH2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 2 */
> +#define DCRN_ASG2_PLB4 (DCRN_DMA2_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
> +
> +#define DCRN_DMACR3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x0) /* DMA Channel Control 3 */
> +#define DCRN_DMACT3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x1) /* DMA Count 3 */
> +#define DCRN_DMASAH3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x2) /* DMA Src Addr High 3 */
> +#define DCRN_DMASA3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x3) /* DMA Src Addr Low 3 */
> +#define DCRN_DMADAH3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x4) /* DMA Dest Addr High 3 */
> +#define DCRN_DMADA3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x5) /* DMA Dest Addr Low 3 */
> +#define DCRN_ASGH3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x6) /* DMA SG Desc Addr High 3 */
> +#define DCRN_ASG3_PLB4 (DCRN_DMA3_PLB4_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
> +
> +#define DCRN_DMASR_PLB4 (DCRN_DMASR_PLB4_BASE + 0x0) /* DMA Status Register */
> +#define DCRN_ASGC_PLB4 (DCRN_DMASR_PLB4_BASE + 0x3) /* DMA Scatter/Gather Command */
> +#define DCRN_SLP_PLB4 (DCRN_DMASR_PLB4_BASE + 0x5) /* DMA Sleep Register */
> +#define DCRN_POL_PLB4 (DCRN_DMASR_PLB4_BASE + 0x6) /* DMA Polarity Register */
> +
> +#define DMA_CE_ENABLE_PLB4 0x80000000
> +#define DMA_CIE_ENABLE_PLB4 0x40000000
> +#define DMA_TD_PLB4 0x20000000
> +#define DMA_PL_PLB4 0x10000000
> +#define DMA_PW_WORD 0x04000000
> +#define DMA_DAI_PLB4 0x01000000
> +#define DMA_SAI_PLB4 0x00800000
> +#define DMA_BUFFER_ENABLED_PLB4 0x00400000
> +#define DMA_MTM_HARDWARE_START_PLB4 0x00300000
> +#define DMA_TS_IS_OUTPUT_PLB4 0x00000100
> +#define DMA_STOP_AT_TC_PLB4 0x00000080
> +#define DMA_PRIORITY_HIGH_PLB4 0x00000060
> +
> +#define DMA_TCIE_ENABLED_PLB4 0x20000000
> +#define DMA_ETIE_ENABLED_PLB4 0x10000000
> +#define DMA_EIE_ENABLED_PLB4 0x08000000
> +#define DMA_BURST_ENABLED_PLB4 0x00800000
> +#define DMA_BURST_SIZE_8_PLB4 0x00400000
> +
> +/* SDR0 */
> +#define SDR0_USB 0x0320 /* Selection of USB2.0 and USB1.1 Device */
> +
> +#endif /* __PPC_PLATFORMS_IBM440EP_H */
> +#endif /* __KERNEL__ */
> diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/Makefile linux-2.6.11-bk7-440ep/arch/ppc/syslib/Makefile
> --- linux-2.6.11-bk7/arch/ppc/syslib/Makefile 2005-03-11 16:25:17.000000000 -0700
> +++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/Makefile 2005-03-14 14:59:52.000000000 -0700
> @@ -11,6 +11,7 @@ obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram
> obj-$(CONFIG_PPC_OCP) += ocp.o
> obj-$(CONFIG_IBM_OCP) += ibm_ocp.o
> obj-$(CONFIG_44x) += ibm44x_common.o
> +obj-$(CONFIG_440EP) += ibm440gx_common.o ibm440ep_common.o
> obj-$(CONFIG_440GP) += ibm440gp_common.o
> obj-$(CONFIG_440GX) += ibm440gx_common.o
> obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o
> @@ -44,6 +45,7 @@ obj-$(CONFIG_PPC_CHRP) += open_pic.o in
> obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o
> obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
> todc_time.o
> +obj-$(CONFIG_BAMBOO) += indirect_pci.o pci_auto.o todc_time.o
> obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o
> obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
> obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
> diff -uprN linux-2.6.11-bk7/arch/ppc/syslib/ibm440ep_common.c linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440ep_common.c
> --- linux-2.6.11-bk7/arch/ppc/syslib/ibm440ep_common.c 1969-12-31 17:00:00.000000000 -0700
> +++ linux-2.6.11-bk7-440ep/arch/ppc/syslib/ibm440ep_common.c 2005-03-14 13:49:37.000000000 -0700
> @@ -0,0 +1,334 @@
> +/*
> + * arch/ppc/kernel/ibm440ep_common.c
> + *
> + * PPC440EP system library
> + *
> + * Wade Farnsworth <wfarnsworth@mvista.com>
> + * Copyright 2004 MontaVista Software, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + */
> +#include <linux/config.h>
> +#include <linux/kernel.h>
> +#include <linux/interrupt.h>
> +#include <asm/ibm44x.h>
> +#include <asm/mmu.h>
> +#include <asm/processor.h>
> +#include <syslib/ibm440ep_common.h>
> +#include <linux/module.h>
> +
> +/* DMA functions reserved for DMA to PLB4 (used for USB2.0 Device) */
> +
> +/*
> + * * Clear DMA Status Register (DMA2P40_SR)
> + * */
> +void clear_dma2pl4_status(void)
> +{
> + mtdcr(DCRN_DMASR_PLB4, 0xffffffff);
> +}
> +
> +/*
> + * * Get the DMA to PLB4 status Register (DMA2P40_SR)
> + * */
> +int get_dma2pl4_status(void)
> +{
> + return (mfdcr(DCRN_DMASR_PLB4));
> +}
> +
> +/*
> + * * Get the DMA to PLB4 ADDRESS DEST (DMA2P40_DA)
> + * */
> +unsigned long get_dma2pl4_dst_addr(unsigned int dmanr)
> +{
> + unsigned long dst_addr;
> +
> + switch (dmanr) {
> + case 0:
> + dst_addr = mfdcr(DCRN_DMADA0_PLB4);
> + break;
> +
> + case 1:
> + dst_addr = mfdcr(DCRN_DMADA1_PLB4);
> + break;
> +
> + case 2:
> + dst_addr = mfdcr(DCRN_DMADA2_PLB4);
> + break;
> +
> + case 3:
> + dst_addr = mfdcr(DCRN_DMADA3_PLB4);
> + break;
PLEASE, there is already "inderect" DCR stuff in the tree. You don't
need all these ugly switch statements.
> +
> + default:
> + dst_addr = 0;
> + if (dmanr >= MAX_DMA_PLB4_CHANNELS)
> + printk("get_dma2pl4_dst_addr: bad channel: %d\n", dmanr);
> + }
> + return dst_addr;
> +}
> +
> +/*
> + * Set the source address
> + */
> +void set_src_addr_dma2pl4(unsigned int dmanr, phys_addr_t src_addr)
> +{
> + switch (dmanr) {
> +
> + case 0:
> + mtdcr(DCRN_DMASAH0_PLB4, (u32)(src_addr >> 32));
> + mtdcr(DCRN_DMASA0_PLB4, (u32)src_addr);
> + break;
> +
> + case 1:
> + mtdcr(DCRN_DMASAH1_PLB4, (u32)(src_addr >> 32));
> + mtdcr(DCRN_DMASA1_PLB4, (u32)src_addr);
> + break;
> +
> + case 2:
> + mtdcr(DCRN_DMASAH2_PLB4, (u32)(src_addr >> 32));
> + mtdcr(DCRN_DMASA2_PLB4, (u32)src_addr);
> + break;
> +
> + case 3:
> + mtdcr(DCRN_DMASAH3_PLB4, (u32)(src_addr >> 32));
> + mtdcr(DCRN_DMASA3_PLB4, (u32)src_addr);
> + break;
Ditto.
> +
> + default:
> + if (dmanr >= MAX_DMA_PLB4_CHANNELS)
> + printk("set_src_addr_dma2pl4: bad channel: %d\n", dmanr);
> + }
> +}
> +
> +/*
> + * Set the destimation address
> + */
> +void set_dst_addr_dma2pl4(unsigned int dmanr, phys_addr_t dst_addr)
> +{
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMADAH0_PLB4, (u32)(dst_addr >> 32));
> + mtdcr(DCRN_DMADA0_PLB4, (u32)dst_addr);
> + break;
> + case 1:
> + mtdcr(DCRN_DMADAH1_PLB4, (u32)(dst_addr >> 32));
> + mtdcr(DCRN_DMADA1_PLB4, (u32)dst_addr);
> + break;
> + case 2:
> + mtdcr(DCRN_DMADAH2_PLB4, (u32)(dst_addr >> 32));
> + mtdcr(DCRN_DMADA2_PLB4, (u32)dst_addr);
> + break;
> + case 3:
> + mtdcr(DCRN_DMADAH3_PLB4, (u32)(dst_addr >> 32));
> + mtdcr(DCRN_DMADA3_PLB4, (u32)dst_addr);
> + break;
Ditto.
> + default:
> + if (dmanr >= MAX_DMA_PLB4_CHANNELS)
> + printk("set_dst_addr_dma2pl4: bad channel: %d\n", dmanr);
> + }
> +}
> +
> +/*
> + * Enable the DMA to PLB4 Peripheral to Memory
> + */
> +void enable_dma2pl4_peripheral_to_memory(unsigned int dmanr,
> + phys_addr_t srcAddr,
> + phys_addr_t destAddr,
> + unsigned int count)
> +{
> + unsigned int control = 0x00;
> +
> + control |= DMA_CIE_ENABLE_PLB4; /* Channel Interrupt Enable */
> + control |= DMA_TD_PLB4; /* Transfers are from peripheral-to-memory */
> + control |= DMA_PL_PLB4; /* Device located on the OPB */
> + control |= DMA_PW_WORD; /* Peripheral Width (32 bits) */
> + control |= DMA_DAI_PLB4; /* Destination Address Increment */
> + control |= 0x00; /* Do not increment Source Address */
> + control |= DMA_BUFFER_ENABLED_PLB4; /* Enable DMA Buffer */
> + control |= DMA_MTM_HARDWARE_START_PLB4; /* Transfert mode: Device spaced memory-to-memory */
> + control |= 0x00; /* Peripheral Setup Cycles:000 */
> + control |= DMA_TS_IS_OUTPUT_PLB4; /* End of transfert Terminal/Count */
> + control |= DMA_STOP_AT_TC_PLB4; /* Stop at TC */
> + control |= DMA_PRIORITY_HIGH_PLB4; /* Channel priority High */
> +
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMACR0_PLB4, control);
> + break;
> + case 1:
> + mtdcr(DCRN_DMACR1_PLB4, control);
> + break;
> + case 2:
> + mtdcr(DCRN_DMACR2_PLB4, control);
> + break;
> + case 3:
> + mtdcr(DCRN_DMACR3_PLB4, control);
> + break;
Ditto
> + default:
> + printk("enable_dma: bad channel: %d\n", dmanr);
> + }
> +
> + /*
> + * Clear the CS, TS, RI bits for the channel from DMASR. This
> + * has been observed to happen correctly only after the mode and
> + * ETD/DCE bits in DMACRx are set above. Must do this before
> + * enabling the channel.
> + */
> + mtdcr(DCRN_DMASR_PLB4, 0xffffffff);
> +
> + /* peripheral to memory */
> + set_src_addr_dma2pl4(dmanr, srcAddr);
> + set_dst_addr_dma2pl4(dmanr, destAddr);
> +
> + count |= DMA_TCIE_ENABLED_PLB4;
> + count |= DMA_ETIE_ENABLED_PLB4;
> + count |= DMA_EIE_ENABLED_PLB4;
> + count |= DMA_BURST_ENABLED_PLB4;
> + count |= DMA_BURST_SIZE_8_PLB4;
> +
> + /* Set the number of bytes to transfer */
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMACT0_PLB4, count);
> + break;
> + case 1:
> + mtdcr(DCRN_DMACT1_PLB4, count);
> + break;
> + case 2:
> + mtdcr(DCRN_DMACT2_PLB4, count);
> + break;
> + case 3:
> + mtdcr(DCRN_DMACT3_PLB4, count);
> + break;
Ditto
> + default:
> + printk("enable_dma: bad channel: %d\n", dmanr);
> + }
> +
> + /*
> + * Now enable the channel.
> + */
> + control |= DMA_CE_ENABLE_PLB4;
> +
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMACR0_PLB4, control);
> + break;
> + case 1:
> + mtdcr(DCRN_DMACR1_PLB4, control);
> + break;
> + case 2:
> + mtdcr(DCRN_DMACR2_PLB4, control);
> + break;
> + case 3:
> + mtdcr(DCRN_DMACR3_PLB4, control);
> + break;
Ditto
> + default:
> + printk("enable_dma: bad channel: %d\n", dmanr);
> + }
> +}
> +
> +/*
> + * * Enable the DMA to PLB4 Memory to Peripheral
> + * */
> +void enable_dma2pl4_memory_to_peripheral(unsigned int dmanr,
> + phys_addr_t srcAddr,
> + phys_addr_t destAddr,
> + unsigned int count)
> +{
> + unsigned int control = 0x00;
> +
> + control |= DMA_CIE_ENABLE_PLB4; /* Channel Interrupt Enable */
> + control |= 0x00; /* Transfers are from memory_to_peripheral */
> + control |= DMA_PL_PLB4; /* Device located on the OPB */
> + control |= DMA_PW_WORD; /* Peripheral Width (32 bits) */
> + control |= 0x00; /* Do not increment Destination Address */
> + control |= DMA_SAI_PLB4; /* Source Address Increment */
> + control |= DMA_BUFFER_ENABLED_PLB4; /* Enable DMA Buffer */
> + control |= DMA_MTM_HARDWARE_START_PLB4; /* Transfert mode: Device spaced memory-to-memory */
> + control |= 0x00; /* Peripheral Setup Cycles:000 */
> + control |= DMA_TS_IS_OUTPUT_PLB4; /* End of transfert Terminal/Count */
> + control |= DMA_STOP_AT_TC_PLB4; /* Stop at TC */
> + control |= DMA_PRIORITY_HIGH_PLB4; /* Channel priority High */
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMACR0_PLB4, control);
> + break;
> + case 1:
> + mtdcr(DCRN_DMACR1_PLB4, control);
> + break;
> + case 2:
> + mtdcr(DCRN_DMACR2_PLB4, control);
> + break;
> + case 3:
> + mtdcr(DCRN_DMACR3_PLB4, control);
> + break;
Ditto
> + default:
> + printk("enable_dma: bad channel: %d\n", dmanr);
> + }
> + /*
> + * Clear the CS, TS, RI bits for the channel from DMASR. This
> + * has been observed to happen correctly only after the mode and
> + * ETD/DCE bits in DMACRx are set above. Must do this before
> + * enabling the channel.
> + */
> + mtdcr(DCRN_DMASR_PLB4, 0xffffffff);
> +
> + /* peripheral to memory */
> + set_src_addr_dma2pl4(dmanr, srcAddr);
> + set_dst_addr_dma2pl4(dmanr, destAddr);
> + count |= DMA_TCIE_ENABLED_PLB4;
> + count |= DMA_ETIE_ENABLED_PLB4;
> + count |= DMA_EIE_ENABLED_PLB4;
> + count |= DMA_BURST_ENABLED_PLB4;
> + count |= DMA_BURST_SIZE_8_PLB4;
> +
> + /* Set the number of bytes to transfer */
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMACT0_PLB4, count);
> + break;
> + case 1:
> + mtdcr(DCRN_DMACT1_PLB4, count);
> + break;
> + case 2:
> + mtdcr(DCRN_DMACT2_PLB4, count);
> + break;
> + case 3:
> + mtdcr(DCRN_DMACT3_PLB4, count);
> + break;
Ditto
> + default:
> + printk("enable_dma: bad channel: %d\n", dmanr);
> + }
> +
> + /*
> + * Now enable the channel.
> + */
> + control |= DMA_CE_ENABLE_PLB4;
> +
> + switch (dmanr) {
> + case 0:
> + mtdcr(DCRN_DMACR0_PLB4, control);
> + break;
> + case 1:
> + mtdcr(DCRN_DMACR1_PLB4, control);
> + break;
> + case 2:
> + mtdcr(DCRN_DMACR2_PLB4, control);
> + break;
> + case 3:
> + mtdcr(DCRN_DMACR3_PLB4, control);
> + break;
Ditto
> + default:
> + printk("enable_dma: bad channel: %d\n", dmanr);
> + }
> +}
> +
> +EXPORT_SYMBOL(get_dma2pl4_status);
> +EXPORT_SYMBOL(clear_dma2pl4_status);
> +EXPORT_SYMBOL(get_dma2pl4_dst_addr);
> +EXPORT_SYMBOL(enable_dma2pl4_peripheral_to_memory);
> +EXPORT_SYMBOL(enable_dma2pl4_memory_to_peripheral);
[snip]
> diff -uprN linux-2.6.11-bk7/include/asm-ppc/reg.h linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h
> --- linux-2.6.11-bk7/include/asm-ppc/reg.h 2005-03-11 16:25:22.000000000 -0700
> +++ linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h 2005-03-14 10:05:47.000000000 -0700
> @@ -449,6 +449,8 @@
> #define PVR_STB03XXX 0x40310000
> #define PVR_NP405H 0x41410000
> #define PVR_NP405L 0x41610000
> +#define PVR_440EP_RA 0x42221850
> +#define PVR_440EP_RB 0x422218D3
I don't think it's needed. There are plans to get rid of all not-used
PVR defines.
> #define PVR_440GP_RB 0x40120440
> #define PVR_440GP_RC1 0x40120481
> #define PVR_440GP_RC2 0x40200481
--
Eugene
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 2/3] PPC440EP: ibm_emac phy mode bug fix
2005-03-15 17:17 [PATCH 1/3] PPC440EP SoC and Bamboo board support Wade Farnsworth
2005-03-15 18:41 ` Eugene Surovegin
@ 2005-03-15 18:47 ` Wade Farnsworth
2005-03-15 18:58 ` [PATCH 3/3] PPC440EP IBM EMAC support Wade Farnsworth
2005-03-15 19:31 ` 440EP FPU patch McMullan, Jason
2005-03-16 1:43 ` [PATCH 1/3] PPC440EP SoC and Bamboo board support Josh Boyer
3 siblings, 1 reply; 35+ messages in thread
From: Wade Farnsworth @ 2005-03-15 18:47 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 377 bytes --]
This patch fixes a bug in drivers/net/ibm_emac/ibm_emac_core.c where if
the MDI0 bit is set in the ZMII_FER register, then the phy mode is not
detected properly, and SMII is selected by default. This only occurs on
platforms where the phy_mode field of struct ocp_func_emac_data is not
used.
Regards,
Wade Farnsworth
Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
[-- Attachment #2: ibm440ep-ibm_emac-bugfix.patch --]
[-- Type: text/plain, Size: 560 bytes --]
--- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_core.c 2005-03-11 16:25:19.000000000 -0700
+++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_core.c 2005-03-11 16:26:19.000000000 -0700
@@ -315,7 +315,7 @@ static int emac_init_zmii(struct ocp_dev
zmii->base->fer &= ~ZMII_FER_MASK(input);
zmii->base->fer |= zmii_enable[input][mode];
} else {
- switch ((zmii->base->fer & ZMII_FER_MASK(input)) << (4 * input)) {
+ switch (((zmii->base->fer & ZMII_FER_MASK(input)) << (4 * input)) & ~ZMII_MDI0) {
case ZMII_MII0:
mode = MII;
break;
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 3/3] PPC440EP IBM EMAC support
2005-03-15 18:47 ` [PATCH 2/3] PPC440EP: ibm_emac phy mode bug fix Wade Farnsworth
@ 2005-03-15 18:58 ` Wade Farnsworth
2005-03-15 19:22 ` Eugene Surovegin
0 siblings, 1 reply; 35+ messages in thread
From: Wade Farnsworth @ 2005-03-15 18:58 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 155 bytes --]
This patch adds support to the IBM EMAC ethernet driver for the 440EP.
Regards,
Wade Farnsworth
Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
[-- Attachment #2: ibm440ep-ibm_emac.patch --]
[-- Type: text/plain, Size: 2903 bytes --]
--- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-02 00:38:13.000000000 -0700
+++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-11 16:32:01.000000000 -0700
@@ -27,6 +27,12 @@
#include "ibm_emac_phy.h"
+#ifdef CONFIG_BAMBOO
+#define BAMBOO_REV0 (mfspr(PVR) == PVR_440EP_RA)
+#else
+#define BAMBOO_REV0 0
+#endif
+
static int reset_one_mii_phy(struct mii_phy *phy, int phy_id)
{
u16 val;
@@ -109,6 +115,54 @@ static int genmii_setup_aneg(struct mii_
return 0;
}
+static int ac104_setup_aneg(struct mii_phy *phy, u32 advertise)
+{
+ /* Rev. 0 of the IBM 440EP Eval Board has improperly biased RJ-45
+ * sockets, causing 100baseTx to be disabled. Removing inductors L17
+ * and L18 enables 100baseTx, but disables 10baseT. Therefore, only
+ * one speed will be allowed.
+ *
+ * Rev. 1 boards and any other boards using the AC104 can use the
+ * generic function.
+ */
+ u16 ctl, adv, bmcr;
+
+ if (!BAMBOO_REV0)
+ return genmii_setup_aneg(phy, advertise);
+
+
+ phy->autoneg = 1;
+ phy->speed = SPEED_10;
+ phy->duplex = DUPLEX_HALF;
+ phy->pause = 0;
+ phy->advertising = advertise;
+
+ bmcr = phy_read(phy, MII_BMCR);
+
+ /* Setup standard advertise */
+ adv = phy_read(phy, MII_ADVERTISE);
+ adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
+ if (bmcr & BMCR_SPEED100) {
+ if (advertise & ADVERTISED_100baseT_Half)
+ adv |= ADVERTISE_100HALF;
+ if (advertise & ADVERTISED_100baseT_Full)
+ adv |= ADVERTISE_100FULL;
+ } else {
+ if (advertise & ADVERTISED_10baseT_Half)
+ adv |= ADVERTISE_10HALF;
+ if (advertise & ADVERTISED_10baseT_Full)
+ adv |= ADVERTISE_10FULL;
+ }
+ phy_write(phy, MII_ADVERTISE, adv);
+
+ /* Start/Restart aneg */
+ ctl = phy_read(phy, MII_BMCR);
+ ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
+ phy_write(phy, MII_BMCR, ctl);
+
+ return 0;
+}
+
static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
{
u16 ctl;
@@ -226,6 +280,14 @@ static struct mii_phy_ops cis8201_phy_op
read_link:cis8201_read_link
};
+/* AC104 phy ops */
+static struct mii_phy_ops ac104_phy_ops = {
+ setup_aneg:ac104_setup_aneg,
+ setup_forced:genmii_setup_forced,
+ poll_link:genmii_poll_link,
+ read_link:genmii_read_link
+};
+
/* Generic implementation for most 10/100 PHYs */
static struct mii_phy_ops generic_phy_ops = {
setup_aneg:genmii_setup_aneg,
@@ -243,6 +305,15 @@ static struct mii_phy_def cis8201_phy_de
ops:&cis8201_phy_ops
};
+static struct mii_phy_def ac104_phy_def = {
+ phy_id:0x00225540,
+ phy_id_mask:0x00fffff0,
+ name:"AC104 Ethernet",
+ features:MII_BASIC_FEATURES,
+ magic_aneg:0,
+ ops:&ac104_phy_ops
+};
+
static struct mii_phy_def genmii_phy_def = {
phy_id:0x00000000,
phy_id_mask:0x00000000,
@@ -254,6 +325,7 @@ static struct mii_phy_def genmii_phy_def
static struct mii_phy_def *mii_phy_table[] = {
&cis8201_phy_def,
+ &ac104_phy_def,
&genmii_phy_def,
NULL
};
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
2005-03-15 18:41 ` Eugene Surovegin
@ 2005-03-15 19:08 ` Wade Farnsworth
2005-03-15 20:58 ` Jason McMullan
0 siblings, 1 reply; 35+ messages in thread
From: Wade Farnsworth @ 2005-03-15 19:08 UTC (permalink / raw)
To: Eugene Surovegin; +Cc: linuxppc-embedded
On Tue, 2005-03-15 at 11:41, Eugene Surovegin wrote:
[snip]
>
> > diff -uprN linux-2.6.11-bk7/include/asm-ppc/reg.h linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h
> > --- linux-2.6.11-bk7/include/asm-ppc/reg.h 2005-03-11 16:25:22.000000000 -0700
> > +++ linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h 2005-03-14 10:05:47.000000000 -0700
> > @@ -449,6 +449,8 @@
> > #define PVR_STB03XXX 0x40310000
> > #define PVR_NP405H 0x41410000
> > #define PVR_NP405L 0x41610000
> > +#define PVR_440EP_RA 0x42221850
> > +#define PVR_440EP_RB 0x422218D3
>
>
> I don't think it's needed. There are plans to get rid of all not-used
> PVR defines.
The PVR for the Rev A is needed for a workaround in the IBM EMAC code
(see patch 3/3). If there is a better way to do this, or if it would be
better to put the PVR define somewhere else, please let me know.
Thanks for your comments.
Regards,
Wade Farnsworth
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 3/3] PPC440EP IBM EMAC support
2005-03-15 18:58 ` [PATCH 3/3] PPC440EP IBM EMAC support Wade Farnsworth
@ 2005-03-15 19:22 ` Eugene Surovegin
2005-03-15 19:24 ` Eugene Surovegin
2005-03-15 20:37 ` Matt Porter
0 siblings, 2 replies; 35+ messages in thread
From: Eugene Surovegin @ 2005-03-15 19:22 UTC (permalink / raw)
To: Wade Farnsworth; +Cc: linuxppc-embedded
On Tue, Mar 15, 2005 at 11:58:54AM -0700, Wade Farnsworth wrote:
> This patch adds support to the IBM EMAC ethernet driver for the 440EP.
>
> Regards,
> Wade Farnsworth
>
> Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
>
> --- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-02 00:38:13.000000000 -0700
> +++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-11 16:32:01.000000000 -0700
> @@ -27,6 +27,12 @@
>
> #include "ibm_emac_phy.h"
>
> +#ifdef CONFIG_BAMBOO
> +#define BAMBOO_REV0 (mfspr(PVR) == PVR_440EP_RA)
> +#else
> +#define BAMBOO_REV0 0
> +#endif
> +
I really don't like it. Chip revision doesn't imply which board
this code is running on. Please, think of some other way to do this or
drop this completely.
--
Eugene
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 3/3] PPC440EP IBM EMAC support
2005-03-15 19:22 ` Eugene Surovegin
@ 2005-03-15 19:24 ` Eugene Surovegin
2005-03-15 20:43 ` Matt Porter
2005-03-15 20:37 ` Matt Porter
1 sibling, 1 reply; 35+ messages in thread
From: Eugene Surovegin @ 2005-03-15 19:24 UTC (permalink / raw)
To: Wade Farnsworth, linuxppc-embedded
On Tue, Mar 15, 2005 at 11:22:16AM -0800, Eugene Surovegin wrote:
> On Tue, Mar 15, 2005 at 11:58:54AM -0700, Wade Farnsworth wrote:
> > This patch adds support to the IBM EMAC ethernet driver for the 440EP.
> >
> > Regards,
> > Wade Farnsworth
> >
> > Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
> >
>
> > --- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-02 00:38:13.000000000 -0700
> > +++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-11 16:32:01.000000000 -0700
> > @@ -27,6 +27,12 @@
> >
> > #include "ibm_emac_phy.h"
> >
> > +#ifdef CONFIG_BAMBOO
> > +#define BAMBOO_REV0 (mfspr(PVR) == PVR_440EP_RA)
> > +#else
> > +#define BAMBOO_REV0 0
> > +#endif
> > +
>
> I really don't like it. Chip revision doesn't imply which board
> this code is running on. Please, think of some other way to do this or
> drop this completely.
>
Or to phrase this differently, it's better to avoid any board specific
code/defines in network driver.
--
Eugene
^ permalink raw reply [flat|nested] 35+ messages in thread
* 440EP FPU patch
2005-03-15 17:17 [PATCH 1/3] PPC440EP SoC and Bamboo board support Wade Farnsworth
2005-03-15 18:41 ` Eugene Surovegin
2005-03-15 18:47 ` [PATCH 2/3] PPC440EP: ibm_emac phy mode bug fix Wade Farnsworth
@ 2005-03-15 19:31 ` McMullan, Jason
2005-03-15 20:50 ` Matt Porter
2005-03-15 21:09 ` Kumar Gala
2005-03-16 1:43 ` [PATCH 1/3] PPC440EP SoC and Bamboo board support Josh Boyer
3 siblings, 2 replies; 35+ messages in thread
From: McMullan, Jason @ 2005-03-15 19:31 UTC (permalink / raw)
To: Wade Farnsworth; +Cc: linuxppc-embedded
[-- Attachment #1.1: Type: text/plain, Size: 292 bytes --]
This patch (against vanilla 2.4.11.3) breaks out the FPU code for
PowerPC into a common .S code for all the head*.S files.
Less cargo-culted code.
Wade, you may want to integrate this into your 440EP patch.
--
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation
[-- Attachment #1.2: cpu-ppc-fpu.patch --]
[-- Type: text/x-patch, Size: 19624 bytes --]
#### Auto-generated patch ####
Date: Tue, 15 Mar 2005 14:27:50 -0500
Maintainer: Jason McMullan <jason.mcmullan@timesys.com>
Summary: FPU support on PPC chips that don't use the normal head.S
Signed-Off-By: Jason McMullan <jason.mcmullan@timesys.com>
###############################
Index of changes:
arch/ppc/Kconfig | 6
arch/ppc/Makefile | 1
arch/ppc/kernel/Makefile | 1
arch/ppc/kernel/head.S | 276 ----------------------------------------
arch/ppc/kernel/head_44x.S | 13 +
arch/ppc/kernel/traps.c | 2
include/asm-ppc/reg_booke.h | 1
linux/arch/ppc/kernel/fpu.S | 297 ++++++++++++++++++++++++++++++++++++++++++++
8 files changed, 317 insertions(+), 280 deletions(-)
--- linux-orig/arch/ppc/Kconfig
+++ linux/arch/ppc/Kconfig
@@ -53,6 +53,7 @@
config 6xx
bool "6xx/7xx/74xx/52xx/8260"
+ select FPU
help
There are four types of PowerPC chips supported. The more common
types (601, 603, 604, 740, 750, 7400), the Motorola embedded
@@ -83,8 +84,11 @@
config E500
bool "e500"
+
+endchoice
-endchoice
+config FPU
+ bool
config BOOKE
bool
--- linux-orig/arch/ppc/Makefile
+++ linux/arch/ppc/Makefile
@@ -53,6 +53,7 @@
head-$(CONFIG_6xx) += arch/ppc/kernel/idle_6xx.o
head-$(CONFIG_POWER4) += arch/ppc/kernel/idle_power4.o
+head-$(CONFIG_FPU) += arch/ppc/kernel/fpu.o
core-y += arch/ppc/kernel/ arch/ppc/platforms/ \
arch/ppc/mm/ arch/ppc/lib/ arch/ppc/syslib/
--- linux-orig/arch/ppc/kernel/Makefile
+++ linux/arch/ppc/kernel/Makefile
@@ -9,6 +9,7 @@
extra-$(CONFIG_8xx) := head_8xx.o
extra-$(CONFIG_6xx) += idle_6xx.o
extra-$(CONFIG_POWER4) += idle_power4.o
+extra-$(CONFIG_FPU) += fpu.o
extra-y += vmlinux.lds
obj-y := entry.o traps.o irq.o idle.o time.o misc.o \
--- /dev/null
+++ linux/arch/ppc/kernel/fpu.S
@@ -0,0 +1,297 @@
+// FPU support code, moved here from head.S so that it can be used
+// by chips which use other head-whatever.S files.
+
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <asm/mmu.h>
+#include <asm/pgtable.h>
+#include <asm/cputable.h>
+#include <asm/cache.h>
+#include <asm/thread_info.h>
+#include <asm/ppc_asm.h>
+#include <asm/offsets.h>
+
+/*
+ * This task wants to use the FPU now.
+ * On UP, disable FP for the task which had the FPU previously,
+ * and save its floating-point registers in its thread_struct.
+ * Load up this task's FP registers from its thread_struct,
+ * enable the FPU for the current task and return to the task.
+ */
+ .global load_up_fpu
+load_up_fpu:
+ mfmsr r5
+ ori r5,r5,MSR_FP
+#ifdef CONFIG_PPC64BRIDGE
+ clrldi r5,r5,1 /* turn off 64-bit mode */
+#endif /* CONFIG_PPC64BRIDGE */
+ SYNC
+ MTMSRD(r5) /* enable use of fpu now */
+ isync
+/*
+ * For SMP, we don't do lazy FPU switching because it just gets too
+ * horrendously complex, especially when a task switches from one CPU
+ * to another. Instead we call giveup_fpu in switch_to.
+ */
+#ifndef CONFIG_SMP
+ tophys(r6,0) /* get __pa constant */
+ addis r3,r6,last_task_used_math@ha
+ lwz r4,last_task_used_math@l(r3)
+ cmpwi 0,r4,0
+ beq 1f
+ add r4,r4,r6
+ addi r4,r4,THREAD /* want last_task_used_math->thread */
+ SAVE_32FPRS(0, r4)
+ mffs fr0
+ stfd fr0,THREAD_FPSCR-4(r4)
+ lwz r5,PT_REGS(r4)
+ add r5,r5,r6
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ li r10,MSR_FP|MSR_FE0|MSR_FE1
+ andc r4,r4,r10 /* disable FP for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#endif /* CONFIG_SMP */
+ /* enable use of FP after return */
+ mfspr r5,SPRG3 /* current task's THREAD (phys) */
+ lwz r4,THREAD_FPEXC_MODE(r5)
+ ori r9,r9,MSR_FP /* enable FP for current */
+ or r9,r9,r4
+ lfd fr0,THREAD_FPSCR-4(r5)
+ mtfsf 0xff,fr0
+ REST_32FPRS(0, r5)
+#ifndef CONFIG_SMP
+ subi r4,r5,THREAD
+ sub r4,r4,r6
+ stw r4,last_task_used_math@l(r3)
+#endif /* CONFIG_SMP */
+ /* restore registers and return */
+ /* we haven't used ctr or xer or lr */
+ /* fall through to fast_exception_return */
+
+ .global fast_exception_return
+fast_exception_return:
+#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
+ andi. r10,r9,MSR_RI /* check for recoverable interrupt */
+ beq 1f /* if not, we've got problems */
+#endif
+
+2: REST_4GPRS(3, r11)
+ lwz r10,_CCR(r11)
+ REST_GPR(1, r11)
+ mtcr r10
+ lwz r10,_LINK(r11)
+ mtlr r10
+ REST_GPR(10, r11)
+ mtspr SRR1,r9
+ mtspr SRR0,r12
+ REST_GPR(9, r11)
+ REST_GPR(12, r11)
+ lwz r11,GPR11(r11)
+ SYNC
+ RFI
+
+/* check if the exception happened in a restartable section */
+1: lis r3,exc_exit_restart_end@ha
+ addi r3,r3,exc_exit_restart_end@l
+ cmplw r12,r3
+ bge 3f
+ lis r4,exc_exit_restart@ha
+ addi r4,r4,exc_exit_restart@l
+ cmplw r12,r4
+ blt 3f
+ lis r3,fee_restarts@ha
+ tophys(r3,r3)
+ lwz r5,fee_restarts@l(r3)
+ addi r5,r5,1
+ stw r5,fee_restarts@l(r3)
+ mr r12,r4 /* restart at exc_exit_restart */
+ b 2b
+
+ .comm fee_restarts,4
+
+/* aargh, a nonrecoverable interrupt, panic */
+/* aargh, we don't know which trap this is */
+/* but the 601 doesn't implement the RI bit, so assume it's OK */
+3:
+BEGIN_FTR_SECTION
+ b 2b
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+ li r10,-1
+ stw r10,TRAP(r11)
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ lis r10, MSR_KERNEL@h
+ ori r10, r10, MSR_KERNEL@l
+ bl transfer_to_handler_full
+ .long nonrecoverable_exception
+ .long ret_from_except
+
+/*
+ * FP unavailable trap from kernel - print a message, but let
+ * the task use FP in the kernel until it returns to user mode.
+ */
+ .global KernelFP
+KernelFP:
+ lwz r3,_MSR(r1)
+ ori r3,r3,MSR_FP
+ stw r3,_MSR(r1) /* enable use of FP after return */
+ lis r3,86f@h
+ ori r3,r3,86f@l
+ mr r4,r2 /* current */
+ lwz r5,_NIP(r1)
+ bl printk
+ b ret_from_except
+86: .string "floating point used in kernel (task=%p, pc=%x)\n"
+ .align 4,0
+
+#ifdef CONFIG_ALTIVEC
+/* Note that the AltiVec support is closely modeled after the FP
+ * support. Changes to one are likely to be applicable to the
+ * other! */
+ .global load_up_altivec
+load_up_altivec:
+/*
+ * Disable AltiVec for the task which had AltiVec previously,
+ * and save its AltiVec registers in its thread_struct.
+ * Enables AltiVec for use in the kernel on return.
+ * On SMP we know the AltiVec units are free, since we give it up every
+ * switch. -- Kumar
+ */
+ mfmsr r5
+ oris r5,r5,MSR_VEC@h
+ MTMSRD(r5) /* enable use of AltiVec now */
+ isync
+/*
+ * For SMP, we don't do lazy AltiVec switching because it just gets too
+ * horrendously complex, especially when a task switches from one CPU
+ * to another. Instead we call giveup_altivec in switch_to.
+ */
+#ifndef CONFIG_SMP
+ tophys(r6,0)
+ addis r3,r6,last_task_used_altivec@ha
+ lwz r4,last_task_used_altivec@l(r3)
+ cmpwi 0,r4,0
+ beq 1f
+ add r4,r4,r6
+ addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
+ SAVE_32VR(0,r10,r4)
+ mfvscr vr0
+ li r10,THREAD_VSCR
+ stvx vr0,r10,r4
+ lwz r5,PT_REGS(r4)
+ add r5,r5,r6
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ lis r10,MSR_VEC@h
+ andc r4,r4,r10 /* disable altivec for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#endif /* CONFIG_SMP */
+ /* enable use of AltiVec after return */
+ oris r9,r9,MSR_VEC@h
+ mfspr r5,SPRG3 /* current task's THREAD (phys) */
+ li r4,1
+ li r10,THREAD_VSCR
+ stw r4,THREAD_USED_VR(r5)
+ lvx vr0,r10,r5
+ mtvscr vr0
+ REST_32VR(0,r10,r5)
+#ifndef CONFIG_SMP
+ subi r4,r5,THREAD
+ sub r4,r4,r6
+ stw r4,last_task_used_altivec@l(r3)
+#endif /* CONFIG_SMP */
+ /* restore registers and return */
+ /* we haven't used ctr or xer or lr */
+ b fast_exception_return
+
+/*
+ * AltiVec unavailable trap from kernel - print a message, but let
+ * the task use AltiVec in the kernel until it returns to user mode.
+ */
+ .global KernelAltiVec
+KernelAltiVec:
+ lwz r3,_MSR(r1)
+ oris r3,r3,MSR_VEC@h
+ stw r3,_MSR(r1) /* enable use of AltiVec after return */
+ lis r3,87f@h
+ ori r3,r3,87f@l
+ mr r4,r2 /* current */
+ lwz r5,_NIP(r1)
+ bl printk
+ b ret_from_except
+87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
+ .align 4,0
+
+/*
+ * giveup_altivec(tsk)
+ * Disable AltiVec for the task given as the argument,
+ * and save the AltiVec registers in its thread_struct.
+ * Enables AltiVec for use in the kernel on return.
+ */
+
+ .global giveup_altivec
+giveup_altivec:
+ mfmsr r5
+ oris r5,r5,MSR_VEC@h
+ SYNC
+ MTMSRD(r5) /* enable use of AltiVec now */
+ isync
+ cmpwi 0,r3,0
+ beqlr- /* if no previous owner, done */
+ addi r3,r3,THREAD /* want THREAD of task */
+ lwz r5,PT_REGS(r3)
+ cmpwi 0,r5,0
+ SAVE_32VR(0, r4, r3)
+ mfvscr vr0
+ li r4,THREAD_VSCR
+ stvx vr0,r4,r3
+ beq 1f
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ lis r3,MSR_VEC@h
+ andc r4,r4,r3 /* disable AltiVec for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#ifndef CONFIG_SMP
+ li r5,0
+ lis r4,last_task_used_altivec@ha
+ stw r5,last_task_used_altivec@l(r4)
+#endif /* CONFIG_SMP */
+ blr
+#endif /* CONFIG_ALTIVEC */
+
+/*
+ * giveup_fpu(tsk)
+ * Disable FP for the task given as the argument,
+ * and save the floating-point registers in its thread_struct.
+ * Enables the FPU for use in the kernel on return.
+ */
+ .global giveup_fpu
+giveup_fpu:
+ mfmsr r5
+ ori r5,r5,MSR_FP
+ SYNC_601
+ ISYNC_601
+ MTMSRD(r5) /* enable use of fpu now */
+ SYNC_601
+ isync
+ cmpwi 0,r3,0
+ beqlr- /* if no previous owner, done */
+ addi r3,r3,THREAD /* want THREAD of task */
+ lwz r5,PT_REGS(r3)
+ cmpwi 0,r5,0
+ SAVE_32FPRS(0, r3)
+ mffs fr0
+ stfd fr0,THREAD_FPSCR-4(r3)
+ beq 1f
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ li r3,MSR_FP|MSR_FE0|MSR_FE1
+ andc r4,r4,r3 /* disable FP for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#ifndef CONFIG_SMP
+ li r5,0
+ lis r4,last_task_used_math@ha
+ stw r5,last_task_used_math@l(r4)
+#endif /* CONFIG_SMP */
+ blr
--- linux-orig/arch/ppc/kernel/head.S
+++ linux/arch/ppc/kernel/head.S
@@ -776,282 +776,6 @@
#endif /* CONFIG_PPC64BRIDGE */
/*
- * This task wants to use the FPU now.
- * On UP, disable FP for the task which had the FPU previously,
- * and save its floating-point registers in its thread_struct.
- * Load up this task's FP registers from its thread_struct,
- * enable the FPU for the current task and return to the task.
- */
-load_up_fpu:
- mfmsr r5
- ori r5,r5,MSR_FP
-#ifdef CONFIG_PPC64BRIDGE
- clrldi r5,r5,1 /* turn off 64-bit mode */
-#endif /* CONFIG_PPC64BRIDGE */
- SYNC
- MTMSRD(r5) /* enable use of fpu now */
- isync
-/*
- * For SMP, we don't do lazy FPU switching because it just gets too
- * horrendously complex, especially when a task switches from one CPU
- * to another. Instead we call giveup_fpu in switch_to.
- */
-#ifndef CONFIG_SMP
- tophys(r6,0) /* get __pa constant */
- addis r3,r6,last_task_used_math@ha
- lwz r4,last_task_used_math@l(r3)
- cmpwi 0,r4,0
- beq 1f
- add r4,r4,r6
- addi r4,r4,THREAD /* want last_task_used_math->thread */
- SAVE_32FPRS(0, r4)
- mffs fr0
- stfd fr0,THREAD_FPSCR-4(r4)
- lwz r5,PT_REGS(r4)
- add r5,r5,r6
- lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
- li r10,MSR_FP|MSR_FE0|MSR_FE1
- andc r4,r4,r10 /* disable FP for previous task */
- stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
- /* enable use of FP after return */
- mfspr r5,SPRG3 /* current task's THREAD (phys) */
- lwz r4,THREAD_FPEXC_MODE(r5)
- ori r9,r9,MSR_FP /* enable FP for current */
- or r9,r9,r4
- lfd fr0,THREAD_FPSCR-4(r5)
- mtfsf 0xff,fr0
- REST_32FPRS(0, r5)
-#ifndef CONFIG_SMP
- subi r4,r5,THREAD
- sub r4,r4,r6
- stw r4,last_task_used_math@l(r3)
-#endif /* CONFIG_SMP */
- /* restore registers and return */
- /* we haven't used ctr or xer or lr */
- /* fall through to fast_exception_return */
-
- .globl fast_exception_return
-fast_exception_return:
- andi. r10,r9,MSR_RI /* check for recoverable interrupt */
- beq 1f /* if not, we've got problems */
-2: REST_4GPRS(3, r11)
- lwz r10,_CCR(r11)
- REST_GPR(1, r11)
- mtcr r10
- lwz r10,_LINK(r11)
- mtlr r10
- REST_GPR(10, r11)
- mtspr SRR1,r9
- mtspr SRR0,r12
- REST_GPR(9, r11)
- REST_GPR(12, r11)
- lwz r11,GPR11(r11)
- SYNC
- RFI
-
-/* check if the exception happened in a restartable section */
-1: lis r3,exc_exit_restart_end@ha
- addi r3,r3,exc_exit_restart_end@l
- cmplw r12,r3
- bge 3f
- lis r4,exc_exit_restart@ha
- addi r4,r4,exc_exit_restart@l
- cmplw r12,r4
- blt 3f
- lis r3,fee_restarts@ha
- tophys(r3,r3)
- lwz r5,fee_restarts@l(r3)
- addi r5,r5,1
- stw r5,fee_restarts@l(r3)
- mr r12,r4 /* restart at exc_exit_restart */
- b 2b
-
- .comm fee_restarts,4
-
-/* aargh, a nonrecoverable interrupt, panic */
-/* aargh, we don't know which trap this is */
-/* but the 601 doesn't implement the RI bit, so assume it's OK */
-3:
-BEGIN_FTR_SECTION
- b 2b
-END_FTR_SECTION_IFSET(CPU_FTR_601)
- li r10,-1
- stw r10,TRAP(r11)
- addi r3,r1,STACK_FRAME_OVERHEAD
- li r10,MSR_KERNEL
- bl transfer_to_handler_full
- .long nonrecoverable_exception
- .long ret_from_except
-
-/*
- * FP unavailable trap from kernel - print a message, but let
- * the task use FP in the kernel until it returns to user mode.
- */
-KernelFP:
- lwz r3,_MSR(r1)
- ori r3,r3,MSR_FP
- stw r3,_MSR(r1) /* enable use of FP after return */
- lis r3,86f@h
- ori r3,r3,86f@l
- mr r4,r2 /* current */
- lwz r5,_NIP(r1)
- bl printk
- b ret_from_except
-86: .string "floating point used in kernel (task=%p, pc=%x)\n"
- .align 4,0
-
-#ifdef CONFIG_ALTIVEC
-/* Note that the AltiVec support is closely modeled after the FP
- * support. Changes to one are likely to be applicable to the
- * other! */
-load_up_altivec:
-/*
- * Disable AltiVec for the task which had AltiVec previously,
- * and save its AltiVec registers in its thread_struct.
- * Enables AltiVec for use in the kernel on return.
- * On SMP we know the AltiVec units are free, since we give it up every
- * switch. -- Kumar
- */
- mfmsr r5
- oris r5,r5,MSR_VEC@h
- MTMSRD(r5) /* enable use of AltiVec now */
- isync
-/*
- * For SMP, we don't do lazy AltiVec switching because it just gets too
- * horrendously complex, especially when a task switches from one CPU
- * to another. Instead we call giveup_altivec in switch_to.
- */
-#ifndef CONFIG_SMP
- tophys(r6,0)
- addis r3,r6,last_task_used_altivec@ha
- lwz r4,last_task_used_altivec@l(r3)
- cmpwi 0,r4,0
- beq 1f
- add r4,r4,r6
- addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
- SAVE_32VR(0,r10,r4)
- mfvscr vr0
- li r10,THREAD_VSCR
- stvx vr0,r10,r4
- lwz r5,PT_REGS(r4)
- add r5,r5,r6
- lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
- lis r10,MSR_VEC@h
- andc r4,r4,r10 /* disable altivec for previous task */
- stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
- /* enable use of AltiVec after return */
- oris r9,r9,MSR_VEC@h
- mfspr r5,SPRG3 /* current task's THREAD (phys) */
- li r4,1
- li r10,THREAD_VSCR
- stw r4,THREAD_USED_VR(r5)
- lvx vr0,r10,r5
- mtvscr vr0
- REST_32VR(0,r10,r5)
-#ifndef CONFIG_SMP
- subi r4,r5,THREAD
- sub r4,r4,r6
- stw r4,last_task_used_altivec@l(r3)
-#endif /* CONFIG_SMP */
- /* restore registers and return */
- /* we haven't used ctr or xer or lr */
- b fast_exception_return
-
-/*
- * AltiVec unavailable trap from kernel - print a message, but let
- * the task use AltiVec in the kernel until it returns to user mode.
- */
-KernelAltiVec:
- lwz r3,_MSR(r1)
- oris r3,r3,MSR_VEC@h
- stw r3,_MSR(r1) /* enable use of AltiVec after return */
- lis r3,87f@h
- ori r3,r3,87f@l
- mr r4,r2 /* current */
- lwz r5,_NIP(r1)
- bl printk
- b ret_from_except
-87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
- .align 4,0
-
-/*
- * giveup_altivec(tsk)
- * Disable AltiVec for the task given as the argument,
- * and save the AltiVec registers in its thread_struct.
- * Enables AltiVec for use in the kernel on return.
- */
-
- .globl giveup_altivec
-giveup_altivec:
- mfmsr r5
- oris r5,r5,MSR_VEC@h
- SYNC
- MTMSRD(r5) /* enable use of AltiVec now */
- isync
- cmpwi 0,r3,0
- beqlr- /* if no previous owner, done */
- addi r3,r3,THREAD /* want THREAD of task */
- lwz r5,PT_REGS(r3)
- cmpwi 0,r5,0
- SAVE_32VR(0, r4, r3)
- mfvscr vr0
- li r4,THREAD_VSCR
- stvx vr0,r4,r3
- beq 1f
- lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
- lis r3,MSR_VEC@h
- andc r4,r4,r3 /* disable AltiVec for previous task */
- stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
- li r5,0
- lis r4,last_task_used_altivec@ha
- stw r5,last_task_used_altivec@l(r4)
-#endif /* CONFIG_SMP */
- blr
-#endif /* CONFIG_ALTIVEC */
-
-/*
- * giveup_fpu(tsk)
- * Disable FP for the task given as the argument,
- * and save the floating-point registers in its thread_struct.
- * Enables the FPU for use in the kernel on return.
- */
- .globl giveup_fpu
-giveup_fpu:
- mfmsr r5
- ori r5,r5,MSR_FP
- SYNC_601
- ISYNC_601
- MTMSRD(r5) /* enable use of fpu now */
- SYNC_601
- isync
- cmpwi 0,r3,0
- beqlr- /* if no previous owner, done */
- addi r3,r3,THREAD /* want THREAD of task */
- lwz r5,PT_REGS(r3)
- cmpwi 0,r5,0
- SAVE_32FPRS(0, r3)
- mffs fr0
- stfd fr0,THREAD_FPSCR-4(r3)
- beq 1f
- lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
- li r3,MSR_FP|MSR_FE0|MSR_FE1
- andc r4,r4,r3 /* disable FP for previous task */
- stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
- li r5,0
- lis r4,last_task_used_math@ha
- stw r5,last_task_used_math@l(r4)
-#endif /* CONFIG_SMP */
- blr
-
-/*
* This code is jumped to from the startup code to copy
* the kernel image to physical address 0.
*/
--- linux-orig/arch/ppc/kernel/head_44x.S
+++ linux/arch/ppc/kernel/head_44x.S
@@ -425,8 +425,15 @@
/* Program Interrupt */
PROGRAM_EXCEPTION
- /* Floating Point Unavailable Interrupt */
+#ifdef CONFIG_FPU
+ START_EXCEPTION(FloatingPointUnavailable)
+ NORMAL_EXCEPTION_PROLOG
+ bne load_up_fpu /* if from user, just load it up */
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ EXC_XFER_EE_LITE(0x800, KernelFP)
+#else
EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
+#endif
/* System Call Interrupt */
START_EXCEPTION(SystemCall)
@@ -686,9 +693,11 @@
*
* The 44x core does not have an FPU.
*/
+#ifndef CONFIG_FPU
_GLOBAL(giveup_fpu)
blr
-
+#endif
+
/*
* extern void abort(void)
*
--- linux-orig/arch/ppc/kernel/traps.c
+++ linux/arch/ppc/kernel/traps.c
@@ -176,7 +176,7 @@
#else
#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
#endif
-#define REASON_FP 0
+#define REASON_FP ESR_FP
#define REASON_ILLEGAL ESR_PIL
#define REASON_PRIVILEGED ESR_PPR
#define REASON_TRAP ESR_PTR
--- linux-orig/include/asm-ppc/reg_booke.h
+++ linux/include/asm-ppc/reg_booke.h
@@ -305,6 +305,7 @@
#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
#define ESR_PTR 0x02000000 /* Program Exception - Trap */
+#define ESR_FP 0x01000000 /* Floating Point Operation */
#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
#define ESR_ST 0x00800000 /* Store Operation */
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 3/3] PPC440EP IBM EMAC support
2005-03-15 19:22 ` Eugene Surovegin
2005-03-15 19:24 ` Eugene Surovegin
@ 2005-03-15 20:37 ` Matt Porter
2005-03-28 17:52 ` Wade Farnsworth
1 sibling, 1 reply; 35+ messages in thread
From: Matt Porter @ 2005-03-15 20:37 UTC (permalink / raw)
To: Wade Farnsworth, linuxppc-embedded
On Tue, Mar 15, 2005 at 11:22:16AM -0800, Eugene Surovegin wrote:
> On Tue, Mar 15, 2005 at 11:58:54AM -0700, Wade Farnsworth wrote:
> > This patch adds support to the IBM EMAC ethernet driver for the 440EP.
> >
> > Regards,
> > Wade Farnsworth
> >
> > Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
> >
>
> > --- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-02 00:38:13.000000000 -0700
> > +++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-11 16:32:01.000000000 -0700
> > @@ -27,6 +27,12 @@
> >
> > #include "ibm_emac_phy.h"
> >
> > +#ifdef CONFIG_BAMBOO
> > +#define BAMBOO_REV0 (mfspr(PVR) == PVR_440EP_RA)
> > +#else
> > +#define BAMBOO_REV0 0
> > +#endif
> > +
>
> I really don't like it. Chip revision doesn't imply which board
> this code is running on. Please, think of some other way to do this or
> drop this completely.
Wade and I talked about this one before and there is no direct way
to detect the board revision on this platform. Given that, I
think that if the PVR of the 440EP in a Bamboo board does imply
the board revision, then this is appropriate.
-Matt
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 3/3] PPC440EP IBM EMAC support
2005-03-15 19:24 ` Eugene Surovegin
@ 2005-03-15 20:43 ` Matt Porter
0 siblings, 0 replies; 35+ messages in thread
From: Matt Porter @ 2005-03-15 20:43 UTC (permalink / raw)
To: Wade Farnsworth, linuxppc-embedded
On Tue, Mar 15, 2005 at 11:24:24AM -0800, Eugene Surovegin wrote:
> On Tue, Mar 15, 2005 at 11:22:16AM -0800, Eugene Surovegin wrote:
> > On Tue, Mar 15, 2005 at 11:58:54AM -0700, Wade Farnsworth wrote:
> > > This patch adds support to the IBM EMAC ethernet driver for the 440EP.
> > >
> > > Regards,
> > > Wade Farnsworth
> > >
> > > Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
> > >
> >
> > > --- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-02 00:38:13.000000000 -0700
> > > +++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-11 16:32:01.000000000 -0700
> > > @@ -27,6 +27,12 @@
> > >
> > > #include "ibm_emac_phy.h"
> > >
> > > +#ifdef CONFIG_BAMBOO
> > > +#define BAMBOO_REV0 (mfspr(PVR) == PVR_440EP_RA)
> > > +#else
> > > +#define BAMBOO_REV0 0
> > > +#endif
> > > +
> >
> > I really don't like it. Chip revision doesn't imply which board
> > this code is running on. Please, think of some other way to do this or
> > drop this completely.
> >
>
> Or to phrase this differently, it's better to avoid any board specific
> code/defines in network driver.
Indeed it's better. However, I made the suggestion that it's not
worth the effort to add in another hook to provide board specific
phy help to ibm_emac/ at this time. I think the hack can exist
until a proper hook can be added to the phy lib stuff that should
be used in the future.
If you think that's too far off, we can go ahead and add another hook
so the hack can be moved into bamboo.c where it ideally belongs.
-Matt
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-15 19:31 ` 440EP FPU patch McMullan, Jason
@ 2005-03-15 20:50 ` Matt Porter
2005-03-15 21:09 ` Kumar Gala
1 sibling, 0 replies; 35+ messages in thread
From: Matt Porter @ 2005-03-15 20:50 UTC (permalink / raw)
To: McMullan, Jason; +Cc: linuxppc-embedded
On Tue, Mar 15, 2005 at 02:27:57PM -0500, McMullan, Jason wrote:
> This patch (against vanilla 2.4.11.3) breaks out the FPU code for
> PowerPC into a common .S code for all the head*.S files.
>
> Less cargo-culted code.
>
> Wade, you may want to integrate this into your 440EP patch.
Hi Jason,
Can you change CONFIG_FPU->CONFIG_PPC_FPU? Otherwise, this looks
like exactly what we need to me.
-Matt
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
2005-03-15 19:08 ` Wade Farnsworth
@ 2005-03-15 20:58 ` Jason McMullan
2005-03-15 21:38 ` Wade Farnsworth
0 siblings, 1 reply; 35+ messages in thread
From: Jason McMullan @ 2005-03-15 20:58 UTC (permalink / raw)
To: Wade Farnsworth; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 405 bytes --]
I think your setup for BAMBOO_PCIL0_PTM1MS is actually incorrect.
According to the AMCC 440EP docs, BAMBOO_PCIL0_PTM1MS is a mask,
so the correct code should look more like:
memory_size = 0xffffffff - (memory_size - 1);
PCI_WRITEL(memory_size | 1, BAMBOO_PCIL0_PTM1MS);
(assuming 'memory_size' is a power of 2)
--
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-15 19:31 ` 440EP FPU patch McMullan, Jason
2005-03-15 20:50 ` Matt Porter
@ 2005-03-15 21:09 ` Kumar Gala
2005-03-15 22:18 ` Jason McMullan
1 sibling, 1 reply; 35+ messages in thread
From: Kumar Gala @ 2005-03-15 21:09 UTC (permalink / raw)
To: McMullan, Jason; +Cc: linuxppc-embedded
Jason,
A few comments:
1. Change config option to CONFIG_PPC_FPU
2. split out altivec support into a separate file, most likely just
move it into vector.S
3. Get ride of the C++ comments
- kumar
On Mar 15, 2005, at 1:27 PM, McMullan, Jason wrote:
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
> Date: March 15, 2005 1:43:37 PM CST
> Subject:
>
>
>
> Date: March 15, 2005 1:43:37 PM CST
> Subject:
>
>
> <ATT110571.txt><cpu-ppc-fpu.patch>
>
> <signature.asc>
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
2005-03-15 20:58 ` Jason McMullan
@ 2005-03-15 21:38 ` Wade Farnsworth
0 siblings, 0 replies; 35+ messages in thread
From: Wade Farnsworth @ 2005-03-15 21:38 UTC (permalink / raw)
To: Jason McMullan; +Cc: linuxppc-embedded
On Tue, 2005-03-15 at 13:58, Jason McMullan wrote:
> I think your setup for BAMBOO_PCIL0_PTM1MS is actually incorrect.
> According to the AMCC 440EP docs, BAMBOO_PCIL0_PTM1MS is a mask,
> so the correct code should look more like:
>
> memory_size = 0xffffffff - (memory_size - 1);
> PCI_WRITEL(memory_size | 1, BAMBOO_PCIL0_PTM1MS);
>
> (assuming 'memory_size' is a power of 2)
Jason,
I think you're right. Your way is much more concise too.
Thanks,
Wade Farnsworth
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-15 21:09 ` Kumar Gala
@ 2005-03-15 22:18 ` Jason McMullan
2005-03-16 7:22 ` Kumar Gala
0 siblings, 1 reply; 35+ messages in thread
From: Jason McMullan @ 2005-03-15 22:18 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-embedded
[-- Attachment #1.1: Type: text/plain, Size: 372 bytes --]
On Tue, 2005-03-15 at 15:09 -0600, Kumar Gala wrote:
> 1. Change config option to CONFIG_PPC_FPU
> 2. split out altivec support into a separate file, most likely just
> move it into vector.S
> 3. Get ride of the C++ comments
Changes made, as per your suggestions, and new patch attached.
--
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation
[-- Attachment #1.2: cpu-ppc-fpu.patch --]
[-- Type: text/x-patch, Size: 19842 bytes --]
#### Auto-generated patch ####
Date: Tue, 15 Mar 2005 17:16:47 -0500
Maintainer: Jason McMullan <jason.mcmullan@timesys.com>
Summary: FPU support on PPC chips that don't use the normal head.S
Signed-Off-By: Jason McMullan <jason.mcmullan@timesys.com>
###############################
Index of changes:
arch/ppc/Kconfig | 6
arch/ppc/Makefile | 1
arch/ppc/kernel/Makefile | 1
arch/ppc/kernel/head.S | 276 --------------------------------------------
arch/ppc/kernel/head_44x.S | 12 +
arch/ppc/kernel/traps.c | 2
arch/ppc/kernel/vector.S | 116 ++++++++++++++++++
include/asm-ppc/reg_booke.h | 1
linux/arch/ppc/kernel/fpu.S | 183 +++++++++++++++++++++++++++++
9 files changed, 319 insertions(+), 279 deletions(-)
--- linux-orig/arch/ppc/Kconfig
+++ linux/arch/ppc/Kconfig
@@ -53,6 +53,7 @@
config 6xx
bool "6xx/7xx/74xx/52xx/8260"
+ select PPC_FPU
help
There are four types of PowerPC chips supported. The more common
types (601, 603, 604, 740, 750, 7400), the Motorola embedded
@@ -83,8 +84,11 @@
config E500
bool "e500"
+
+endchoice
-endchoice
+config PPC_FPU
+ bool
config BOOKE
bool
--- linux-orig/arch/ppc/Makefile
+++ linux/arch/ppc/Makefile
@@ -53,6 +53,7 @@
head-$(CONFIG_6xx) += arch/ppc/kernel/idle_6xx.o
head-$(CONFIG_POWER4) += arch/ppc/kernel/idle_power4.o
+head-$(CONFIG_PPC_FPU) += arch/ppc/kernel/fpu.o
core-y += arch/ppc/kernel/ arch/ppc/platforms/ \
arch/ppc/mm/ arch/ppc/lib/ arch/ppc/syslib/
--- linux-orig/arch/ppc/kernel/Makefile
+++ linux/arch/ppc/kernel/Makefile
@@ -9,6 +9,7 @@
extra-$(CONFIG_8xx) := head_8xx.o
extra-$(CONFIG_6xx) += idle_6xx.o
extra-$(CONFIG_POWER4) += idle_power4.o
+extra-$(CONFIG_PPC_FPU) += fpu.o
extra-y += vmlinux.lds
obj-y := entry.o traps.o irq.o idle.o time.o misc.o \
--- /dev/null
+++ linux/arch/ppc/kernel/fpu.S
@@ -0,0 +1,183 @@
+/* FPU support code, moved here from head.S so that it can be used
+ * by chips which use other head-whatever.S files.
+ */
+
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <asm/mmu.h>
+#include <asm/pgtable.h>
+#include <asm/cputable.h>
+#include <asm/cache.h>
+#include <asm/thread_info.h>
+#include <asm/ppc_asm.h>
+#include <asm/offsets.h>
+
+/*
+ * This task wants to use the FPU now.
+ * On UP, disable FP for the task which had the FPU previously,
+ * and save its floating-point registers in its thread_struct.
+ * Load up this task's FP registers from its thread_struct,
+ * enable the FPU for the current task and return to the task.
+ */
+ .global load_up_fpu
+load_up_fpu:
+ mfmsr r5
+ ori r5,r5,MSR_FP
+#ifdef CONFIG_PPC64BRIDGE
+ clrldi r5,r5,1 /* turn off 64-bit mode */
+#endif /* CONFIG_PPC64BRIDGE */
+ SYNC
+ MTMSRD(r5) /* enable use of fpu now */
+ isync
+/*
+ * For SMP, we don't do lazy FPU switching because it just gets too
+ * horrendously complex, especially when a task switches from one CPU
+ * to another. Instead we call giveup_fpu in switch_to.
+ */
+#ifndef CONFIG_SMP
+ tophys(r6,0) /* get __pa constant */
+ addis r3,r6,last_task_used_math@ha
+ lwz r4,last_task_used_math@l(r3)
+ cmpwi 0,r4,0
+ beq 1f
+ add r4,r4,r6
+ addi r4,r4,THREAD /* want last_task_used_math->thread */
+ SAVE_32FPRS(0, r4)
+ mffs fr0
+ stfd fr0,THREAD_FPSCR-4(r4)
+ lwz r5,PT_REGS(r4)
+ add r5,r5,r6
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ li r10,MSR_FP|MSR_FE0|MSR_FE1
+ andc r4,r4,r10 /* disable FP for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#endif /* CONFIG_SMP */
+ /* enable use of FP after return */
+ mfspr r5,SPRG3 /* current task's THREAD (phys) */
+ lwz r4,THREAD_FPEXC_MODE(r5)
+ ori r9,r9,MSR_FP /* enable FP for current */
+ or r9,r9,r4
+ lfd fr0,THREAD_FPSCR-4(r5)
+ mtfsf 0xff,fr0
+ REST_32FPRS(0, r5)
+#ifndef CONFIG_SMP
+ subi r4,r5,THREAD
+ sub r4,r4,r6
+ stw r4,last_task_used_math@l(r3)
+#endif /* CONFIG_SMP */
+ /* restore registers and return */
+ /* we haven't used ctr or xer or lr */
+ /* fall through to fast_exception_return */
+
+ .global fast_exception_return
+fast_exception_return:
+#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
+ andi. r10,r9,MSR_RI /* check for recoverable interrupt */
+ beq 1f /* if not, we've got problems */
+#endif
+
+2: REST_4GPRS(3, r11)
+ lwz r10,_CCR(r11)
+ REST_GPR(1, r11)
+ mtcr r10
+ lwz r10,_LINK(r11)
+ mtlr r10
+ REST_GPR(10, r11)
+ mtspr SRR1,r9
+ mtspr SRR0,r12
+ REST_GPR(9, r11)
+ REST_GPR(12, r11)
+ lwz r11,GPR11(r11)
+ SYNC
+ RFI
+
+/* check if the exception happened in a restartable section */
+1: lis r3,exc_exit_restart_end@ha
+ addi r3,r3,exc_exit_restart_end@l
+ cmplw r12,r3
+ bge 3f
+ lis r4,exc_exit_restart@ha
+ addi r4,r4,exc_exit_restart@l
+ cmplw r12,r4
+ blt 3f
+ lis r3,fee_restarts@ha
+ tophys(r3,r3)
+ lwz r5,fee_restarts@l(r3)
+ addi r5,r5,1
+ stw r5,fee_restarts@l(r3)
+ mr r12,r4 /* restart at exc_exit_restart */
+ b 2b
+
+ .comm fee_restarts,4
+
+/* aargh, a nonrecoverable interrupt, panic */
+/* aargh, we don't know which trap this is */
+/* but the 601 doesn't implement the RI bit, so assume it's OK */
+3:
+BEGIN_FTR_SECTION
+ b 2b
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+ li r10,-1
+ stw r10,TRAP(r11)
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ lis r10, MSR_KERNEL@h
+ ori r10, r10, MSR_KERNEL@l
+ bl transfer_to_handler_full
+ .long nonrecoverable_exception
+ .long ret_from_except
+
+/*
+ * FP unavailable trap from kernel - print a message, but let
+ * the task use FP in the kernel until it returns to user mode.
+ */
+ .global KernelFP
+KernelFP:
+ lwz r3,_MSR(r1)
+ ori r3,r3,MSR_FP
+ stw r3,_MSR(r1) /* enable use of FP after return */
+ lis r3,86f@h
+ ori r3,r3,86f@l
+ mr r4,r2 /* current */
+ lwz r5,_NIP(r1)
+ bl printk
+ b ret_from_except
+86: .string "floating point used in kernel (task=%p, pc=%x)\n"
+ .align 4,0
+
+/*
+ * giveup_fpu(tsk)
+ * Disable FP for the task given as the argument,
+ * and save the floating-point registers in its thread_struct.
+ * Enables the FPU for use in the kernel on return.
+ */
+ .global giveup_fpu
+giveup_fpu:
+ mfmsr r5
+ ori r5,r5,MSR_FP
+ SYNC_601
+ ISYNC_601
+ MTMSRD(r5) /* enable use of fpu now */
+ SYNC_601
+ isync
+ cmpwi 0,r3,0
+ beqlr- /* if no previous owner, done */
+ addi r3,r3,THREAD /* want THREAD of task */
+ lwz r5,PT_REGS(r3)
+ cmpwi 0,r5,0
+ SAVE_32FPRS(0, r3)
+ mffs fr0
+ stfd fr0,THREAD_FPSCR-4(r3)
+ beq 1f
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ li r3,MSR_FP|MSR_FE0|MSR_FE1
+ andc r4,r4,r3 /* disable FP for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#ifndef CONFIG_SMP
+ li r5,0
+ lis r4,last_task_used_math@ha
+ stw r5,last_task_used_math@l(r4)
+#endif /* CONFIG_SMP */
+ blr
--- linux-orig/arch/ppc/kernel/head.S
+++ linux/arch/ppc/kernel/head.S
@@ -776,282 +776,6 @@
#endif /* CONFIG_PPC64BRIDGE */
/*
- * This task wants to use the FPU now.
- * On UP, disable FP for the task which had the FPU previously,
- * and save its floating-point registers in its thread_struct.
- * Load up this task's FP registers from its thread_struct,
- * enable the FPU for the current task and return to the task.
- */
-load_up_fpu:
- mfmsr r5
- ori r5,r5,MSR_FP
-#ifdef CONFIG_PPC64BRIDGE
- clrldi r5,r5,1 /* turn off 64-bit mode */
-#endif /* CONFIG_PPC64BRIDGE */
- SYNC
- MTMSRD(r5) /* enable use of fpu now */
- isync
-/*
- * For SMP, we don't do lazy FPU switching because it just gets too
- * horrendously complex, especially when a task switches from one CPU
- * to another. Instead we call giveup_fpu in switch_to.
- */
-#ifndef CONFIG_SMP
- tophys(r6,0) /* get __pa constant */
- addis r3,r6,last_task_used_math@ha
- lwz r4,last_task_used_math@l(r3)
- cmpwi 0,r4,0
- beq 1f
- add r4,r4,r6
- addi r4,r4,THREAD /* want last_task_used_math->thread */
- SAVE_32FPRS(0, r4)
- mffs fr0
- stfd fr0,THREAD_FPSCR-4(r4)
- lwz r5,PT_REGS(r4)
- add r5,r5,r6
- lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
- li r10,MSR_FP|MSR_FE0|MSR_FE1
- andc r4,r4,r10 /* disable FP for previous task */
- stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
- /* enable use of FP after return */
- mfspr r5,SPRG3 /* current task's THREAD (phys) */
- lwz r4,THREAD_FPEXC_MODE(r5)
- ori r9,r9,MSR_FP /* enable FP for current */
- or r9,r9,r4
- lfd fr0,THREAD_FPSCR-4(r5)
- mtfsf 0xff,fr0
- REST_32FPRS(0, r5)
-#ifndef CONFIG_SMP
- subi r4,r5,THREAD
- sub r4,r4,r6
- stw r4,last_task_used_math@l(r3)
-#endif /* CONFIG_SMP */
- /* restore registers and return */
- /* we haven't used ctr or xer or lr */
- /* fall through to fast_exception_return */
-
- .globl fast_exception_return
-fast_exception_return:
- andi. r10,r9,MSR_RI /* check for recoverable interrupt */
- beq 1f /* if not, we've got problems */
-2: REST_4GPRS(3, r11)
- lwz r10,_CCR(r11)
- REST_GPR(1, r11)
- mtcr r10
- lwz r10,_LINK(r11)
- mtlr r10
- REST_GPR(10, r11)
- mtspr SRR1,r9
- mtspr SRR0,r12
- REST_GPR(9, r11)
- REST_GPR(12, r11)
- lwz r11,GPR11(r11)
- SYNC
- RFI
-
-/* check if the exception happened in a restartable section */
-1: lis r3,exc_exit_restart_end@ha
- addi r3,r3,exc_exit_restart_end@l
- cmplw r12,r3
- bge 3f
- lis r4,exc_exit_restart@ha
- addi r4,r4,exc_exit_restart@l
- cmplw r12,r4
- blt 3f
- lis r3,fee_restarts@ha
- tophys(r3,r3)
- lwz r5,fee_restarts@l(r3)
- addi r5,r5,1
- stw r5,fee_restarts@l(r3)
- mr r12,r4 /* restart at exc_exit_restart */
- b 2b
-
- .comm fee_restarts,4
-
-/* aargh, a nonrecoverable interrupt, panic */
-/* aargh, we don't know which trap this is */
-/* but the 601 doesn't implement the RI bit, so assume it's OK */
-3:
-BEGIN_FTR_SECTION
- b 2b
-END_FTR_SECTION_IFSET(CPU_FTR_601)
- li r10,-1
- stw r10,TRAP(r11)
- addi r3,r1,STACK_FRAME_OVERHEAD
- li r10,MSR_KERNEL
- bl transfer_to_handler_full
- .long nonrecoverable_exception
- .long ret_from_except
-
-/*
- * FP unavailable trap from kernel - print a message, but let
- * the task use FP in the kernel until it returns to user mode.
- */
-KernelFP:
- lwz r3,_MSR(r1)
- ori r3,r3,MSR_FP
- stw r3,_MSR(r1) /* enable use of FP after return */
- lis r3,86f@h
- ori r3,r3,86f@l
- mr r4,r2 /* current */
- lwz r5,_NIP(r1)
- bl printk
- b ret_from_except
-86: .string "floating point used in kernel (task=%p, pc=%x)\n"
- .align 4,0
-
-#ifdef CONFIG_ALTIVEC
-/* Note that the AltiVec support is closely modeled after the FP
- * support. Changes to one are likely to be applicable to the
- * other! */
-load_up_altivec:
-/*
- * Disable AltiVec for the task which had AltiVec previously,
- * and save its AltiVec registers in its thread_struct.
- * Enables AltiVec for use in the kernel on return.
- * On SMP we know the AltiVec units are free, since we give it up every
- * switch. -- Kumar
- */
- mfmsr r5
- oris r5,r5,MSR_VEC@h
- MTMSRD(r5) /* enable use of AltiVec now */
- isync
-/*
- * For SMP, we don't do lazy AltiVec switching because it just gets too
- * horrendously complex, especially when a task switches from one CPU
- * to another. Instead we call giveup_altivec in switch_to.
- */
-#ifndef CONFIG_SMP
- tophys(r6,0)
- addis r3,r6,last_task_used_altivec@ha
- lwz r4,last_task_used_altivec@l(r3)
- cmpwi 0,r4,0
- beq 1f
- add r4,r4,r6
- addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
- SAVE_32VR(0,r10,r4)
- mfvscr vr0
- li r10,THREAD_VSCR
- stvx vr0,r10,r4
- lwz r5,PT_REGS(r4)
- add r5,r5,r6
- lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
- lis r10,MSR_VEC@h
- andc r4,r4,r10 /* disable altivec for previous task */
- stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
- /* enable use of AltiVec after return */
- oris r9,r9,MSR_VEC@h
- mfspr r5,SPRG3 /* current task's THREAD (phys) */
- li r4,1
- li r10,THREAD_VSCR
- stw r4,THREAD_USED_VR(r5)
- lvx vr0,r10,r5
- mtvscr vr0
- REST_32VR(0,r10,r5)
-#ifndef CONFIG_SMP
- subi r4,r5,THREAD
- sub r4,r4,r6
- stw r4,last_task_used_altivec@l(r3)
-#endif /* CONFIG_SMP */
- /* restore registers and return */
- /* we haven't used ctr or xer or lr */
- b fast_exception_return
-
-/*
- * AltiVec unavailable trap from kernel - print a message, but let
- * the task use AltiVec in the kernel until it returns to user mode.
- */
-KernelAltiVec:
- lwz r3,_MSR(r1)
- oris r3,r3,MSR_VEC@h
- stw r3,_MSR(r1) /* enable use of AltiVec after return */
- lis r3,87f@h
- ori r3,r3,87f@l
- mr r4,r2 /* current */
- lwz r5,_NIP(r1)
- bl printk
- b ret_from_except
-87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
- .align 4,0
-
-/*
- * giveup_altivec(tsk)
- * Disable AltiVec for the task given as the argument,
- * and save the AltiVec registers in its thread_struct.
- * Enables AltiVec for use in the kernel on return.
- */
-
- .globl giveup_altivec
-giveup_altivec:
- mfmsr r5
- oris r5,r5,MSR_VEC@h
- SYNC
- MTMSRD(r5) /* enable use of AltiVec now */
- isync
- cmpwi 0,r3,0
- beqlr- /* if no previous owner, done */
- addi r3,r3,THREAD /* want THREAD of task */
- lwz r5,PT_REGS(r3)
- cmpwi 0,r5,0
- SAVE_32VR(0, r4, r3)
- mfvscr vr0
- li r4,THREAD_VSCR
- stvx vr0,r4,r3
- beq 1f
- lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
- lis r3,MSR_VEC@h
- andc r4,r4,r3 /* disable AltiVec for previous task */
- stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
- li r5,0
- lis r4,last_task_used_altivec@ha
- stw r5,last_task_used_altivec@l(r4)
-#endif /* CONFIG_SMP */
- blr
-#endif /* CONFIG_ALTIVEC */
-
-/*
- * giveup_fpu(tsk)
- * Disable FP for the task given as the argument,
- * and save the floating-point registers in its thread_struct.
- * Enables the FPU for use in the kernel on return.
- */
- .globl giveup_fpu
-giveup_fpu:
- mfmsr r5
- ori r5,r5,MSR_FP
- SYNC_601
- ISYNC_601
- MTMSRD(r5) /* enable use of fpu now */
- SYNC_601
- isync
- cmpwi 0,r3,0
- beqlr- /* if no previous owner, done */
- addi r3,r3,THREAD /* want THREAD of task */
- lwz r5,PT_REGS(r3)
- cmpwi 0,r5,0
- SAVE_32FPRS(0, r3)
- mffs fr0
- stfd fr0,THREAD_FPSCR-4(r3)
- beq 1f
- lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
- li r3,MSR_FP|MSR_FE0|MSR_FE1
- andc r4,r4,r3 /* disable FP for previous task */
- stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
- li r5,0
- lis r4,last_task_used_math@ha
- stw r5,last_task_used_math@l(r4)
-#endif /* CONFIG_SMP */
- blr
-
-/*
* This code is jumped to from the startup code to copy
* the kernel image to physical address 0.
*/
--- linux-orig/arch/ppc/kernel/head_44x.S
+++ linux/arch/ppc/kernel/head_44x.S
@@ -426,7 +426,15 @@
PROGRAM_EXCEPTION
/* Floating Point Unavailable Interrupt */
+#ifdef CONFIG_PPC_FPU
+ START_EXCEPTION(FloatingPointUnavailable)
+ NORMAL_EXCEPTION_PROLOG
+ bne load_up_fpu /* if from user, just load it up */
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ EXC_XFER_EE_LITE(0x800, KernelFP)
+#else
EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
+#endif
/* System Call Interrupt */
START_EXCEPTION(SystemCall)
@@ -686,9 +694,11 @@
*
* The 44x core does not have an FPU.
*/
+#ifndef CONFIG_PPC_FPU
_GLOBAL(giveup_fpu)
blr
-
+#endif
+
/*
* extern void abort(void)
*
--- linux-orig/arch/ppc/kernel/traps.c
+++ linux/arch/ppc/kernel/traps.c
@@ -176,7 +176,7 @@
#else
#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
#endif
-#define REASON_FP 0
+#define REASON_FP ESR_FP
#define REASON_ILLEGAL ESR_PIL
#define REASON_PRIVILEGED ESR_PPR
#define REASON_TRAP ESR_PTR
--- linux-orig/arch/ppc/kernel/vector.S
+++ linux/arch/ppc/kernel/vector.S
@@ -1,3 +1,6 @@
+/* Altivec support code.
+ */
+
#include <asm/ppc_asm.h>
#include <asm/processor.h>
@@ -215,3 +218,116 @@
mtlr r0
addi r1,r1,32
blr
+
+/* Note that the AltiVec support is closely modeled after the FP
+ * support. Changes to one are likely to be applicable to the
+ * other! */
+ .global load_up_altivec
+load_up_altivec:
+/*
+ * Disable AltiVec for the task which had AltiVec previously,
+ * and save its AltiVec registers in its thread_struct.
+ * Enables AltiVec for use in the kernel on return.
+ * On SMP we know the AltiVec units are free, since we give it up every
+ * switch. -- Kumar
+ */
+ mfmsr r5
+ oris r5,r5,MSR_VEC@h
+ MTMSRD(r5) /* enable use of AltiVec now */
+ isync
+/*
+ * For SMP, we don't do lazy AltiVec switching because it just gets too
+ * horrendously complex, especially when a task switches from one CPU
+ * to another. Instead we call giveup_altivec in switch_to.
+ */
+#ifndef CONFIG_SMP
+ tophys(r6,0)
+ addis r3,r6,last_task_used_altivec@ha
+ lwz r4,last_task_used_altivec@l(r3)
+ cmpwi 0,r4,0
+ beq 1f
+ add r4,r4,r6
+ addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
+ SAVE_32VR(0,r10,r4)
+ mfvscr vr0
+ li r10,THREAD_VSCR
+ stvx vr0,r10,r4
+ lwz r5,PT_REGS(r4)
+ add r5,r5,r6
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ lis r10,MSR_VEC@h
+ andc r4,r4,r10 /* disable altivec for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#endif /* CONFIG_SMP */
+ /* enable use of AltiVec after return */
+ oris r9,r9,MSR_VEC@h
+ mfspr r5,SPRG3 /* current task's THREAD (phys) */
+ li r4,1
+ li r10,THREAD_VSCR
+ stw r4,THREAD_USED_VR(r5)
+ lvx vr0,r10,r5
+ mtvscr vr0
+ REST_32VR(0,r10,r5)
+#ifndef CONFIG_SMP
+ subi r4,r5,THREAD
+ sub r4,r4,r6
+ stw r4,last_task_used_altivec@l(r3)
+#endif /* CONFIG_SMP */
+ /* restore registers and return */
+ /* we haven't used ctr or xer or lr */
+ b fast_exception_return
+
+/*
+ * AltiVec unavailable trap from kernel - print a message, but let
+ * the task use AltiVec in the kernel until it returns to user mode.
+ */
+ .global KernelAltiVec
+KernelAltiVec:
+ lwz r3,_MSR(r1)
+ oris r3,r3,MSR_VEC@h
+ stw r3,_MSR(r1) /* enable use of AltiVec after return */
+ lis r3,87f@h
+ ori r3,r3,87f@l
+ mr r4,r2 /* current */
+ lwz r5,_NIP(r1)
+ bl printk
+ b ret_from_except
+87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
+ .align 4,0
+
+/*
+ * giveup_altivec(tsk)
+ * Disable AltiVec for the task given as the argument,
+ * and save the AltiVec registers in its thread_struct.
+ * Enables AltiVec for use in the kernel on return.
+ */
+
+ .global giveup_altivec
+giveup_altivec:
+ mfmsr r5
+ oris r5,r5,MSR_VEC@h
+ SYNC
+ MTMSRD(r5) /* enable use of AltiVec now */
+ isync
+ cmpwi 0,r3,0
+ beqlr- /* if no previous owner, done */
+ addi r3,r3,THREAD /* want THREAD of task */
+ lwz r5,PT_REGS(r3)
+ cmpwi 0,r5,0
+ SAVE_32VR(0, r4, r3)
+ mfvscr vr0
+ li r4,THREAD_VSCR
+ stvx vr0,r4,r3
+ beq 1f
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ lis r3,MSR_VEC@h
+ andc r4,r4,r3 /* disable AltiVec for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#ifndef CONFIG_SMP
+ li r5,0
+ lis r4,last_task_used_altivec@ha
+ stw r5,last_task_used_altivec@l(r4)
+#endif /* CONFIG_SMP */
+ blr
--- linux-orig/include/asm-ppc/reg_booke.h
+++ linux/include/asm-ppc/reg_booke.h
@@ -305,6 +305,7 @@
#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
#define ESR_PTR 0x02000000 /* Program Exception - Trap */
+#define ESR_FP 0x01000000 /* Floating Point Operation */
#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
#define ESR_ST 0x00800000 /* Store Operation */
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
2005-03-15 17:17 [PATCH 1/3] PPC440EP SoC and Bamboo board support Wade Farnsworth
` (2 preceding siblings ...)
2005-03-15 19:31 ` 440EP FPU patch McMullan, Jason
@ 2005-03-16 1:43 ` Josh Boyer
2005-03-16 16:09 ` Wade Farnsworth
3 siblings, 1 reply; 35+ messages in thread
From: Josh Boyer @ 2005-03-16 1:43 UTC (permalink / raw)
To: Wade Farnsworth; +Cc: linuxppc-embedded
On Tue, 2005-03-15 at 10:17 -0700, Wade Farnsworth wrote:
> Hello all,
>
> This adds support for the IBM/AMCC PPC440EP SoC and the Bamboo reference
> board. Any comments would be appreciated.
Isn't the NAND chip on that board a 64MiB chip? If so, the
BAMBOO_NAND_FLASH_SIZE define is wrong. It should be 0x4000000.
Also, are there any plans to add MTD support for the NAND controller
found on those boards?
thx,
josh
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-15 22:18 ` Jason McMullan
@ 2005-03-16 7:22 ` Kumar Gala
2005-03-16 22:14 ` Tom Rini
0 siblings, 1 reply; 35+ messages in thread
From: Kumar Gala @ 2005-03-16 7:22 UTC (permalink / raw)
To: Jason McMullan; +Cc: linuxppc-embedded
Jason,
Is it possible to make this against a newer tree (like a current bk
pull). The patch doesn't apply cleanly against head.S, which I'm
guessing is due to the SPRN changes pushed upstream recently.
If I can apply it cleanly, I will get it pushed upstream.
- kumar
On Mar 15, 2005, at 4:18 PM, Jason McMullan wrote:
> On Tue, 2005-03-15 at 15:09 -0600, Kumar Gala wrote:
>> 1. Change config option to CONFIG_PPC_FPU
>> 2. split out altivec support into a separate file, most likely just
>> move it into vector.S
>> 3. Get ride of the C++ comments
>
> Changes made, as per your suggestions, and new patch attached.
>
> --
> Jason McMullan <jason.mcmullan@timesys.com>
> TimeSys Corporation
>
> <cpu-ppc-fpu.patch>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
2005-03-16 1:43 ` [PATCH 1/3] PPC440EP SoC and Bamboo board support Josh Boyer
@ 2005-03-16 16:09 ` Wade Farnsworth
2005-03-16 17:26 ` Jason McMullan
0 siblings, 1 reply; 35+ messages in thread
From: Wade Farnsworth @ 2005-03-16 16:09 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-embedded
On Tue, 2005-03-15 at 18:43, Josh Boyer wrote:
> On Tue, 2005-03-15 at 10:17 -0700, Wade Farnsworth wrote:
> > Hello all,
> >
> > This adds support for the IBM/AMCC PPC440EP SoC and the Bamboo reference
> > board. Any comments would be appreciated.
>
> Isn't the NAND chip on that board a 64MiB chip? If so, the
> BAMBOO_NAND_FLASH_SIZE define is wrong. It should be 0x4000000.
>
> Also, are there any plans to add MTD support for the NAND controller
> found on those boards?
>
> thx,
> josh
Yes, you're right. I'll fix that.
I'm working on MTD support, including support for the NAND controller.
Thanks,
Wade Farnsworth
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
2005-03-16 16:09 ` Wade Farnsworth
@ 2005-03-16 17:26 ` Jason McMullan
2005-03-16 18:04 ` Wade Farnsworth
0 siblings, 1 reply; 35+ messages in thread
From: Jason McMullan @ 2005-03-16 17:26 UTC (permalink / raw)
To: Wade Farnsworth; +Cc: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 215 bytes --]
Do you need a 'special' toolchain to work around Errata 42 (isync before
blrl) for user-space, or are the kernel-land fixes sufficient?
--
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 1/3] PPC440EP SoC and Bamboo board support
2005-03-16 17:26 ` Jason McMullan
@ 2005-03-16 18:04 ` Wade Farnsworth
0 siblings, 0 replies; 35+ messages in thread
From: Wade Farnsworth @ 2005-03-16 18:04 UTC (permalink / raw)
To: Jason McMullan; +Cc: linuxppc-embedded
On Wed, 2005-03-16 at 10:26, Jason McMullan wrote:
> Do you need a 'special' toolchain to work around Errata 42 (isync before
> blrl) for user-space, or are the kernel-land fixes sufficient?
Yes, this work around also needs to be in gcc. I know this has been
fixed in MontaVista's toolchain, but I don't know if the work around has
been pushed up to the main gcc tree.
-Wade Farnsworth
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-16 7:22 ` Kumar Gala
@ 2005-03-16 22:14 ` Tom Rini
2005-03-16 22:52 ` Kumar Gala
0 siblings, 1 reply; 35+ messages in thread
From: Tom Rini @ 2005-03-16 22:14 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-embedded
On Wed, Mar 16, 2005 at 01:22:48AM -0600, Kumar Gala wrote:
> Jason,
>
> Is it possible to make this against a newer tree (like a current bk
> pull). The patch doesn't apply cleanly against head.S, which I'm
> guessing is due to the SPRN changes pushed upstream recently.
>
> If I can apply it cleanly, I will get it pushed upstream.
Can one of you run say LTP on a classic box, just as a sanity test
before pushing? If not, lemme know and I'll do it :)
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-16 22:14 ` Tom Rini
@ 2005-03-16 22:52 ` Kumar Gala
2005-03-16 23:18 ` Tom Rini
0 siblings, 1 reply; 35+ messages in thread
From: Kumar Gala @ 2005-03-16 22:52 UTC (permalink / raw)
To: Tom Rini; +Cc: linuxppc-embedded
I dont have either of these readily available at this point.
If you dont mind running it through when you get a chance. However, is=20=
this going to test anything but FP?
- kumar
On Mar 16, 2005, at 4:14 PM, Tom Rini wrote:
> On Wed, Mar 16, 2005 at 01:22:48AM -0600, Kumar Gala wrote:
>
> > Jason,
> >
> > Is it possible to make this against a newer tree (like a current bk
> > pull).=A0 The patch doesn't apply cleanly against head.S, which I'm
> > guessing is due to the SPRN changes pushed upstream recently.
> >
> > If I can apply it cleanly, I will get it pushed upstream.
>
> Can one of you run say LTP on a classic box, just as a sanity test
> before pushing?=A0 If not, lemme know and I'll do it :)
>
> --=20
> Tom Rini
> http://gate.crashing.org/~trini/
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-16 22:52 ` Kumar Gala
@ 2005-03-16 23:18 ` Tom Rini
2005-03-18 16:06 ` Kumar Gala
0 siblings, 1 reply; 35+ messages in thread
From: Tom Rini @ 2005-03-16 23:18 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-embedded
On Wed, Mar 16, 2005 at 04:52:00PM -0600, Kumar Gala wrote:
> I dont have either of these readily available at this point.
>
> If you dont mind running it through when you get a chance. However, is
> this going to test anything but FP?
It's more of a funkiness test, just in case.
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-16 23:18 ` Tom Rini
@ 2005-03-18 16:06 ` Kumar Gala
2005-03-18 18:43 ` Jason McMullan
0 siblings, 1 reply; 35+ messages in thread
From: Kumar Gala @ 2005-03-18 16:06 UTC (permalink / raw)
To: Jason McMullan; +Cc: Tom Rini, linuxppc-embedded Linux list
Jason,
Can you build your patch for the lopec_defconfig and fix the errors=20
associated with enabling altivec.
Looks like you need to include asm/offset.h & asm/page.h in vector.S,=20
however there is another build error after that.
Resend, with a fix.
thanks
- kumar
On Mar 16, 2005, at 5:18 PM, Tom Rini wrote:
> On Wed, Mar 16, 2005 at 04:52:00PM -0600, Kumar Gala wrote:
>
> > I dont have either of these readily available at this point.
> >
> > If you dont mind running it through when you get a chance.=A0 =
However,=20
> is
> > this going to test anything but FP?
>
> It's more of a funkiness test, just in case.
>
> --=20
> Tom Rini
> http://gate.crashing.org/~trini/
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-18 16:06 ` Kumar Gala
@ 2005-03-18 18:43 ` Jason McMullan
2005-03-18 19:30 ` Tom Rini
0 siblings, 1 reply; 35+ messages in thread
From: Jason McMullan @ 2005-03-18 18:43 UTC (permalink / raw)
To: Kumar Gala; +Cc: Tom Rini, linuxppc-embedded Linux list
[-- Attachment #1.1: Type: text/plain, Size: 598 bytes --]
On Fri, 2005-03-18 at 10:06 -0600, Kumar Gala wrote:
> Can you build your patch for the lopec_defconfig and fix the errors
> associated with enabling altivec.
>
> Looks like you need to include asm/offset.h & asm/page.h in vector.S,
> however there is another build error after that.
Thanks! That also found a linking bug, fixed in this patch.. Please
double check the call in 'AltiVecUnavalible' in head.S, and the re-load
of 'ctr' at the end of load_up_altivec, as I do not have an AltiVec
machine here.
--
Jason McMullan <jason.mcmullan@timesys.com>
TimeSys Corporation
[-- Attachment #1.2: cpu-ppc-fpu.patch --]
[-- Type: text/x-patch, Size: 21743 bytes --]
Maintainer: Jason McMullan <jason.mcmullan@timesys.com>
Date: Fri Mar 18 13:42:19 EST 2005
Summary: Split FPU and AlitVec support off of head*.S
Signed-Off-By: Jason McMullan <jason.mcmullan@timesys.com>
diff -urN -X /home/jmcmullan/dontdiff linux-2.6/arch/ppc/Kconfig linux-2.6-cpu-fpu/arch/ppc/Kconfig
--- linux-2.6/arch/ppc/Kconfig 2005-03-18 09:10:07.689764097 -0500
+++ linux-2.6-cpu-fpu/arch/ppc/Kconfig 2005-03-18 11:29:59.420731605 -0500
@@ -53,6 +53,7 @@
config 6xx
bool "6xx/7xx/74xx/52xx/82xx/83xx"
+ select PPC_FPU
help
There are four types of PowerPC chips supported. The more common
types (601, 603, 604, 740, 750, 7400), the Motorola embedded
@@ -83,9 +84,12 @@
config E500
bool "e500"
-
+
endchoice
+config PPC_FPU
+ bool
+
config BOOKE
bool
depends on E500
diff -urN -X /home/jmcmullan/dontdiff linux-2.6/arch/ppc/kernel/fpu.S linux-2.6-cpu-fpu/arch/ppc/kernel/fpu.S
--- linux-2.6/arch/ppc/kernel/fpu.S 1969-12-31 19:00:00.000000000 -0500
+++ linux-2.6-cpu-fpu/arch/ppc/kernel/fpu.S 2005-03-18 11:29:59.426730234 -0500
@@ -0,0 +1,183 @@
+/* FPU support code, moved here from head.S so that it can be used
+ * by chips which use other head-whatever.S files.
+ */
+
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <asm/mmu.h>
+#include <asm/pgtable.h>
+#include <asm/cputable.h>
+#include <asm/cache.h>
+#include <asm/thread_info.h>
+#include <asm/ppc_asm.h>
+#include <asm/offsets.h>
+
+/*
+ * This task wants to use the FPU now.
+ * On UP, disable FP for the task which had the FPU previously,
+ * and save its floating-point registers in its thread_struct.
+ * Load up this task's FP registers from its thread_struct,
+ * enable the FPU for the current task and return to the task.
+ */
+ .global load_up_fpu
+load_up_fpu:
+ mfmsr r5
+ ori r5,r5,MSR_FP
+#ifdef CONFIG_PPC64BRIDGE
+ clrldi r5,r5,1 /* turn off 64-bit mode */
+#endif /* CONFIG_PPC64BRIDGE */
+ SYNC
+ MTMSRD(r5) /* enable use of fpu now */
+ isync
+/*
+ * For SMP, we don't do lazy FPU switching because it just gets too
+ * horrendously complex, especially when a task switches from one CPU
+ * to another. Instead we call giveup_fpu in switch_to.
+ */
+#ifndef CONFIG_SMP
+ tophys(r6,0) /* get __pa constant */
+ addis r3,r6,last_task_used_math@ha
+ lwz r4,last_task_used_math@l(r3)
+ cmpwi 0,r4,0
+ beq 1f
+ add r4,r4,r6
+ addi r4,r4,THREAD /* want last_task_used_math->thread */
+ SAVE_32FPRS(0, r4)
+ mffs fr0
+ stfd fr0,THREAD_FPSCR-4(r4)
+ lwz r5,PT_REGS(r4)
+ add r5,r5,r6
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ li r10,MSR_FP|MSR_FE0|MSR_FE1
+ andc r4,r4,r10 /* disable FP for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#endif /* CONFIG_SMP */
+ /* enable use of FP after return */
+ mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
+ lwz r4,THREAD_FPEXC_MODE(r5)
+ ori r9,r9,MSR_FP /* enable FP for current */
+ or r9,r9,r4
+ lfd fr0,THREAD_FPSCR-4(r5)
+ mtfsf 0xff,fr0
+ REST_32FPRS(0, r5)
+#ifndef CONFIG_SMP
+ subi r4,r5,THREAD
+ sub r4,r4,r6
+ stw r4,last_task_used_math@l(r3)
+#endif /* CONFIG_SMP */
+ /* restore registers and return */
+ /* we haven't used ctr or xer or lr */
+ /* fall through to fast_exception_return */
+
+ .global fast_exception_return
+fast_exception_return:
+#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
+ andi. r10,r9,MSR_RI /* check for recoverable interrupt */
+ beq 1f /* if not, we've got problems */
+#endif
+
+2: REST_4GPRS(3, r11)
+ lwz r10,_CCR(r11)
+ REST_GPR(1, r11)
+ mtcr r10
+ lwz r10,_LINK(r11)
+ mtlr r10
+ REST_GPR(10, r11)
+ mtspr SPRN_SRR1,r9
+ mtspr SPRN_SRR0,r12
+ REST_GPR(9, r11)
+ REST_GPR(12, r11)
+ lwz r11,GPR11(r11)
+ SYNC
+ RFI
+
+/* check if the exception happened in a restartable section */
+1: lis r3,exc_exit_restart_end@ha
+ addi r3,r3,exc_exit_restart_end@l
+ cmplw r12,r3
+ bge 3f
+ lis r4,exc_exit_restart@ha
+ addi r4,r4,exc_exit_restart@l
+ cmplw r12,r4
+ blt 3f
+ lis r3,fee_restarts@ha
+ tophys(r3,r3)
+ lwz r5,fee_restarts@l(r3)
+ addi r5,r5,1
+ stw r5,fee_restarts@l(r3)
+ mr r12,r4 /* restart at exc_exit_restart */
+ b 2b
+
+ .comm fee_restarts,4
+
+/* aargh, a nonrecoverable interrupt, panic */
+/* aargh, we don't know which trap this is */
+/* but the 601 doesn't implement the RI bit, so assume it's OK */
+3:
+BEGIN_FTR_SECTION
+ b 2b
+END_FTR_SECTION_IFSET(CPU_FTR_601)
+ li r10,-1
+ stw r10,TRAP(r11)
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ lis r10, MSR_KERNEL@h
+ ori r10, r10, MSR_KERNEL@l
+ bl transfer_to_handler_full
+ .long nonrecoverable_exception
+ .long ret_from_except
+
+/*
+ * FP unavailable trap from kernel - print a message, but let
+ * the task use FP in the kernel until it returns to user mode.
+ */
+ .global KernelFP
+KernelFP:
+ lwz r3,_MSR(r1)
+ ori r3,r3,MSR_FP
+ stw r3,_MSR(r1) /* enable use of FP after return */
+ lis r3,86f@h
+ ori r3,r3,86f@l
+ mr r4,r2 /* current */
+ lwz r5,_NIP(r1)
+ bl printk
+ b ret_from_except
+86: .string "floating point used in kernel (task=%p, pc=%x)\n"
+ .align 4,0
+
+/*
+ * giveup_fpu(tsk)
+ * Disable FP for the task given as the argument,
+ * and save the floating-point registers in its thread_struct.
+ * Enables the FPU for use in the kernel on return.
+ */
+ .global giveup_fpu
+giveup_fpu:
+ mfmsr r5
+ ori r5,r5,MSR_FP
+ SYNC_601
+ ISYNC_601
+ MTMSRD(r5) /* enable use of fpu now */
+ SYNC_601
+ isync
+ cmpwi 0,r3,0
+ beqlr- /* if no previous owner, done */
+ addi r3,r3,THREAD /* want THREAD of task */
+ lwz r5,PT_REGS(r3)
+ cmpwi 0,r5,0
+ SAVE_32FPRS(0, r3)
+ mffs fr0
+ stfd fr0,THREAD_FPSCR-4(r3)
+ beq 1f
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ li r3,MSR_FP|MSR_FE0|MSR_FE1
+ andc r4,r4,r3 /* disable FP for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#ifndef CONFIG_SMP
+ li r5,0
+ lis r4,last_task_used_math@ha
+ stw r5,last_task_used_math@l(r4)
+#endif /* CONFIG_SMP */
+ blr
diff -urN -X /home/jmcmullan/dontdiff linux-2.6/arch/ppc/kernel/head_44x.S linux-2.6-cpu-fpu/arch/ppc/kernel/head_44x.S
--- linux-2.6/arch/ppc/kernel/head_44x.S 2005-03-18 09:10:09.548338544 -0500
+++ linux-2.6-cpu-fpu/arch/ppc/kernel/head_44x.S 2005-03-18 11:29:59.456723379 -0500
@@ -426,7 +426,15 @@
PROGRAM_EXCEPTION
/* Floating Point Unavailable Interrupt */
+#ifdef CONFIG_PPC_FPU
+ START_EXCEPTION(FloatingPointUnavailable)
+ NORMAL_EXCEPTION_PROLOG
+ bne load_up_fpu /* if from user, just load it up */
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ EXC_XFER_EE_LITE(0x800, KernelFP)
+#else
EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
+#endif
/* System Call Interrupt */
START_EXCEPTION(SystemCall)
@@ -686,9 +694,11 @@
*
* The 44x core does not have an FPU.
*/
+#ifndef CONFIG_PPC_FPU
_GLOBAL(giveup_fpu)
blr
-
+#endif
+
/*
* extern void abort(void)
*
diff -urN -X /home/jmcmullan/dontdiff linux-2.6/arch/ppc/kernel/head.S linux-2.6-cpu-fpu/arch/ppc/kernel/head.S
--- linux-2.6/arch/ppc/kernel/head.S 2005-03-18 09:10:10.164197532 -0500
+++ linux-2.6-cpu-fpu/arch/ppc/kernel/head.S 2005-03-18 13:36:05.834947939 -0500
@@ -749,7 +749,12 @@
AltiVecUnavailable:
EXCEPTION_PROLOG
#ifdef CONFIG_ALTIVEC
- bne load_up_altivec /* if from user, just load it up */
+ mflr r4 /* Save CTR, and use CTR to branch */
+ stw r4, _CTR(r11) /* since load_up_altivec may be */
+ lis r4, load_up_altivec@h /* far away. */
+ ori r4, r4, load_up_altivec@l
+ mtctr r4
+ bctr /* if from user, just load it up */
#endif /* CONFIG_ALTIVEC */
EXC_XFER_EE_LITE(0xf20, AltivecUnavailException)
@@ -776,282 +781,6 @@
#endif /* CONFIG_PPC64BRIDGE */
/*
- * This task wants to use the FPU now.
- * On UP, disable FP for the task which had the FPU previously,
- * and save its floating-point registers in its thread_struct.
- * Load up this task's FP registers from its thread_struct,
- * enable the FPU for the current task and return to the task.
- */
-load_up_fpu:
- mfmsr r5
- ori r5,r5,MSR_FP
-#ifdef CONFIG_PPC64BRIDGE
- clrldi r5,r5,1 /* turn off 64-bit mode */
-#endif /* CONFIG_PPC64BRIDGE */
- SYNC
- MTMSRD(r5) /* enable use of fpu now */
- isync
-/*
- * For SMP, we don't do lazy FPU switching because it just gets too
- * horrendously complex, especially when a task switches from one CPU
- * to another. Instead we call giveup_fpu in switch_to.
- */
-#ifndef CONFIG_SMP
- tophys(r6,0) /* get __pa constant */
- addis r3,r6,last_task_used_math@ha
- lwz r4,last_task_used_math@l(r3)
- cmpwi 0,r4,0
- beq 1f
- add r4,r4,r6
- addi r4,r4,THREAD /* want last_task_used_math->thread */
- SAVE_32FPRS(0, r4)
- mffs fr0
- stfd fr0,THREAD_FPSCR-4(r4)
- lwz r5,PT_REGS(r4)
- add r5,r5,r6
- lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
- li r10,MSR_FP|MSR_FE0|MSR_FE1
- andc r4,r4,r10 /* disable FP for previous task */
- stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
- /* enable use of FP after return */
- mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
- lwz r4,THREAD_FPEXC_MODE(r5)
- ori r9,r9,MSR_FP /* enable FP for current */
- or r9,r9,r4
- lfd fr0,THREAD_FPSCR-4(r5)
- mtfsf 0xff,fr0
- REST_32FPRS(0, r5)
-#ifndef CONFIG_SMP
- subi r4,r5,THREAD
- sub r4,r4,r6
- stw r4,last_task_used_math@l(r3)
-#endif /* CONFIG_SMP */
- /* restore registers and return */
- /* we haven't used ctr or xer or lr */
- /* fall through to fast_exception_return */
-
- .globl fast_exception_return
-fast_exception_return:
- andi. r10,r9,MSR_RI /* check for recoverable interrupt */
- beq 1f /* if not, we've got problems */
-2: REST_4GPRS(3, r11)
- lwz r10,_CCR(r11)
- REST_GPR(1, r11)
- mtcr r10
- lwz r10,_LINK(r11)
- mtlr r10
- REST_GPR(10, r11)
- mtspr SPRN_SRR1,r9
- mtspr SPRN_SRR0,r12
- REST_GPR(9, r11)
- REST_GPR(12, r11)
- lwz r11,GPR11(r11)
- SYNC
- RFI
-
-/* check if the exception happened in a restartable section */
-1: lis r3,exc_exit_restart_end@ha
- addi r3,r3,exc_exit_restart_end@l
- cmplw r12,r3
- bge 3f
- lis r4,exc_exit_restart@ha
- addi r4,r4,exc_exit_restart@l
- cmplw r12,r4
- blt 3f
- lis r3,fee_restarts@ha
- tophys(r3,r3)
- lwz r5,fee_restarts@l(r3)
- addi r5,r5,1
- stw r5,fee_restarts@l(r3)
- mr r12,r4 /* restart at exc_exit_restart */
- b 2b
-
- .comm fee_restarts,4
-
-/* aargh, a nonrecoverable interrupt, panic */
-/* aargh, we don't know which trap this is */
-/* but the 601 doesn't implement the RI bit, so assume it's OK */
-3:
-BEGIN_FTR_SECTION
- b 2b
-END_FTR_SECTION_IFSET(CPU_FTR_601)
- li r10,-1
- stw r10,TRAP(r11)
- addi r3,r1,STACK_FRAME_OVERHEAD
- li r10,MSR_KERNEL
- bl transfer_to_handler_full
- .long nonrecoverable_exception
- .long ret_from_except
-
-/*
- * FP unavailable trap from kernel - print a message, but let
- * the task use FP in the kernel until it returns to user mode.
- */
-KernelFP:
- lwz r3,_MSR(r1)
- ori r3,r3,MSR_FP
- stw r3,_MSR(r1) /* enable use of FP after return */
- lis r3,86f@h
- ori r3,r3,86f@l
- mr r4,r2 /* current */
- lwz r5,_NIP(r1)
- bl printk
- b ret_from_except
-86: .string "floating point used in kernel (task=%p, pc=%x)\n"
- .align 4,0
-
-#ifdef CONFIG_ALTIVEC
-/* Note that the AltiVec support is closely modeled after the FP
- * support. Changes to one are likely to be applicable to the
- * other! */
-load_up_altivec:
-/*
- * Disable AltiVec for the task which had AltiVec previously,
- * and save its AltiVec registers in its thread_struct.
- * Enables AltiVec for use in the kernel on return.
- * On SMP we know the AltiVec units are free, since we give it up every
- * switch. -- Kumar
- */
- mfmsr r5
- oris r5,r5,MSR_VEC@h
- MTMSRD(r5) /* enable use of AltiVec now */
- isync
-/*
- * For SMP, we don't do lazy AltiVec switching because it just gets too
- * horrendously complex, especially when a task switches from one CPU
- * to another. Instead we call giveup_altivec in switch_to.
- */
-#ifndef CONFIG_SMP
- tophys(r6,0)
- addis r3,r6,last_task_used_altivec@ha
- lwz r4,last_task_used_altivec@l(r3)
- cmpwi 0,r4,0
- beq 1f
- add r4,r4,r6
- addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
- SAVE_32VR(0,r10,r4)
- mfvscr vr0
- li r10,THREAD_VSCR
- stvx vr0,r10,r4
- lwz r5,PT_REGS(r4)
- add r5,r5,r6
- lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
- lis r10,MSR_VEC@h
- andc r4,r4,r10 /* disable altivec for previous task */
- stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#endif /* CONFIG_SMP */
- /* enable use of AltiVec after return */
- oris r9,r9,MSR_VEC@h
- mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
- li r4,1
- li r10,THREAD_VSCR
- stw r4,THREAD_USED_VR(r5)
- lvx vr0,r10,r5
- mtvscr vr0
- REST_32VR(0,r10,r5)
-#ifndef CONFIG_SMP
- subi r4,r5,THREAD
- sub r4,r4,r6
- stw r4,last_task_used_altivec@l(r3)
-#endif /* CONFIG_SMP */
- /* restore registers and return */
- /* we haven't used ctr or xer or lr */
- b fast_exception_return
-
-/*
- * AltiVec unavailable trap from kernel - print a message, but let
- * the task use AltiVec in the kernel until it returns to user mode.
- */
-KernelAltiVec:
- lwz r3,_MSR(r1)
- oris r3,r3,MSR_VEC@h
- stw r3,_MSR(r1) /* enable use of AltiVec after return */
- lis r3,87f@h
- ori r3,r3,87f@l
- mr r4,r2 /* current */
- lwz r5,_NIP(r1)
- bl printk
- b ret_from_except
-87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
- .align 4,0
-
-/*
- * giveup_altivec(tsk)
- * Disable AltiVec for the task given as the argument,
- * and save the AltiVec registers in its thread_struct.
- * Enables AltiVec for use in the kernel on return.
- */
-
- .globl giveup_altivec
-giveup_altivec:
- mfmsr r5
- oris r5,r5,MSR_VEC@h
- SYNC
- MTMSRD(r5) /* enable use of AltiVec now */
- isync
- cmpwi 0,r3,0
- beqlr- /* if no previous owner, done */
- addi r3,r3,THREAD /* want THREAD of task */
- lwz r5,PT_REGS(r3)
- cmpwi 0,r5,0
- SAVE_32VR(0, r4, r3)
- mfvscr vr0
- li r4,THREAD_VSCR
- stvx vr0,r4,r3
- beq 1f
- lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
- lis r3,MSR_VEC@h
- andc r4,r4,r3 /* disable AltiVec for previous task */
- stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
- li r5,0
- lis r4,last_task_used_altivec@ha
- stw r5,last_task_used_altivec@l(r4)
-#endif /* CONFIG_SMP */
- blr
-#endif /* CONFIG_ALTIVEC */
-
-/*
- * giveup_fpu(tsk)
- * Disable FP for the task given as the argument,
- * and save the floating-point registers in its thread_struct.
- * Enables the FPU for use in the kernel on return.
- */
- .globl giveup_fpu
-giveup_fpu:
- mfmsr r5
- ori r5,r5,MSR_FP
- SYNC_601
- ISYNC_601
- MTMSRD(r5) /* enable use of fpu now */
- SYNC_601
- isync
- cmpwi 0,r3,0
- beqlr- /* if no previous owner, done */
- addi r3,r3,THREAD /* want THREAD of task */
- lwz r5,PT_REGS(r3)
- cmpwi 0,r5,0
- SAVE_32FPRS(0, r3)
- mffs fr0
- stfd fr0,THREAD_FPSCR-4(r3)
- beq 1f
- lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
- li r3,MSR_FP|MSR_FE0|MSR_FE1
- andc r4,r4,r3 /* disable FP for previous task */
- stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
-1:
-#ifndef CONFIG_SMP
- li r5,0
- lis r4,last_task_used_math@ha
- stw r5,last_task_used_math@l(r4)
-#endif /* CONFIG_SMP */
- blr
-
-/*
* This code is jumped to from the startup code to copy
* the kernel image to physical address 0.
*/
diff -urN -X /home/jmcmullan/dontdiff linux-2.6/arch/ppc/kernel/Makefile linux-2.6-cpu-fpu/arch/ppc/kernel/Makefile
--- linux-2.6/arch/ppc/kernel/Makefile 2005-03-18 09:10:11.397915051 -0500
+++ linux-2.6-cpu-fpu/arch/ppc/kernel/Makefile 2005-03-18 11:29:59.486716524 -0500
@@ -9,6 +9,7 @@
extra-$(CONFIG_8xx) := head_8xx.o
extra-$(CONFIG_6xx) += idle_6xx.o
extra-$(CONFIG_POWER4) += idle_power4.o
+extra-$(CONFIG_PPC_FPU) += fpu.o
extra-y += vmlinux.lds
obj-y := entry.o traps.o irq.o idle.o time.o misc.o \
diff -urN -X /home/jmcmullan/dontdiff linux-2.6/arch/ppc/kernel/traps.c linux-2.6-cpu-fpu/arch/ppc/kernel/traps.c
--- linux-2.6/arch/ppc/kernel/traps.c 2005-03-18 09:10:13.936333835 -0500
+++ linux-2.6-cpu-fpu/arch/ppc/kernel/traps.c 2005-03-18 11:29:59.507711725 -0500
@@ -176,7 +176,7 @@
#else
#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
#endif
-#define REASON_FP 0
+#define REASON_FP ESR_FP
#define REASON_ILLEGAL ESR_PIL
#define REASON_PRIVILEGED ESR_PPR
#define REASON_TRAP ESR_PTR
diff -urN -X /home/jmcmullan/dontdiff linux-2.6/arch/ppc/kernel/vector.S linux-2.6-cpu-fpu/arch/ppc/kernel/vector.S
--- linux-2.6/arch/ppc/kernel/vector.S 2005-03-18 09:10:13.938333378 -0500
+++ linux-2.6-cpu-fpu/arch/ppc/kernel/vector.S 2005-03-18 13:34:34.697801457 -0500
@@ -1,5 +1,10 @@
+/* Altivec support code.
+ */
+
#include <asm/ppc_asm.h>
#include <asm/processor.h>
+#include <asm/offsets.h>
+#include <asm/page.h>
/*
* The routines below are in assembler so we can closely control the
@@ -215,3 +220,118 @@
mtlr r0
addi r1,r1,32
blr
+
+/* Note that the AltiVec support is closely modeled after the FP
+ * support. Changes to one are likely to be applicable to the
+ * other! */
+ .global load_up_altivec
+load_up_altivec:
+/*
+ * Disable AltiVec for the task which had AltiVec previously,
+ * and save its AltiVec registers in its thread_struct.
+ * Enables AltiVec for use in the kernel on return.
+ * On SMP we know the AltiVec units are free, since we give it up every
+ * switch. -- Kumar
+ */
+ mfmsr r5
+ oris r5,r5,MSR_VEC@h
+ MTMSRD(r5) /* enable use of AltiVec now */
+ isync
+/*
+ * For SMP, we don't do lazy AltiVec switching because it just gets too
+ * horrendously complex, especially when a task switches from one CPU
+ * to another. Instead we call giveup_altivec in switch_to.
+ */
+#ifndef CONFIG_SMP
+ tophys(r6,0)
+ addis r3,r6,last_task_used_altivec@ha
+ lwz r4,last_task_used_altivec@l(r3)
+ cmpwi 0,r4,0
+ beq 1f
+ add r4,r4,r6
+ addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
+ SAVE_32VR(0,r10,r4)
+ mfvscr vr0
+ li r10,THREAD_VSCR
+ stvx vr0,r10,r4
+ lwz r5,PT_REGS(r4)
+ add r5,r5,r6
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ lis r10,MSR_VEC@h
+ andc r4,r4,r10 /* disable altivec for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#endif /* CONFIG_SMP */
+ /* enable use of AltiVec after return */
+ oris r9,r9,MSR_VEC@h
+ mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
+ li r4,1
+ li r10,THREAD_VSCR
+ stw r4,THREAD_USED_VR(r5)
+ lvx vr0,r10,r5
+ mtvscr vr0
+ REST_32VR(0,r10,r5)
+#ifndef CONFIG_SMP
+ subi r4,r5,THREAD
+ sub r4,r4,r6
+ stw r4,last_task_used_altivec@l(r3)
+#endif /* CONFIG_SMP */
+ /* restore registers and return */
+ lwz r4, _CTR(r11) /* Restore saved ctr */
+ mtlr r4
+ /* we haven't used ctr or xer or lr */
+ b fast_exception_return
+
+/*
+ * AltiVec unavailable trap from kernel - print a message, but let
+ * the task use AltiVec in the kernel until it returns to user mode.
+ */
+ .global KernelAltiVec
+KernelAltiVec:
+ lwz r3,_MSR(r1)
+ oris r3,r3,MSR_VEC@h
+ stw r3,_MSR(r1) /* enable use of AltiVec after return */
+ lis r3,87f@h
+ ori r3,r3,87f@l
+ mr r4,r2 /* current */
+ lwz r5,_NIP(r1)
+ bl printk
+ b ret_from_except
+87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
+ .align 4,0
+
+/*
+ * giveup_altivec(tsk)
+ * Disable AltiVec for the task given as the argument,
+ * and save the AltiVec registers in its thread_struct.
+ * Enables AltiVec for use in the kernel on return.
+ */
+
+ .global giveup_altivec
+giveup_altivec:
+ mfmsr r5
+ oris r5,r5,MSR_VEC@h
+ SYNC
+ MTMSRD(r5) /* enable use of AltiVec now */
+ isync
+ cmpwi 0,r3,0
+ beqlr- /* if no previous owner, done */
+ addi r3,r3,THREAD /* want THREAD of task */
+ lwz r5,PT_REGS(r3)
+ cmpwi 0,r5,0
+ SAVE_32VR(0, r4, r3)
+ mfvscr vr0
+ li r4,THREAD_VSCR
+ stvx vr0,r4,r3
+ beq 1f
+ lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+ lis r3,MSR_VEC@h
+ andc r4,r4,r3 /* disable AltiVec for previous task */
+ stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
+1:
+#ifndef CONFIG_SMP
+ li r5,0
+ lis r4,last_task_used_altivec@ha
+ stw r5,last_task_used_altivec@l(r4)
+#endif /* CONFIG_SMP */
+ blr
diff -urN -X /home/jmcmullan/dontdiff linux-2.6/arch/ppc/Makefile linux-2.6-cpu-fpu/arch/ppc/Makefile
--- linux-2.6/arch/ppc/Makefile 2005-03-18 09:10:14.737150474 -0500
+++ linux-2.6-cpu-fpu/arch/ppc/Makefile 2005-03-18 11:29:59.524707840 -0500
@@ -53,6 +53,7 @@
head-$(CONFIG_6xx) += arch/ppc/kernel/idle_6xx.o
head-$(CONFIG_POWER4) += arch/ppc/kernel/idle_power4.o
+head-$(CONFIG_PPC_FPU) += arch/ppc/kernel/fpu.o
core-y += arch/ppc/kernel/ arch/ppc/platforms/ \
arch/ppc/mm/ arch/ppc/lib/ arch/ppc/syslib/
diff -urN -X /home/jmcmullan/dontdiff linux-2.6/include/asm-ppc/reg_booke.h linux-2.6-cpu-fpu/include/asm-ppc/reg_booke.h
--- linux-2.6/include/asm-ppc/reg_booke.h 2005-03-18 09:37:41.000000000 -0500
+++ linux-2.6-cpu-fpu/include/asm-ppc/reg_booke.h 2005-03-18 11:29:59.530706469 -0500
@@ -304,6 +304,7 @@
#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
#define ESR_PTR 0x02000000 /* Program Exception - Trap */
+#define ESR_FP 0x01000000 /* Floating Point Operation */
#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
#define ESR_ST 0x00800000 /* Store Operation */
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-18 18:43 ` Jason McMullan
@ 2005-03-18 19:30 ` Tom Rini
2005-03-31 16:26 ` Wade Farnsworth
0 siblings, 1 reply; 35+ messages in thread
From: Tom Rini @ 2005-03-18 19:30 UTC (permalink / raw)
To: Jason McMullan; +Cc: linuxppc-embedded Linux list
On Fri, Mar 18, 2005 at 01:43:11PM -0500, Jason McMullan wrote:
> On Fri, 2005-03-18 at 10:06 -0600, Kumar Gala wrote:
> > Can you build your patch for the lopec_defconfig and fix the errors
> > associated with enabling altivec.
> >
> > Looks like you need to include asm/offset.h & asm/page.h in vector.S,
> > however there is another build error after that.
>
> Thanks! That also found a linking bug, fixed in this patch.. Please
> double check the call in 'AltiVecUnavalible' in head.S, and the re-load
> of 'ctr' at the end of load_up_altivec, as I do not have an AltiVec
> machine here.
No dice:
VFS: Mounted root (nfs filesystem) readonly.
Freeing unused kernel memory: 100k init 4k prep
floating point used in kernel (task=c03816b0, pc=c000d664)
Doing some objdump'ing, that's the start of load_up_altivec.
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH 3/3] PPC440EP IBM EMAC support
2005-03-15 20:37 ` Matt Porter
@ 2005-03-28 17:52 ` Wade Farnsworth
0 siblings, 0 replies; 35+ messages in thread
From: Wade Farnsworth @ 2005-03-28 17:52 UTC (permalink / raw)
To: Matt Porter; +Cc: linuxppc-embedded
On Tue, 2005-03-15 at 13:37, Matt Porter wrote:
> On Tue, Mar 15, 2005 at 11:22:16AM -0800, Eugene Surovegin wrote:
> > On Tue, Mar 15, 2005 at 11:58:54AM -0700, Wade Farnsworth wrote:
> > > This patch adds support to the IBM EMAC ethernet driver for the 440EP.
> > >
> > > Regards,
> > > Wade Farnsworth
> > >
> > > Signed-off-by: Wade Farnsworth <wfarnsworth@mvista.com>
> > >
> >
> > > --- linux-2.6.11-bk7/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-02 00:38:13.000000000 -0700
> > > +++ linux-2.6.11-bk7-440ep/drivers/net/ibm_emac/ibm_emac_phy.c 2005-03-11 16:32:01.000000000 -0700
> > > @@ -27,6 +27,12 @@
> > >
> > > #include "ibm_emac_phy.h"
> > >
> > > +#ifdef CONFIG_BAMBOO
> > > +#define BAMBOO_REV0 (mfspr(PVR) == PVR_440EP_RA)
> > > +#else
> > > +#define BAMBOO_REV0 0
> > > +#endif
> > > +
> >
> > I really don't like it. Chip revision doesn't imply which board
> > this code is running on. Please, think of some other way to do this or
> > drop this completely.
>
> Wade and I talked about this one before and there is no direct way
> to detect the board revision on this platform. Given that, I
> think that if the PVR of the 440EP in a Bamboo board does imply
> the board revision, then this is appropriate.
I emailed AMCC support about the 440EP eval board revision situation and
(finally) got a reply.
It seems there are no plans to replace the Rev 0 boards with Rev 1
boards. It is, therefore, conceivable that some users will have Rev 0
boards, and will need the workaround in the patch. Others will have Rev
1 boards, which work fine with the current version of the driver.
So it looks like there will have to be some sort of way to determine
which board the kernel is running on. According to AMCC, all Rev 0's
have the 440EP Rev A processor and all Rev 1's have the 440EP Rev B
processor. AMCC also says that the best way for software to determine
to determine which board rev it is running on is to either use the PVR
or the JTAG ID. I agree this is not an ideal solution, but it seems to
be the best one.
I am, however, open to suggestions, if anyone knows of a better
solution.
Thanks,
-Wade Farnsworth
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-18 19:30 ` Tom Rini
@ 2005-03-31 16:26 ` Wade Farnsworth
2005-03-31 16:34 ` Tom Rini
0 siblings, 1 reply; 35+ messages in thread
From: Wade Farnsworth @ 2005-03-31 16:26 UTC (permalink / raw)
To: Jason McMullan, Tom Rini; +Cc: linuxppc-embedded Linux list
On Fri, 2005-03-18 at 12:30, Tom Rini wrote:
> On Fri, Mar 18, 2005 at 01:43:11PM -0500, Jason McMullan wrote:
> > On Fri, 2005-03-18 at 10:06 -0600, Kumar Gala wrote:
> > > Can you build your patch for the lopec_defconfig and fix the errors
> > > associated with enabling altivec.
> > >
> > > Looks like you need to include asm/offset.h & asm/page.h in vector.S,
> > > however there is another build error after that.
> >
> > Thanks! That also found a linking bug, fixed in this patch.. Please
> > double check the call in 'AltiVecUnavalible' in head.S, and the re-load
> > of 'ctr' at the end of load_up_altivec, as I do not have an AltiVec
> > machine here.
>
> No dice:
> VFS: Mounted root (nfs filesystem) readonly.
> Freeing unused kernel memory: 100k init 4k prep
> floating point used in kernel (task=c03816b0, pc=c000d664)
> Doing some objdump'ing, that's the start of load_up_altivec.
Hi Jason and Tom,
Has there been any more progress on this patch?
Thanks,
Wade Farnsworth
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-31 16:26 ` Wade Farnsworth
@ 2005-03-31 16:34 ` Tom Rini
2005-03-31 18:45 ` Kumar Gala
2005-03-31 20:10 ` Matt
0 siblings, 2 replies; 35+ messages in thread
From: Tom Rini @ 2005-03-31 16:34 UTC (permalink / raw)
To: Wade Farnsworth; +Cc: linuxppc-embedded Linux list
On Thu, Mar 31, 2005 at 09:26:18AM -0700, Wade Farnsworth wrote:
> On Fri, 2005-03-18 at 12:30, Tom Rini wrote:
> > On Fri, Mar 18, 2005 at 01:43:11PM -0500, Jason McMullan wrote:
> > > On Fri, 2005-03-18 at 10:06 -0600, Kumar Gala wrote:
> > > > Can you build your patch for the lopec_defconfig and fix the errors
> > > > associated with enabling altivec.
> > > >
> > > > Looks like you need to include asm/offset.h & asm/page.h in vector.S,
> > > > however there is another build error after that.
> > >
> > > Thanks! That also found a linking bug, fixed in this patch.. Please
> > > double check the call in 'AltiVecUnavalible' in head.S, and the re-load
> > > of 'ctr' at the end of load_up_altivec, as I do not have an AltiVec
> > > machine here.
> >
> > No dice:
> > VFS: Mounted root (nfs filesystem) readonly.
> > Freeing unused kernel memory: 100k init 4k prep
> > floating point used in kernel (task=c03816b0, pc=c000d664)
> > Doing some objdump'ing, that's the start of load_up_altivec.
>
> Hi Jason and Tom,
>
> Has there been any more progress on this patch?
Sadly no. We got to the point where it was reliably crashing on my
LoPEC (7400), but no time to try and fix it. The problem should show up
on any classic PPC box..
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-31 16:34 ` Tom Rini
@ 2005-03-31 18:45 ` Kumar Gala
2005-03-31 19:04 ` Tom Rini
2005-03-31 20:10 ` Matt
1 sibling, 1 reply; 35+ messages in thread
From: Kumar Gala @ 2005-03-31 18:45 UTC (permalink / raw)
To: Tom Rini; +Cc: linuxppc-embedded Linux list
Tom,
On Mar 31, 2005, at 10:34 AM, Tom Rini wrote:
> On Thu, Mar 31, 2005 at 09:26:18AM -0700, Wade Farnsworth wrote:
> > On Fri, 2005-03-18 at 12:30, Tom Rini wrote:
> > > On Fri, Mar 18, 2005 at 01:43:11PM -0500, Jason McMullan wrote:
> > > > On Fri, 2005-03-18 at 10:06 -0600, Kumar Gala wrote:
> > > > > Can you build your patch for the lopec_defconfig and fix the=20=
> errors
> > > > > associated with enabling altivec.
> > > > >
> > > > > Looks like you need to include asm/offset.h & asm/page.h in=20
> vector.S,
> > > > > however there is another build error after that.
> > > >
> > > > Thanks! That also found a linking bug, fixed in this patch..=20
> Please
> > > > double check the call in 'AltiVecUnavalible' in head.S, and the=20=
> re-load
> > > > of 'ctr' at the end of load_up_altivec, as I do not have an=20
> AltiVec
> > > > machine here.
> > >
> > > No dice:
> > > VFS: Mounted root (nfs filesystem) readonly.
> > > Freeing unused kernel memory: 100k init 4k prep
> > > floating point used in kernel (task=3Dc03816b0, pc=3Dc000d664)
> > > Doing some objdump'ing, that's the start of load_up_altivec.
> >
> > Hi Jason and Tom,
> >
> > Has there been any more progress on this patch?
>
> Sadly no.=A0 We got to the point where it was reliably crashing on my
> LoPEC (7400), but no time to try and fix it.=A0 The problem should =
show=20
> up
> on any classic PPC box..
Is it crashing on just avec code or everything?
- kumar
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-31 18:45 ` Kumar Gala
@ 2005-03-31 19:04 ` Tom Rini
0 siblings, 0 replies; 35+ messages in thread
From: Tom Rini @ 2005-03-31 19:04 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-embedded Linux list
On Thu, Mar 31, 2005 at 12:45:44PM -0600, Kumar Gala wrote:
> Tom,
>
> On Mar 31, 2005, at 10:34 AM, Tom Rini wrote:
>
> >On Thu, Mar 31, 2005 at 09:26:18AM -0700, Wade Farnsworth wrote:
> > > On Fri, 2005-03-18 at 12:30, Tom Rini wrote:
> > > > On Fri, Mar 18, 2005 at 01:43:11PM -0500, Jason McMullan wrote:
> > > > > On Fri, 2005-03-18 at 10:06 -0600, Kumar Gala wrote:
> > > > > > Can you build your patch for the lopec_defconfig and fix the
> >errors
> >> > > > associated with enabling altivec.
> > > > > >
> >> > > > Looks like you need to include asm/offset.h & asm/page.h in
> >vector.S,
> >> > > > however there is another build error after that.
> > > > >
> >> > > Thanks! That also found a linking bug, fixed in this patch..
> >Please
> > > > > double check the call in 'AltiVecUnavalible' in head.S, and the
> >re-load
> > > > > of 'ctr' at the end of load_up_altivec, as I do not have an
> >AltiVec
> > > > > machine here.
> > > >
> >> > No dice:
> > > > VFS: Mounted root (nfs filesystem) readonly.
> > > > Freeing unused kernel memory: 100k init 4k prep
> > > > floating point used in kernel (task=c03816b0, pc=c000d664)
> >> > Doing some objdump'ing, that's the start of load_up_altivec.
> >>
> >> Hi Jason and Tom,
> > >
> >> Has there been any more progress on this patch?
> >
> >Sadly no.? We got to the point where it was reliably crashing on my
> >LoPEC (7400), but no time to try and fix it.? The problem should show
> >up
> > on any classic PPC box..
>
> Is it crashing on just avec code or everything?
That's a good question. IIRC, I was using a userspace with an
altivec-using setjmp/longjmp, so it could have been Altivec-specific.
I don't have test kernels w/ the patch handy anymore to verify, sorry.
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-31 16:34 ` Tom Rini
2005-03-31 18:45 ` Kumar Gala
@ 2005-03-31 20:10 ` Matt
2005-03-31 20:15 ` Tom Rini
2005-03-31 23:37 ` Josh Boyer
1 sibling, 2 replies; 35+ messages in thread
From: Matt @ 2005-03-31 20:10 UTC (permalink / raw)
To: Tom Rini; +Cc: linuxppc-embedded Linux list
On Thu, Mar 31, 2005 at 09:34:21AM -0700, Tom Rini wrote:
> On Thu, Mar 31, 2005 at 09:26:18AM -0700, Wade Farnsworth wrote:
> > On Fri, 2005-03-18 at 12:30, Tom Rini wrote:
> > > On Fri, Mar 18, 2005 at 01:43:11PM -0500, Jason McMullan wrote:
> > > > On Fri, 2005-03-18 at 10:06 -0600, Kumar Gala wrote:
> > > > > Can you build your patch for the lopec_defconfig and fix the errors
> > > > > associated with enabling altivec.
> > > > >
> > > > > Looks like you need to include asm/offset.h & asm/page.h in vector.S,
> > > > > however there is another build error after that.
> > > >
> > > > Thanks! That also found a linking bug, fixed in this patch.. Please
> > > > double check the call in 'AltiVecUnavalible' in head.S, and the re-load
> > > > of 'ctr' at the end of load_up_altivec, as I do not have an AltiVec
> > > > machine here.
> > >
> > > No dice:
> > > VFS: Mounted root (nfs filesystem) readonly.
> > > Freeing unused kernel memory: 100k init 4k prep
> > > floating point used in kernel (task=c03816b0, pc=c000d664)
> > > Doing some objdump'ing, that's the start of load_up_altivec.
> >
> > Hi Jason and Tom,
> >
> > Has there been any more progress on this patch?
>
> Sadly no. We got to the point where it was reliably crashing on my
> LoPEC (7400), but no time to try and fix it. The problem should show up
> on any classic PPC box..
If nobody has time to work on this, then I intend to put Wade's 440EP
support in as is (actually, he's planning on resubmitting with some
additional changes). When somebody has time, they can redo the patch
against that.
-Matt
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-31 20:10 ` Matt
@ 2005-03-31 20:15 ` Tom Rini
2005-03-31 23:10 ` Kumar Gala
2005-03-31 23:37 ` Josh Boyer
1 sibling, 1 reply; 35+ messages in thread
From: Tom Rini @ 2005-03-31 20:15 UTC (permalink / raw)
To: Matt, Jason McMullan; +Cc: linuxppc-embedded Linux list
On Thu, Mar 31, 2005 at 01:10:44PM -0700, Matt wrote:
> On Thu, Mar 31, 2005 at 09:34:21AM -0700, Tom Rini wrote:
> > On Thu, Mar 31, 2005 at 09:26:18AM -0700, Wade Farnsworth wrote:
> > > On Fri, 2005-03-18 at 12:30, Tom Rini wrote:
> > > > On Fri, Mar 18, 2005 at 01:43:11PM -0500, Jason McMullan wrote:
> > > > > On Fri, 2005-03-18 at 10:06 -0600, Kumar Gala wrote:
> > > > > > Can you build your patch for the lopec_defconfig and fix the errors
> > > > > > associated with enabling altivec.
> > > > > >
> > > > > > Looks like you need to include asm/offset.h & asm/page.h in vector.S,
> > > > > > however there is another build error after that.
> > > > >
> > > > > Thanks! That also found a linking bug, fixed in this patch.. Please
> > > > > double check the call in 'AltiVecUnavalible' in head.S, and the re-load
> > > > > of 'ctr' at the end of load_up_altivec, as I do not have an AltiVec
> > > > > machine here.
> > > >
> > > > No dice:
> > > > VFS: Mounted root (nfs filesystem) readonly.
> > > > Freeing unused kernel memory: 100k init 4k prep
> > > > floating point used in kernel (task=c03816b0, pc=c000d664)
> > > > Doing some objdump'ing, that's the start of load_up_altivec.
> > >
> > > Hi Jason and Tom,
> > >
> > > Has there been any more progress on this patch?
> >
> > Sadly no. We got to the point where it was reliably crashing on my
> > LoPEC (7400), but no time to try and fix it. The problem should show up
> > on any classic PPC box..
>
> If nobody has time to work on this, then I intend to put Wade's 440EP
> support in as is (actually, he's planning on resubmitting with some
> additional changes). When somebody has time, they can redo the patch
> against that.
That's a good point to bring up. Jason, do you want to post your
current version to the list and we can try and see if we can get it
workign right?
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-31 20:15 ` Tom Rini
@ 2005-03-31 23:10 ` Kumar Gala
0 siblings, 0 replies; 35+ messages in thread
From: Kumar Gala @ 2005-03-31 23:10 UTC (permalink / raw)
To: Tom Rini; +Cc: linuxppc-embedded Linux list
I'll try to see if I can build a kernel to use on a pegasos box to test=20=
out the avec side tomorrow.
- kumar
On Mar 31, 2005, at 2:15 PM, Tom Rini wrote:
> On Thu, Mar 31, 2005 at 01:10:44PM -0700, Matt wrote:
> > On Thu, Mar 31, 2005 at 09:34:21AM -0700, Tom Rini wrote:
> > > On Thu, Mar 31, 2005 at 09:26:18AM -0700, Wade Farnsworth wrote:
> > > > On Fri, 2005-03-18 at 12:30, Tom Rini wrote:
> > > > > On Fri, Mar 18, 2005 at 01:43:11PM -0500, Jason McMullan=20
> wrote:
> > > > > > On Fri, 2005-03-18 at 10:06 -0600, Kumar Gala wrote:
> > > > > > > Can you build your patch for the lopec_defconfig and fix=20=
> the errors
> > > > > > > associated with enabling altivec.
> > > > > > >
> > > > > > > Looks like you need to include asm/offset.h & asm/page.h=20=
> in vector.S,
> > > > > > > however there is another build error after that.
> > > > > >
> > > > > > Thanks! That also found a linking bug, fixed in this patch..=20=
> Please
> > > > > > double check the call in 'AltiVecUnavalible' in head.S, and=20=
> the re-load
> > > > > > of 'ctr' at the end of load_up_altivec, as I do not have an=20=
> AltiVec
> > > > > > machine here.
> > > > >
> > > > > No dice:
> > > > > VFS: Mounted root (nfs filesystem) readonly.
> > > > > Freeing unused kernel memory: 100k init 4k prep
> > > > > floating point used in kernel (task=3Dc03816b0, pc=3Dc000d664)
> > > > > Doing some objdump'ing, that's the start of load_up_altivec.
> > > >
> > > > Hi Jason and Tom,
> > > >
> > > > Has there been any more progress on this patch?
> > >
> > > Sadly no.=A0 We got to the point where it was reliably crashing on =
my
> > > LoPEC (7400), but no time to try and fix it.=A0 The problem should=20=
> show up
> > > on any classic PPC box..
> >
> > If nobody has time to work on this, then I intend=A0 to put Wade's=20=
> 440EP
> > support in as is (actually, he's planning on resubmitting with some
> > additional changes).=A0 When somebody has time, they can redo the=20=
> patch
> > against that.
>
> That's a good point to bring up.=A0 Jason, do you want to post your
> current version to the list and we can try and see if we can get it
> workign right?
>
> --=20
> Tom Rini
> http://gate.crashing.org/~trini/
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: 440EP FPU patch
2005-03-31 20:10 ` Matt
2005-03-31 20:15 ` Tom Rini
@ 2005-03-31 23:37 ` Josh Boyer
1 sibling, 0 replies; 35+ messages in thread
From: Josh Boyer @ 2005-03-31 23:37 UTC (permalink / raw)
To: Matt; +Cc: Tom Rini, linuxppc-embedded Linux list
On Thu, 2005-03-31 at 13:10 -0700, Matt wrote:
>
> If nobody has time to work on this, then I intend to put Wade's 440EP
> support in as is (actually, he's planning on resubmitting with some
> additional changes). When somebody has time, they can redo the patch
> against that.
Do those changes happen to include the MTD driver for the NAND
controller? Wade, any word on that?
josh
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2005-03-31 23:37 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2005-03-15 17:17 [PATCH 1/3] PPC440EP SoC and Bamboo board support Wade Farnsworth
2005-03-15 18:41 ` Eugene Surovegin
2005-03-15 19:08 ` Wade Farnsworth
2005-03-15 20:58 ` Jason McMullan
2005-03-15 21:38 ` Wade Farnsworth
2005-03-15 18:47 ` [PATCH 2/3] PPC440EP: ibm_emac phy mode bug fix Wade Farnsworth
2005-03-15 18:58 ` [PATCH 3/3] PPC440EP IBM EMAC support Wade Farnsworth
2005-03-15 19:22 ` Eugene Surovegin
2005-03-15 19:24 ` Eugene Surovegin
2005-03-15 20:43 ` Matt Porter
2005-03-15 20:37 ` Matt Porter
2005-03-28 17:52 ` Wade Farnsworth
2005-03-15 19:31 ` 440EP FPU patch McMullan, Jason
2005-03-15 20:50 ` Matt Porter
2005-03-15 21:09 ` Kumar Gala
2005-03-15 22:18 ` Jason McMullan
2005-03-16 7:22 ` Kumar Gala
2005-03-16 22:14 ` Tom Rini
2005-03-16 22:52 ` Kumar Gala
2005-03-16 23:18 ` Tom Rini
2005-03-18 16:06 ` Kumar Gala
2005-03-18 18:43 ` Jason McMullan
2005-03-18 19:30 ` Tom Rini
2005-03-31 16:26 ` Wade Farnsworth
2005-03-31 16:34 ` Tom Rini
2005-03-31 18:45 ` Kumar Gala
2005-03-31 19:04 ` Tom Rini
2005-03-31 20:10 ` Matt
2005-03-31 20:15 ` Tom Rini
2005-03-31 23:10 ` Kumar Gala
2005-03-31 23:37 ` Josh Boyer
2005-03-16 1:43 ` [PATCH 1/3] PPC440EP SoC and Bamboo board support Josh Boyer
2005-03-16 16:09 ` Wade Farnsworth
2005-03-16 17:26 ` Jason McMullan
2005-03-16 18:04 ` Wade Farnsworth
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