From: David Hildenbrand <david@redhat.com>
To: Alistair Popple <apopple@nvidia.com>
Cc: "Sierra Guiza, Alejandro \(Alex\)" <alex.sierra@amd.com>,
Ralph Campbell <rcampbell@nvidia.com>,
Lyude Paul <lyude@redhat.com>, Karol Herbst <kherbst@redhat.com>,
Nadav Amit <nadav.amit@gmail.com>,
Felix Kuehling <Felix.Kuehling@amd.com>,
linuxppc-dev@lists.ozlabs.org,
LKML <linux-kernel@vger.kernel.org>, Peter Xu <peterx@redhat.com>,
linux-mm@kvack.org, Logan Gunthorpe <logang@deltatee.com>,
Matthew Wilcox <willy@infradead.org>,
Jason Gunthorpe <jgg@nvidia.com>,
John Hubbard <jhubbard@nvidia.com>,
stable@vger.kernel.org, akpm@linux-foundation.org,
huang ying <huang.ying.caritas@gmail.com>,
Ben Skeggs <bskeggs@redhat.com>
Subject: Re: [PATCH v3 1/3] mm/migrate_device.c: Flush TLB while holding PTL
Date: Wed, 24 Aug 2022 14:35:51 +0200 [thread overview]
Message-ID: <6e31290a-5b72-ceb6-b11c-f8c1b066beaf@redhat.com> (raw)
In-Reply-To: <87wnaxg6u4.fsf@nvdebian.thelocal>
On 24.08.22 14:26, Alistair Popple wrote:
>
> David Hildenbrand <david@redhat.com> writes:
>
>> On 24.08.22 05:03, Alistair Popple wrote:
>>> When clearing a PTE the TLB should be flushed whilst still holding the
>>> PTL to avoid a potential race with madvise/munmap/etc. For example
>>> consider the following sequence:
>>>
>>> CPU0 CPU1
>>> ---- ----
>>>
>>> migrate_vma_collect_pmd()
>>> pte_unmap_unlock()
>>> madvise(MADV_DONTNEED)
>>> -> zap_pte_range()
>>> pte_offset_map_lock()
>>> [ PTE not present, TLB not flushed ]
>>> pte_unmap_unlock()
>>> [ page is still accessible via stale TLB ]
>>> flush_tlb_range()
>>>
>>> In this case the page may still be accessed via the stale TLB entry
>>> after madvise returns. Fix this by flushing the TLB while holding the
>>> PTL.
>>>
>>> Signed-off-by: Alistair Popple <apopple@nvidia.com>
>>> Reported-by: Nadav Amit <nadav.amit@gmail.com>
>>> Fixes: 8c3328f1f36a ("mm/migrate: migrate_vma() unmap page from vma while collecting pages")
>>> Cc: stable@vger.kernel.org
>>>
>>> ---
>>>
>>> Changes for v3:
>>>
>>> - New for v3
>>> ---
>>> mm/migrate_device.c | 5 +++--
>>> 1 file changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/mm/migrate_device.c b/mm/migrate_device.c
>>> index 27fb37d..6a5ef9f 100644
>>> --- a/mm/migrate_device.c
>>> +++ b/mm/migrate_device.c
>>> @@ -254,13 +254,14 @@ static int migrate_vma_collect_pmd(pmd_t *pmdp,
>>> migrate->dst[migrate->npages] = 0;
>>> migrate->src[migrate->npages++] = mpfn;
>>> }
>>> - arch_leave_lazy_mmu_mode();
>>> - pte_unmap_unlock(ptep - 1, ptl);
>>>
>>> /* Only flush the TLB if we actually modified any entries */
>>> if (unmapped)
>>> flush_tlb_range(walk->vma, start, end);
>>>
>>> + arch_leave_lazy_mmu_mode();
>>> + pte_unmap_unlock(ptep - 1, ptl);
>>> +
>>> return 0;
>>> }
>>>
>>>
>>> base-commit: ffcf9c5700e49c0aee42dcba9a12ba21338e8136
>>
>> I'm not a TLB-flushing expert, but this matches my understanding (and a
>> TLB flushing Linux documentation I stumbled over some while ago but
>> cannot quickly find).
>>
>> In the ordinary try_to_migrate_one() path, flushing would happen via
>> ptep_clear_flush() (just like we do for the anon_exclusive case here as
>> well), correct?
>
> Correct.
>
Acked-by: David Hildenbrand <david@redhat.com>
--
Thanks,
David / dhildenb
next prev parent reply other threads:[~2022-08-24 12:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-24 3:03 [PATCH v3 1/3] mm/migrate_device.c: Flush TLB while holding PTL Alistair Popple
2022-08-24 3:03 ` [PATCH v3 2/3] mm/migrate_device.c: Copy pte dirty bit to page Alistair Popple
2022-08-24 15:39 ` Peter Xu
2022-08-25 22:21 ` Alistair Popple
2022-08-25 23:27 ` Peter Xu
2022-08-26 1:02 ` Alistair Popple
2022-08-26 1:14 ` Huang, Ying
2022-08-26 14:32 ` Peter Xu
2022-08-26 14:47 ` David Hildenbrand
2022-08-26 15:55 ` Peter Xu
2022-08-26 16:46 ` David Hildenbrand
2022-08-26 21:37 ` Peter Xu
2022-08-26 22:19 ` David Hildenbrand
2022-08-24 3:03 ` [PATCH v3 3/3] selftests/hmm-tests: Add test for dirty bits Alistair Popple
2022-08-24 8:21 ` [PATCH v3 1/3] mm/migrate_device.c: Flush TLB while holding PTL David Hildenbrand
2022-08-24 12:26 ` Alistair Popple
2022-08-24 12:35 ` David Hildenbrand [this message]
2022-08-25 1:36 ` Huang, Ying
2022-08-25 22:35 ` Alistair Popple
2022-08-26 0:56 ` Huang, Ying
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