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From: Michael Neuling <mikey@neuling.org>
To: Vladimir Murzin <murzin.v@gmail.com>
Cc: linuxppc-dev@lists.ozlabs.org, matt@ozlabs.org, paulus@samba.org
Subject: Re: [PATCH] powerpc: net: filter: fix DIVWU instruction opcode
Date: Thu, 12 Sep 2013 10:32:59 +1000	[thread overview]
Message-ID: <7012.1378945979@ale.ozlabs.ibm.com> (raw)
In-Reply-To: <1378915410-2262-1-git-send-email-murzin.v@gmail.com>

Vladimir Murzin <murzin.v@gmail.com> wrote:

> Currently DIVWU stands for *signed* divw opcode:
> 
> 7d 2a 4b 96 	divwu   r9,r10,r9
> 7d 2a 4b d6 	divw    r9,r10,r9
> 
> Use the *unsigned* divw opcode for DIVWU.

This looks like it's in only used in the BPF JIT code.  

Matt, any chance you an ACK/NACK this?

Mikey

> 
> Signed-off-by: Vladimir Murzin <murzin.v@gmail.com>
> ---
>  arch/powerpc/include/asm/ppc-opcode.h |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
> index d7fe9f5..c91842c 100644
> --- a/arch/powerpc/include/asm/ppc-opcode.h
> +++ b/arch/powerpc/include/asm/ppc-opcode.h
> @@ -218,7 +218,7 @@
>  #define PPC_INST_MULLW			0x7c0001d6
>  #define PPC_INST_MULHWU			0x7c000016
>  #define PPC_INST_MULLI			0x1c000000
> -#define PPC_INST_DIVWU			0x7c0003d6
> +#define PPC_INST_DIVWU			0x7c000396
>  #define PPC_INST_RLWINM			0x54000000
>  #define PPC_INST_RLDICR			0x78000004
>  #define PPC_INST_SLW			0x7c000030
> -- 
> 1.7.10.4
> 

  reply	other threads:[~2013-09-12  0:32 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-09-11 16:03 [PATCH] powerpc: net: filter: fix DIVWU instruction opcode Vladimir Murzin
2013-09-12  0:32 ` Michael Neuling [this message]
2013-09-12  0:58   ` Matt Evans
2013-09-12  2:52     ` Vladimir Murzin

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