[PATCH] [POWERPC] Cleanup mpic nodes in .dts

[PATCH] [POWERPC] Cleanup mpic nodes in .dts

[Kumar Gala]

Removed clock-frequency and big-endian props as they aren't specified
anywhere.

---

In my powerpc-next branch.

 Documentation/powerpc/booting-without-of.txt |    6 ------
 arch/powerpc/boot/dts/mpc7448hpc2.dts        |    2 --
 arch/powerpc/boot/dts/mpc8540ads.dts         |    2 --
 arch/powerpc/boot/dts/mpc8541cds.dts         |    2 --
 arch/powerpc/boot/dts/mpc8544ds.dts          |    2 --
 arch/powerpc/boot/dts/mpc8548cds.dts         |    2 --
 arch/powerpc/boot/dts/mpc8555cds.dts         |    2 --
 arch/powerpc/boot/dts/mpc8560ads.dts         |    1 +
 arch/powerpc/boot/dts/mpc8568mds.dts         |    2 --
 arch/powerpc/boot/dts/mpc8572ds.dts          |    2 --
 arch/powerpc/boot/dts/mpc8610_hpcd.dts       |    2 --
 arch/powerpc/boot/dts/mpc8641_hpcn.dts       |    2 --
 arch/powerpc/boot/dts/sbc8548.dts            |    2 --
 arch/powerpc/boot/dts/sbc8560.dts            |    2 +-
 arch/powerpc/boot/dts/storcenter.dts         |    1 +
 arch/powerpc/boot/dts/stx_gp3_8560.dts       |    1 +
 arch/powerpc/boot/dts/tqm8540.dts            |    1 +
 arch/powerpc/boot/dts/tqm8541.dts            |    1 +
 arch/powerpc/boot/dts/tqm8555.dts            |    1 +
 arch/powerpc/boot/dts/tqm8560.dts            |    1 +
 20 files changed, 8 insertions(+), 29 deletions(-)

diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index c67d2f5..948f641 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1363,14 +1363,11 @@ platforms are moved over to use the flattened-device-tree model.
 
 	pic@40000 {
 		linux,phandle = <40000>;
-		clock-frequency = <0>;
 		interrupt-controller;
 		#address-cells = <0>;
 		reg = <40000 40000>;
-		built-in;
 		compatible = "chrp,open-pic";
 		device_type = "open-pic";
-		big-endian;
 	};
 
 
@@ -3663,14 +3660,11 @@ not necessary as they are usually the same as the root node.
 
 		pic@40000 {
 			linux,phandle = <40000>;
-			clock-frequency = <0>;
 			interrupt-controller;
 			#address-cells = <0>;
 			reg = <40000 40000>;
-			built-in;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
-                        big-endian;
 		};
 
 		i2c@3000 {
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
index 4936349..705c23c 100644
--- a/arch/powerpc/boot/dts/mpc7448hpc2.dts
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -124,14 +124,12 @@
 		};
 
 	  	mpic: pic@7400 {
-			clock-frequency = <0>;
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x7400 0x400>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
-                       	big-endian;
 		};
 		pci@1000 {
 			compatible = "tsi108-pci";
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 18033ed..58e165e 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -165,14 +165,12 @@
 			interrupt-parent = <&mpic>;
 		};
 		mpic: pic@40000 {
-			clock-frequency = <0>;
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
-			big-endian;
 		};
 	};
 
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 663c7c5..21ebe7c 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -148,14 +148,12 @@
 		};
 
 		mpic: pic@40000 {
-			clock-frequency = <0>;
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
-                        big-endian;
 		};
 
 		cpm@919c0 {
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 1cfd970..921f9f6 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -210,14 +210,12 @@
 		};
 
 		mpic: pic@40000 {
-			clock-frequency = <0>;
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
-			big-endian;
 		};
 
 		msi@41600 {
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index fa298a8..213c88e 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -208,14 +208,12 @@
 		};
 
 		mpic: pic@40000 {
-			clock-frequency = <0>;
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
-                        big-endian;
 		};
 	};
 
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index b025c56..400f6db 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -148,14 +148,12 @@
 		};
 
 		mpic: pic@40000 {
-			clock-frequency = <0>;
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
-                        big-endian;
 		};
 
 		cpm@919c0 {
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index 0cc16ab..f0b1f98 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -134,6 +134,7 @@
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
+			compatible = "chrp,open-pic";
 			device_type = "open-pic";
 		};
 
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index a025a8e..d9064ee 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -202,14 +202,12 @@
 		};
 
 		mpic: pic@40000 {
-			clock-frequency = <0>;
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
-                        big-endian;
 		};
 
 		par_io@e0100 {
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index 174d51a..3ca8cae 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -238,14 +238,12 @@
 		};
 
 		mpic: pic@40000 {
-			clock-frequency = <0>;
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
-			big-endian;
 		};
 	};
 
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index fa9c297..186f102 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -172,14 +172,12 @@
 		};
 
 		mpic: interrupt-controller@40000 {
-			clock-frequency = <0>;
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
-			big-endian;
 		};
 
 		msi@41600 {
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 1e4bfe9..14f718d 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -239,14 +239,12 @@
 		};
 
 		mpic: pic@40000 {
-			clock-frequency = <0>;
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
-			big-endian;
 		};
 
 		global-utilities@e0000 {
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 22d9671..ce496fb 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -265,12 +265,10 @@
 		mpic: pic@40000 {
 			interrupt-controller;
 			#address-cells = <0>;
-			#size-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			compatible = "chrp,open-pic";
 			device_type = "open-pic";
-                        big-endian;
 		};
 	};
 
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
index 0476802..2663501 100644
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -155,8 +155,8 @@
 		mpic: pic@40000 {
 			interrupt-controller;
 			#address-cells = <0>;
-			#size-cells = <0>;
 			#interrupt-cells = <2>;
+			compatible = "chrp,open-pic";
 			reg = <0x40000 0x40000>;
 			device_type = "open-pic";
 		};
diff --git a/arch/powerpc/boot/dts/storcenter.dts b/arch/powerpc/boot/dts/storcenter.dts
index 5893816..eab680c 100644
--- a/arch/powerpc/boot/dts/storcenter.dts
+++ b/arch/powerpc/boot/dts/storcenter.dts
@@ -95,6 +95,7 @@
 
 		mpic: interrupt-controller@40000 {
 			#interrupt-cells = <2>;
+			#address-cells = <0>;
 			device_type = "open-pic";
 			compatible = "chrp,open-pic";
 			interrupt-controller;
diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts
index f81fd7f..096277b 100644
--- a/arch/powerpc/boot/dts/stx_gp3_8560.dts
+++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts
@@ -131,6 +131,7 @@
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
+			compatible = "chrp,open-pic";
 			device_type = "open-pic";
 		};
 
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 1addb3a..8ee4664 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -177,6 +177,7 @@
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			device_type = "open-pic";
+			compatible = "chrp,open-pic";
 		};
 	};
 
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index 9e01093..cadbebf 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -164,6 +164,7 @@
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			device_type = "open-pic";
+			compatible = "chrp,open-pic";
 		};
 
 		cpm@919c0 {
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index a20eb06..9d6dc04 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -164,6 +164,7 @@
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			device_type = "open-pic";
+			compatible = "chrp,open-pic";
 		};
 
 		cpm@919c0 {
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index b9ac6c9..358cbd7 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -145,6 +145,7 @@
 			#interrupt-cells = <2>;
 			reg = <0x40000 0x40000>;
 			device_type = "open-pic";
+			compatible = "chrp,open-pic";
 		};
 
 		cpm@919c0 {
-- 
1.5.4.5

[PATCH] [POWERPC] 85xx: Add next-level-cache property

[Kumar Gala]

Added next-level-cache to the L1 and a reference to the new L2 label.

---
In my powerpc-next branch.

 arch/powerpc/boot/dts/ksi8560.dts      |    3 ++-
 arch/powerpc/boot/dts/mpc8540ads.dts   |    3 ++-
 arch/powerpc/boot/dts/mpc8541cds.dts   |    3 ++-
 arch/powerpc/boot/dts/mpc8544ds.dts    |    3 ++-
 arch/powerpc/boot/dts/mpc8548cds.dts   |    3 ++-
 arch/powerpc/boot/dts/mpc8555cds.dts   |    3 ++-
 arch/powerpc/boot/dts/mpc8560ads.dts   |    2 +-
 arch/powerpc/boot/dts/mpc8568mds.dts   |    3 ++-
 arch/powerpc/boot/dts/mpc8572ds.dts    |    4 +++-
 arch/powerpc/boot/dts/sbc8548.dts      |    3 ++-
 arch/powerpc/boot/dts/sbc8560.dts      |    3 ++-
 arch/powerpc/boot/dts/stx_gp3_8560.dts |    3 ++-
 arch/powerpc/boot/dts/tqm8540.dts      |    3 ++-
 arch/powerpc/boot/dts/tqm8541.dts      |    3 ++-
 arch/powerpc/boot/dts/tqm8555.dts      |    3 ++-
 arch/powerpc/boot/dts/tqm8560.dts      |    3 ++-
 16 files changed, 32 insertions(+), 16 deletions(-)

diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
index f869ce3..6eb7c77 100644
--- a/arch/powerpc/boot/dts/ksi8560.dts
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -40,6 +40,7 @@
 			timebase-frequency = <0>;		/* From U-boot */
 			bus-frequency = <0>;			/* From U-boot */
 			clock-frequency = <0>;			/* From U-boot */
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -62,7 +63,7 @@
 			interrupts = <0x12 0x2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8540-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <0x20>;		/* 32 bytes */
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 58e165e..79881a1 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -40,6 +40,7 @@
 			timebase-frequency = <0>;	//  33 MHz, from uboot
 			bus-frequency = <0>;	// 166 MHz
 			clock-frequency = <0>;	// 825 MHz, from uboot
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -63,7 +64,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8540-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 21ebe7c..66192aa 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -40,6 +40,7 @@
 			timebase-frequency = <0>;	//  33 MHz, from uboot
 			bus-frequency = <0>;	// 166 MHz
 			clock-frequency = <0>;	// 825 MHz, from uboot
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -63,7 +64,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8541-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 921f9f6..6cf533f 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -41,6 +41,7 @@
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -65,7 +66,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8544-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 213c88e..205598d 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -45,6 +45,7 @@
 			timebase-frequency = <0>;	//  33 MHz, from uboot
 			bus-frequency = <0>;	// 166 MHz
 			clock-frequency = <0>;	// 825 MHz, from uboot
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -68,7 +69,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8548-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 400f6db..7c9d0b1 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -40,6 +40,7 @@
 			timebase-frequency = <0>;	//  33 MHz, from uboot
 			bus-frequency = <0>;	// 166 MHz
 			clock-frequency = <0>;	// 825 MHz, from uboot
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -63,7 +64,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8555-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index f0b1f98..5d9f3c4 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -64,7 +64,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8540-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index d9064ee..d7af8db 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -42,6 +42,7 @@
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -70,7 +71,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8568-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index 3ca8cae..a444e6a 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -42,6 +42,7 @@
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
+			next-level-cache = <&L2>;
 		};
 
 		PowerPC,8572@1 {
@@ -54,6 +55,7 @@
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -84,7 +86,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,mpc8572-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index ce496fb..d252e38 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -44,6 +44,7 @@
 			timebase-frequency = <0>;	// From uboot
 			bus-frequency = <0>;
 			clock-frequency = <0>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -161,7 +162,7 @@
 			interrupts = <0x12 0x2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8548-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <0x20>;	// 32 bytes
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
index 2663501..e556c5a 100644
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ b/arch/powerpc/boot/dts/sbc8560.dts
@@ -43,6 +43,7 @@
 			timebase-frequency = <0>;	// From uboot
 			bus-frequency = <0>;
 			clock-frequency = <0>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -66,7 +67,7 @@
 			interrupts = <0x12 0x2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8560-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <0x20>;	// 32 bytes
diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts
index 096277b..1e61283 100644
--- a/arch/powerpc/boot/dts/stx_gp3_8560.dts
+++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts
@@ -38,6 +38,7 @@
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -62,7 +63,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8540-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 8ee4664..7b653a5 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -40,6 +40,7 @@
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -64,7 +65,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8540-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index cadbebf..8fe73ef 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -39,6 +39,7 @@
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -63,7 +64,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8540-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 9d6dc04..0a53bb9 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -39,6 +39,7 @@
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -63,7 +64,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8540-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index 358cbd7..a4ee596 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -40,6 +40,7 @@
 			timebase-frequency = <0>;
 			bus-frequency = <0>;
 			clock-frequency = <0>;
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -64,7 +65,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8540-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;
-- 
1.5.4.5

Re: [PATCH] [POWERPC] Cleanup mpic nodes in .dts

[Segher Boessenkool]

> Removed clock-frequency and big-endian props as they aren't specified
> anywhere.

If you remove "big-endian", you'll have to provide some other way
to get that information (like, some new "compatible" value).

Dunno if we need "clock-frequency".

This patch also removes "built-in" properties.  I'm all for that,
but the patch description didn't say it does.


Segher

Re: [PATCH] [POWERPC] 85xx: Add next-level-cache property

[Segher Boessenkool]

> Added next-level-cache to the L1 and a reference to the new L2 label.

Where is this property defined?  I can't find it.

The PowerPC binding defines an "l2-cache" property for this (it
points from CPU node to L2 cache node, from L2 cache node to L3
cache node, from L3 cache node to L4 cache node, etc.)


Segher

Re: [PATCH] [POWERPC] 85xx: Add next-level-cache property

[Kumar Gala]

On May 30, 2008, at 4:49 PM, Segher Boessenkool wrote:

>> Added next-level-cache to the L1 and a reference to the new L2 label.
>
> Where is this property defined?  I can't find it.

its in ePAPR.

> The PowerPC binding defines an "l2-cache" property for this (it
> points from CPU node to L2 cache node, from L2 cache node to L3
> cache node, from L3 cache node to L4 cache node, etc.)

ok, will go look.

- k

Re: [PATCH] [POWERPC] Cleanup mpic nodes in .dts

[Kumar Gala]

On May 30, 2008, at 4:42 PM, Segher Boessenkool wrote:

>> Removed clock-frequency and big-endian props as they aren't specified
>> anywhere.
>
> If you remove "big-endian", you'll have to provide some other way
> to get that information (like, some new "compatible" value).

I'm all for "big-endian" but we don't spec this anywhere and aren't  
using it right now.  So until we have an real need to start an  
extended mpic definition I'm getting rid of it.

> Dunno if we need "clock-frequency".

Not used today.

> This patch also removes "built-in" properties.  I'm all for that,
> but the patch description didn't say it does.
>
will add that to the commit message.

- k

Re: [PATCH] [POWERPC] Cleanup mpic nodes in .dts

[Segher Boessenkool]

>>> Removed clock-frequency and big-endian props as they aren't specified
>>> anywhere.
>>
>> If you remove "big-endian", you'll have to provide some other way
>> to get that information (like, some new "compatible" value).
>
> I'm all for "big-endian" but we don't spec this anywhere and aren't 
> using it right now.  So until we have an real need to start an 
> extended mpic definition I'm getting rid of it.

If we would remove everything insufficiently documented, not much would
be left.  This doesn't seem very productive to me.  Could you instead
just add some TODO somewhere?

>> Dunno if we need "clock-frequency".
>
> Not used today.

Sure, the kernel might not use it today, but that's no reason to remove
stuff from the device tree.

I'm not against removing "clock-frequency" though, it's not 
well-defined,
and what would it be useful for anyway?

>> This patch also removes "built-in" properties.  I'm all for that,
>> but the patch description didn't say it does.
>>
> will add that to the commit message.

Thanks.


Segher

Re: [PATCH] [POWERPC] 85xx: Add next-level-cache property

[Kumar Gala]

On May 30, 2008, at 4:49 PM, Segher Boessenkool wrote:

>> Added next-level-cache to the L1 and a reference to the new L2 label.
>
> Where is this property defined?  I can't find it.
>
> The PowerPC binding defines an "l2-cache" property for this (it
> points from CPU node to L2 cache node, from L2 cache node to L3
> cache node, from L3 cache node to L4 cache node, etc.)

So looking at the PPC binding its not terrible clear about "l3-cache"  
being a valid property.  I believe the discussion w/ePAPR was to  
create something a bit more generic and clarify/update the PPC binding.

I'm going to stick with the new binding as we don't use this linking  
currently.

- k

Re: [PATCH] [POWERPC] 85xx: Add next-level-cache property

[Segher Boessenkool]

>>> Added next-level-cache to the L1 and a reference to the new L2 label.
>>
>> Where is this property defined?  I can't find it.
>>
>> The PowerPC binding defines an "l2-cache" property for this (it
>> points from CPU node to L2 cache node, from L2 cache node to L3
>> cache node, from L3 cache node to L4 cache node, etc.)
>
> So looking at the PPC binding its not terrible clear about "l3-cache" 
> being a valid property.

It isn't.  The property is called "l2-cache" at every level.

> I believe the discussion w/ePAPR was to create something a bit more 
> generic and clarify/update the PPC binding.

Nasty.  Sure, "l2-cache" isn't the nicest name to point to deeper
cache levels, but introducing a new property with (substantially)
the same semantics is worse.

There really shouldn't be a new property name until new functionality
is introduced.  For example, it could allow to describe more than one
cache at each level (the current binding already allows more than one
parent for each cache, but only one child; and cache hierarchies like
that actually exist).

> I'm going to stick with the new binding as we don't use this linking 
> currently.

Dunno what's the best thing to do here.  If you don't need the
functionality yet, it might be best to postpone putting either
property in there.  Sigh, what a mess.


Segher

Re: [PATCH] [POWERPC] 85xx: Add next-level-cache property

[Nathan Lynch]

Segher Boessenkool wrote:
>>>
>>> The PowerPC binding defines an "l2-cache" property for this (it
>>> points from CPU node to L2 cache node, from L2 cache node to L3
>>> cache node, from L3 cache node to L4 cache node, etc.)
>>
>> So looking at the PPC binding its not terrible clear about "l3-cache"  
>> being a valid property.
>
> It isn't.  The property is called "l2-cache" at every level.
>
>> I believe the discussion w/ePAPR was to create something a bit more  
>> generic and clarify/update the PPC binding.
>
> Nasty.  Sure, "l2-cache" isn't the nicest name to point to deeper
> cache levels, but introducing a new property with (substantially)
> the same semantics is worse.

The semantics appear to be identical, even.


> There really shouldn't be a new property name until new functionality
> is introduced.  For example, it could allow to describe more than one
> cache at each level (the current binding already allows more than one
> parent for each cache, but only one child; and cache hierarchies like
> that actually exist).
>
>> I'm going to stick with the new binding as we don't use this linking  
>> currently.
>
> Dunno what's the best thing to do here.  If you don't need the
> functionality yet, it might be best to postpone putting either
> property in there.  Sigh, what a mess.

Does existing practice count for anything?  IBM pseries firmware uses
the l2-cache property as described in the PowerPC binding.

Re: [PATCH] [POWERPC] 85xx: Add next-level-cache property

[Kumar Gala]

On Jun 2, 2008, at 4:26 PM, Nathan Lynch wrote:

> Segher Boessenkool wrote:
>>>>
>>>> The PowerPC binding defines an "l2-cache" property for this (it
>>>> points from CPU node to L2 cache node, from L2 cache node to L3
>>>> cache node, from L3 cache node to L4 cache node, etc.)
>>>
>>> So looking at the PPC binding its not terrible clear about "l3- 
>>> cache"
>>> being a valid property.
>>
>> It isn't.  The property is called "l2-cache" at every level.
>>
>>> I believe the discussion w/ePAPR was to create something a bit more
>>> generic and clarify/update the PPC binding.
>>
>> Nasty.  Sure, "l2-cache" isn't the nicest name to point to deeper
>> cache levels, but introducing a new property with (substantially)
>> the same semantics is worse.
>
> The semantics appear to be identical, even.
>
>
>> There really shouldn't be a new property name until new functionality
>> is introduced.  For example, it could allow to describe more than one
>> cache at each level (the current binding already allows more than one
>> parent for each cache, but only one child; and cache hierarchies like
>> that actually exist).
>>
>>> I'm going to stick with the new binding as we don't use this linking
>>> currently.
>>
>> Dunno what's the best thing to do here.  If you don't need the
>> functionality yet, it might be best to postpone putting either
>> property in there.  Sigh, what a mess.
>
> Does existing practice count for anything?  IBM pseries firmware uses
> the l2-cache property as described in the PowerPC binding.

The ePAPR does suggest to implement l2-cache for SW compat.  If there  
is strong enough feeling we can support both but I'm sticking w/what's  
in ePAPR for 85xx as its just slightly more sane.

- k

Re: [PATCH] [POWERPC] Cleanup mpic nodes in .dts

[Kumar Gala]

On Jun 2, 2008, at 11:32 AM, Segher Boessenkool wrote:

>>>> Removed clock-frequency and big-endian props as they aren't  
>>>> specified
>>>> anywhere.
>>>
>>> If you remove "big-endian", you'll have to provide some other way
>>> to get that information (like, some new "compatible" value).
>>
>> I'm all for "big-endian" but we don't spec this anywhere and aren't  
>> using it right now.  So until we have an real need to start an  
>> extended mpic definition I'm getting rid of it.
>
> If we would remove everything insufficiently documented, not much  
> would
> be left.  This doesn't seem very productive to me.  Could you instead
> just add some TODO somewhere?

we were already inconsistent here so I've made all things equal and  
baselined.

>>> Dunno if we need "clock-frequency".
>>
>> Not used today.
>
> Sure, the kernel might not use it today, but that's no reason to  
> remove
> stuff from the device tree.
>
> I'm not against removing "clock-frequency" though, it's not well- 
> defined,
> and what would it be useful for anyway?

As Scott pointed it it could be used for the frequency of the timers  
that exist in OpenPIC.

>>> This patch also removes "built-in" properties.  I'm all for that,
>>> but the patch description didn't say it does.
>>>
>> will add that to the commit message.
>
> Thanks.

I'm sticking to removing the cruft and if/when we need it some can add  
it properly.

- k