From: Dan Malek <dan@embeddedalley.com>
To: Kalle Pokki <kalle.pokki@iki.fi>
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: CPM2 early console
Date: Tue, 27 Sep 2005 16:48:21 -0400 [thread overview]
Message-ID: <714c16295fbfa97caafd1d0aa3a5932e@embeddedalley.com> (raw)
In-Reply-To: <4339AD01.30708@iki.fi>
On Sep 27, 2005, at 4:35 PM, Kalle Pokki wrote:
> OK. Then the question really is why isn't the cache controller
> enforcing coherency between the G2_LE core and the CPM.
Is the GBL and DTB set properly in the function code registers
of the SCC parameter ram?
-- Dan
next prev parent reply other threads:[~2005-09-27 20:48 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-09-22 16:02 CPM2 early console Rune Torgersen
2005-09-22 16:05 ` Kumar Gala
2005-09-23 10:55 ` Kalle Pokki
2005-09-27 14:11 ` Kalle Pokki
2005-09-27 16:39 ` Dan Malek
2005-09-27 20:35 ` Kalle Pokki
2005-09-27 20:48 ` Dan Malek [this message]
2005-09-28 10:20 ` Kalle Pokki
2005-09-29 12:24 ` Kalle Pokki
2005-09-29 12:50 ` Dan Malek
2005-09-30 13:22 ` Alex Zeffertt
2005-09-30 13:42 ` Alex Zeffertt
2005-09-30 20:16 ` Kalle Pokki
2005-09-30 13:58 ` Dan Malek
2005-09-30 20:10 ` Kalle Pokki
2005-09-30 20:28 ` Dan Malek
2005-10-01 5:57 ` Kalle Pokki
2005-10-01 8:24 ` Roger Larsson
2005-10-02 16:59 ` Dan Malek
2005-10-03 7:04 ` Kalle Pokki
2005-10-04 8:13 ` Kalle Pokki
2005-10-04 9:59 ` Alex Zeffertt
2005-10-04 10:16 ` Kalle Pokki
2005-10-04 16:04 ` Dan Malek
-- strict thread matches above, loose matches on Subject: below --
2005-09-22 13:11 Kalle Pokki
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