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From: Dan Malek <dan@embeddedalley.com>
Date: Tue, 27 Sep 2005 16:48:21 -0400
To: Kalle Pokki <kalle.pokki@iki.fi>
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: CPM2 early console
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On Sep 27, 2005, at 4:35 PM, Kalle Pokki wrote:

> OK. Then the question really is why isn't the cache controller 
> enforcing coherency between the G2_LE core and the CPM.

Is the GBL and DTB set properly in the function code registers
of the SCC parameter ram?


	-- Dan