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Tue, 29 Mar 2022 15:59:03 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.5.0-alpha0-4911-g925b585eab-fm-20220323.003-g925b585e Mime-Version: 1.0 Message-Id: <74a36bce-3d6e-4124-add1-8ed44ba2c80d@www.fastmail.com> In-Reply-To: <20220329183817.21656-1-povik+lin@cutebit.org> References: <20220329183817.21656-1-povik+lin@cutebit.org> Date: Tue, 29 Mar 2022 21:58:43 +0200 From: "Sven Peter" To: =?UTF-8?Q?Martin_Povi=C5=A1er?= , "Hector Martin" , "Michael Ellerman" Subject: Re: [PATCH] i2c: pasemi: Wait for write xfers to finish Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, Olof Johansson , Paul Mackerras , Alyssa Rosenzweig , Jean Delvare , Janne Grunau , linuxppc-dev , linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tue, Mar 29, 2022, at 20:38, Martin Povi=C5=A1er wrote: > Wait for completion of write transfers before returning from the drive= r. > At first sight it may seem advantageous to leave write transfers queued > for the controller to carry out on its own time, but there's a couple = of > issues with it: > > * Driver doesn't check for FIFO space. Maybe we should also check that in a follow-up patch :-) > > * The queued writes can complete while the driver is in its I2C read > transfer path which means it will get confused by the raising of > XEN (the 'transaction ended' signal). This can cause a spurious > ENODATA error due to premature reading of the MRXFIFO register. > > Adding the wait fixes some unreliability issues with the driver. There= 's > some efficiency cost to it (especially with pasemi_smb_waitready doing > its polling), but that will be alleviated once the driver receives > interrupt support. > > Fixes: beb58aa39e6e ("i2c: PA Semi SMBus driver") > Signed-off-by: Martin Povi=C5=A1er > --- Reviewed-by: Sven Peter > > Tested on Apple's t8103 chip. To my knowledge the PA Semi controller > in its pre-Apple occurences behaves the same as far as this patch is > concerned. > > drivers/i2c/busses/i2c-pasemi-core.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/i2c/busses/i2c-pasemi-core.c=20 > b/drivers/i2c/busses/i2c-pasemi-core.c > index 7728c8460dc0..9028ffb58cc0 100644 > --- a/drivers/i2c/busses/i2c-pasemi-core.c > +++ b/drivers/i2c/busses/i2c-pasemi-core.c > @@ -137,6 +137,12 @@ static int pasemi_i2c_xfer_msg(struct i2c_adapter=20 > *adapter, >=20 > TXFIFO_WR(smbus, msg->buf[msg->len-1] | > (stop ? MTXFIFO_STOP : 0)); > + > + if (stop) { > + err =3D pasemi_smb_waitready(smbus); > + if (err) > + goto reset_out; > + } Looks like pasemi_smb_xfer doesn't suffer from the same issue. I wonder if every device connected to the bus on the original PA Semi bo= ards only used that path and that's why no one noticed it. Sven