From: "Ed Goforth" <egoforth@gmail.com>
To: "Ed Goforth" <egoforth@gmail.com>, linuxppc-embedded@ozlabs.org
Subject: Re: 440gx GPIO
Date: Mon, 20 Feb 2006 12:20:33 -0500 [thread overview]
Message-ID: <75b39f010602200920x403312c7ye0088301602b7e23@mail.gmail.com> (raw)
In-Reply-To: <20060214170140.GB12465@gate.ebshome.net>
On 2/14/06, Eugene Surovegin <ebs@ebshome.net> wrote:
>
> Try writing the same GPIO output register value as you read from it
> (without clearing bit 11). Also, try changing some other GPIO bit
> (e.g. one which is not connected in your design). Maybe board hangs
> exactly because you set GPIO bit 11 low :).
Bingo! The board wasn't actually hanging. When we set GPIO11 low, it
is supposed to reset our on-board FPGAs. One of the FPGAs controls a
TX disable signal. And the (current) default on a reset is to leave
the TX disable low, hence no network after a FPGA reset. Doesn't work
well with a NFS root :)
>
> Also, connect scope to that GPIO pin and see what is really going on.
>
> --
> Eugene
next prev parent reply other threads:[~2006-02-20 17:20 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-02-14 5:20 440gx GPIO Ed Goforth
2006-02-14 6:59 ` Eugene Surovegin
2006-02-14 13:48 ` Ed Goforth
2006-02-14 17:01 ` Eugene Surovegin
2006-02-14 17:10 ` Ed Goforth
2006-02-14 21:47 ` Ed Goforth
2006-02-20 17:20 ` Ed Goforth [this message]
-- strict thread matches above, loose matches on Subject: below --
2006-02-15 0:01 Howard, Marc
2006-02-20 17:13 ` Ed Goforth
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