From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40fqBF3z87zF13r for ; Tue, 8 May 2018 03:20:05 +1000 (AEST) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w47HJQul019907 for ; Mon, 7 May 2018 13:20:03 -0400 Received: from e06smtp15.uk.ibm.com (e06smtp15.uk.ibm.com [195.75.94.111]) by mx0a-001b2d01.pphosted.com with ESMTP id 2htqdv2jth-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 07 May 2018 13:20:02 -0400 Received: from localhost by e06smtp15.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 7 May 2018 18:20:00 +0100 Subject: Re: [PATCH v2 2/7] powerpc: Use TIDR CPU feature to control TIDR allocation To: "Alastair D'Silva" , linuxppc-dev@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, mikey@neuling.org, vaibhav@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com, malat@debian.org, felix@linux.vnet.ibm.com, pombredanne@nexb.com, sukadev@linux.vnet.ibm.com, npiggin@gmail.com, gregkh@linuxfoundation.org, arnd@arndb.de, andrew.donnellan@au1.ibm.com, fbarrat@linux.vnet.ibm.com, corbet@lwn.net, "Alastair D'Silva" References: <20180417020950.21446-1-alastair@au1.ibm.com> <20180418010810.30937-1-alastair@au1.ibm.com> <20180418010810.30937-3-alastair@au1.ibm.com> From: Frederic Barrat Date: Mon, 7 May 2018 19:19:53 +0200 MIME-Version: 1.0 In-Reply-To: <20180418010810.30937-3-alastair@au1.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Message-Id: <772d6e5d-54c2-0512-b8e6-21d12d8c44cc@linux.ibm.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : > From: Alastair D'Silva > > Switch the use of TIDR on it's CPU feature, rather than assuming it > is available based on architecture. > > Signed-off-by: Alastair D'Silva > --- Reviewed-by: Frederic Barrat > arch/powerpc/kernel/process.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c > index 1237f13fed51..3b00da47699b 100644 > --- a/arch/powerpc/kernel/process.c > +++ b/arch/powerpc/kernel/process.c > @@ -1154,7 +1154,7 @@ static inline void restore_sprs(struct thread_struct *old_thread, > mtspr(SPRN_TAR, new_thread->tar); > } > > - if (cpu_has_feature(CPU_FTR_ARCH_300) && > + if (cpu_has_feature(CPU_FTR_P9_TIDR) && > old_thread->tidr != new_thread->tidr) > mtspr(SPRN_TIDR, new_thread->tidr); > #endif > @@ -1570,7 +1570,7 @@ void clear_thread_tidr(struct task_struct *t) > if (!t->thread.tidr) > return; > > - if (!cpu_has_feature(CPU_FTR_ARCH_300)) { > + if (!cpu_has_feature(CPU_FTR_P9_TIDR)) { > WARN_ON_ONCE(1); > return; > } > @@ -1593,7 +1593,7 @@ int set_thread_tidr(struct task_struct *t) > { > int rc; > > - if (!cpu_has_feature(CPU_FTR_ARCH_300)) > + if (!cpu_has_feature(CPU_FTR_P9_TIDR)) > return -EINVAL; > > if (t != current) >