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Thu, 15 Sep 2022 05:47:08 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 41E8CA405F; Thu, 15 Sep 2022 05:47:08 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E132DA4054; Thu, 15 Sep 2022 05:47:07 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 15 Sep 2022 05:47:07 +0000 (GMT) Received: from smtpclient.apple (unknown [9.192.255.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 3530B6016C; Thu, 15 Sep 2022 15:47:05 +1000 (AEST) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3696.120.41.1.1\)) Subject: Re: [PATCH v4 11/20] powerpc: Add ZEROIZE_GPRS macros for register clears From: Rohan McLure In-Reply-To: Date: Thu, 15 Sep 2022 15:47:04 +1000 Content-Transfer-Encoding: quoted-printable Message-Id: <79671045-7D84-4454-B835-346A3F4F175B@linux.ibm.com> References: <20220824020548.62625-1-rmclure@linux.ibm.com> <20220824020548.62625-12-rmclure@linux.ibm.com> To: Nicholas Piggin X-Mailer: Apple Mail (2.3696.120.41.1.1) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: TmYWebuEPqLgFzi3UvYxng_GI_WYYD1N X-Proofpoint-ORIG-GUID: 8rs7Gk_OaI20sBhrpw79aErwWDbBtQfD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-15_02,2022-09-14_04,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 mlxscore=0 phishscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 bulkscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2208220000 definitions=main-2209150028 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" > On 12 Sep 2022, at 9:09 pm, Nicholas Piggin wrote: >=20 > On Wed Aug 24, 2022 at 12:05 PM AEST, Rohan McLure wrote: >> Macros for restoring and saving registers to and from the stack = exist. >> Provide macros with the same interface for clearing a range of gprs = by >> setting each register's value in that range to zero. >=20 > Can I bikeshed this a bit more and ask if you would change the order? >=20 > Saving and restoring macros are incidental, and are neither the change > nor the reson for it. I think the changelog reads better if you state > the change (or the problem) up front. >=20 > Provid register zeroing macros ... follow the same convention as > existing register stack save/restore macros ... will be used in later > change to zero registers. Thanks for the suggestion, that should read better. >=20 > Or not, if you disagree. >=20 > Reviewed-by: Nicholas Piggin >=20 >> The resulting macros are called ZEROIZE_GPRS and ZEROIZE_NVGPRS, = keeping >> with the naming of the accompanying restore and save macros, and = usage >> of zeroize to describe this operation elsewhere in the kernel. >>=20 >> Signed-off-by: Rohan McLure >> --- >> V1 -> V2: Change 'ZERO' usage in naming to 'NULLIFY', a more obvious = verb >> V2 -> V3: Change 'NULLIFY' usage in naming to 'ZEROIZE', which has >> precedent in kernel and explicitly specifies that we are zeroing. >> V3 -> V4: Update commit message to use zeroize. >> --- >> arch/powerpc/include/asm/ppc_asm.h | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >>=20 >> diff --git a/arch/powerpc/include/asm/ppc_asm.h = b/arch/powerpc/include/asm/ppc_asm.h >> index 83c02f5a7f2a..b95689ada59c 100644 >> --- a/arch/powerpc/include/asm/ppc_asm.h >> +++ b/arch/powerpc/include/asm/ppc_asm.h >> @@ -33,6 +33,20 @@ >> .endr >> .endm >>=20 >> +/* >> + * This expands to a sequence of register clears for regs start to = end >> + * inclusive, of the form: >> + * >> + * li rN, 0 >> + */ >> +.macro ZEROIZE_REGS start, end >> + .Lreg=3D\start >> + .rept (\end - \start + 1) >> + li .Lreg, 0 >> + .Lreg=3D.Lreg+1 >> + .endr >> +.endm >> + >> /* >> * Macros for storing registers into and loading registers from >> * exception frames. >> @@ -49,6 +63,14 @@ >> #define REST_NVGPRS(base) REST_GPRS(13, 31, base) >> #endif >>=20 >> +#define ZEROIZE_GPRS(start, end) ZEROIZE_REGS start, end >> +#ifdef __powerpc64__ >> +#define ZEROIZE_NVGPRS() ZEROIZE_GPRS(14, 31) >> +#else >> +#define ZEROIZE_NVGPRS() ZEROIZE_GPRS(13, 31) >> +#endif >> +#define ZEROIZE_GPR(n) ZEROIZE_GPRS(n, n) >> + >> #define SAVE_GPR(n, base) SAVE_GPRS(n, n, base) >> #define REST_GPR(n, base) REST_GPRS(n, n, base) >>=20 >> --=20 >> 2.34.1 >=20