RE: Xilinx LLTEMAC driver issues

RE: Xilinx LLTEMAC driver issues

[John Linn]

Hi Magnus,

Sorry to hear you're having problems with it.

I am doing testing on an ML405 which is the same board but with a bigger =
FPGA, but with ppc arch and I don't see this issue. I have done limited =
testing with powerpc arch and the LL TEMAC, but I didn't see this issue =
there either.  Powerpc arch is definitely less mature in my experience =
than the ppc arch. I'll do a quick test with my powerpc arch and make =
sure again I'm not seeing it.

My kernel is from the Xilinx Git tree, but there have been a number of =
changes we have pushed out so I don't know how long ago you pulled from =
the Git tree.

My EDK project is 10.1 so it's a little newer. I am using LL TEMAC 1.01a =
so it's a little newer.  I reviewed the change log for the LL TEMAC and =
don't see any big problems that were fixed in the newer versions, more =
new features.  I'll check with some others here to see if I missed =
something there.

I am using DMA also, but no DRE or checksum offload.  You didn't say =
anything about those. I'm going to insert my mhs file that describes my =
system to let you compare your system configuration. It's not clear to =
me yet if you have a h/w or s/w problem. =20

I'll also insert some of my device tree with the LL TEMAC so you can =
compare (ignore 16550 stuff as we are still working on that).

Since you can't ping reliably I would probably focus on that since it's =
simpler than the other issues you're seeing.

Thanks,
John



# =
#########################################################################=
#####
# Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build =
EDK_K_SP1.1
# Thu Feb 14 14:11:12 2008
# Target Board:  Xilinx Virtex 4 ML405 Evaluation Platform Rev 1
# Family:    virtex4
# Device:    xc4vfx20
# Package:   ff672
# Speed Grade:  -10
# Processor: ppc405_0
# Processor clock frequency: 300.00 MHz
# Bus clock frequency: 100.00 MHz
# On Chip Memory :   8 KB
# Total Off Chip Memory : 128 MB
# - DDR_SDRAM =3D 128 MB
# =
#########################################################################=
#####
 PARAMETER VERSION =3D 2.1.0


 PORT fpga_0_RS232_Uart_sin_pin =3D fpga_0_RS232_Uart_sin, DIR =3D I
 PORT fpga_0_RS232_Uart_sout_pin =3D fpga_0_RS232_Uart_sout, DIR =3D O
 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin =3D fpga_0_LEDs_4Bit_GPIO_IO, DIR =3D =
IO, VEC =3D [0:3]
 PORT fpga_0_IIC_EEPROM_Scl_pin =3D fpga_0_IIC_EEPROM_Scl, DIR =3D IO
 PORT fpga_0_IIC_EEPROM_Sda_pin =3D fpga_0_IIC_EEPROM_Sda, DIR =3D IO
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR =3D I
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR =3D O, VEC =3D [6:1]
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR =3D IO, VEC =3D [15:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR =3D O
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR =3D O
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR =3D O
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR =3D I
 PORT fpga_0_DDR_SDRAM_DDR_Clk_pin =3D fpga_0_DDR_SDRAM_DDR_Clk, DIR =3D =
O
 PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin =3D fpga_0_DDR_SDRAM_DDR_Clk_n, DIR =
=3D O
 PORT fpga_0_DDR_SDRAM_DDR_Addr_pin =3D fpga_0_DDR_SDRAM_DDR_Addr, DIR =
=3D O, VEC =3D [12:0]
 PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =3D =
fpga_0_DDR_SDRAM_DDR_BankAddr, DIR =3D O, VEC =3D [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin =3D fpga_0_DDR_SDRAM_DDR_CAS_n, DIR =
=3D O
 PORT fpga_0_DDR_SDRAM_DDR_CE_pin =3D fpga_0_DDR_SDRAM_DDR_CE, DIR =3D O
 PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin =3D fpga_0_DDR_SDRAM_DDR_CS_n, DIR =
=3D O
 PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin =3D fpga_0_DDR_SDRAM_DDR_RAS_n, DIR =
=3D O
 PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin =3D fpga_0_DDR_SDRAM_DDR_WE_n, DIR =
=3D O
 PORT fpga_0_DDR_SDRAM_DDR_DM_pin =3D fpga_0_DDR_SDRAM_DDR_DM, DIR =3D =
O, VEC =3D [3:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQS =3D fpga_0_DDR_SDRAM_DDR_DQS, DIR =3D IO, =
VEC =3D [3:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQ =3D fpga_0_DDR_SDRAM_DDR_DQ, DIR =3D IO, =
VEC =3D [31:0]
 PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR =3D O, VEC =3D [7:0]
 PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR =3D O
 PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR =3D O
 PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR =3D O
 PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR =3D I, VEC =3D [7:0]
 PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR =3D I
 PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR =3D I
 PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR =3D I
 PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin =3D =
fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR =3D I
 PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin =3D =
fpga_0_TriMode_MAC_GMII_MDIO_0, DIR =3D IO
 PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin =3D =
fpga_0_TriMode_MAC_GMII_MDC_0, DIR =3D O
 PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin =3D =
fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR =3D O
 PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D CLK, CLK_FREQ =3D =
100000000
 PORT sys_rst_pin =3D sys_rst_s, DIR =3D I, RST_POLARITY =3D 0, SIGIS =
=3D RST


BEGIN ppc405_virtex4
 PARAMETER INSTANCE =3D ppc405_0
 PARAMETER HW_VER =3D 2.01.a
 PARAMETER C_FASTEST_PLB_CLOCK =3D DPLB1
 PARAMETER C_IDCR_BASEADDR =3D 0b0100000000
 PARAMETER C_IDCR_HIGHADDR =3D 0b0111111111
 BUS_INTERFACE JTAGPPC =3D jtagppc_0_0
 BUS_INTERFACE IPLB0 =3D plb
 BUS_INTERFACE DPLB0 =3D plb
 BUS_INTERFACE IPLB1 =3D ppc405_0_iplb1
 BUS_INTERFACE DPLB1 =3D ppc405_0_dplb1
 BUS_INTERFACE RESETPPC =3D ppc_reset_bus
 PORT CPMC405CLOCK =3D proc_clk_s
 PORT EICC405EXTINPUTIRQ =3D EICC405EXTINPUTIRQ
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE =3D jtagppc_0
 PARAMETER HW_VER =3D 2.01.a
 BUS_INTERFACE JTAGPPC0 =3D jtagppc_0_0
END

BEGIN plb_v46
 PARAMETER INSTANCE =3D plb
 PARAMETER C_DCR_INTFCE =3D 0
 PARAMETER C_NUM_CLK_PLB2OPB_REARB =3D 100
 PARAMETER HW_VER =3D 1.02.a
 PORT PLB_Clk =3D sys_clk_s
 PORT SYS_Rst =3D sys_bus_reset
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE =3D xps_bram_if_cntlr_1
 PARAMETER HW_VER =3D 1.00.a
 PARAMETER C_SPLB_NATIVE_DWIDTH =3D 64
 PARAMETER C_BASEADDR =3D 0xffffe000
 PARAMETER C_HIGHADDR =3D 0xffffffff
 BUS_INTERFACE SPLB =3D plb
 BUS_INTERFACE PORTA =3D xps_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE =3D plb_bram_if_cntlr_1_bram
 PARAMETER HW_VER =3D 1.00.a
 BUS_INTERFACE PORTA =3D xps_bram_if_cntlr_1_port
END

BEGIN xps_uart16550
 PARAMETER INSTANCE =3D RS232_Uart
 PARAMETER HW_VER =3D 2.00.a
 PARAMETER C_IS_A_16550 =3D 1
 PARAMETER C_BASEADDR =3D 0x83e00000
 PARAMETER C_HIGHADDR =3D 0x83e0ffff
 BUS_INTERFACE SPLB =3D plb
 PORT sin =3D fpga_0_RS232_Uart_sin
 PORT sout =3D fpga_0_RS232_Uart_sout
 PORT IP2INTC_Irpt =3D RS232_Uart_IP2INTC_Irpt
END

BEGIN xps_gpio
 PARAMETER INSTANCE =3D LEDs_4Bit
 PARAMETER HW_VER =3D 1.00.a
 PARAMETER C_INTERRUPT_PRESENT =3D 1
 PARAMETER C_GPIO_WIDTH =3D 4
 PARAMETER C_IS_DUAL =3D 0
 PARAMETER C_IS_BIDIR =3D 1
 PARAMETER C_ALL_INPUTS =3D 0
 PARAMETER C_BASEADDR =3D 0x81400000
 PARAMETER C_HIGHADDR =3D 0x8140ffff
 BUS_INTERFACE SPLB =3D plb
 PORT GPIO_IO =3D fpga_0_LEDs_4Bit_GPIO_IO
 PORT IP2INTC_Irpt =3D LEDs_4Bit_IP2INTC_Irpt
END

BEGIN xps_iic
 PARAMETER INSTANCE =3D IIC_EEPROM
 PARAMETER HW_VER =3D 2.00.a
 PARAMETER C_CLK_FREQ =3D 100000000
 PARAMETER C_IIC_FREQ =3D 100000
 PARAMETER C_TEN_BIT_ADR =3D 0
 PARAMETER C_BASEADDR =3D 0x81600000
 PARAMETER C_HIGHADDR =3D 0x8160ffff
 BUS_INTERFACE SPLB =3D plb
 PORT Scl =3D fpga_0_IIC_EEPROM_Scl
 PORT Sda =3D fpga_0_IIC_EEPROM_Sda
 PORT IIC2INTC_Irpt =3D IIC_EEPROM_IIC2INTC_Irpt
END

BEGIN xps_sysace
 PARAMETER INSTANCE =3D SysACE_CompactFlash
 PARAMETER HW_VER =3D 1.00.a
 PARAMETER C_MEM_WIDTH =3D 16
 PARAMETER C_BASEADDR =3D 0x83600000
 PARAMETER C_HIGHADDR =3D 0x8360ffff
 BUS_INTERFACE SPLB =3D plb
 PORT SysACE_CLK =3D fpga_0_SysACE_CompactFlash_SysACE_CLK
 PORT SysACE_MPA =3D fpga_0_SysACE_CompactFlash_SysACE_MPA_split
 PORT SysACE_MPD =3D fpga_0_SysACE_CompactFlash_SysACE_MPD
 PORT SysACE_CEN =3D fpga_0_SysACE_CompactFlash_SysACE_CEN
 PORT SysACE_OEN =3D fpga_0_SysACE_CompactFlash_SysACE_OEN
 PORT SysACE_WEN =3D fpga_0_SysACE_CompactFlash_SysACE_WEN
 PORT SysACE_MPIRQ =3D fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
 PORT SysACE_IRQ =3D SysACE_CompactFlash_SysACE_IRQ
END

BEGIN mpmc
 PARAMETER INSTANCE =3D DDR_SDRAM
 PARAMETER HW_VER =3D 4.00.a
 PARAMETER C_NUM_PORTS =3D 3
 PARAMETER C_MEM_PARTNO =3D HYB25D512160BE-5
 PARAMETER C_MEM_DATA_WIDTH =3D 32
 PARAMETER C_MEM_DQS_WIDTH =3D 4
 PARAMETER C_MEM_DM_WIDTH =3D 4
 PARAMETER C_MEM_TYPE =3D DDR
 PARAMETER C_NUM_IDELAYCTRL =3D 2
 PARAMETER C_IDELAYCTRL_LOC =3D IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
 PARAMETER C_PIM0_BASETYPE =3D 2
 PARAMETER C_PIM1_BASETYPE =3D 2
 PARAMETER C_PIM2_BASETYPE =3D 3
 PARAMETER C_MPMC_CLK0_PERIOD_PS =3D 10000
 PARAMETER C_SDMA2_PI2LL_CLK_RATIO =3D 1
 PARAMETER C_MPMC_BASEADDR =3D 0x00000000
 PARAMETER C_MPMC_HIGHADDR =3D 0x07ffffff
 PARAMETER C_SDMA_CTRL_BASEADDR =3D 0x84600000
 PARAMETER C_SDMA_CTRL_HIGHADDR =3D 0x8460ffff
 BUS_INTERFACE SPLB0 =3D ppc405_0_iplb1
 BUS_INTERFACE SPLB1 =3D ppc405_0_dplb1
 BUS_INTERFACE SDMA_LL2 =3D TriMode_MAC_GMII_LLINK0
 BUS_INTERFACE SDMA_CTRL2 =3D plb
 PORT DDR_Addr =3D fpga_0_DDR_SDRAM_DDR_Addr
 PORT DDR_BankAddr =3D fpga_0_DDR_SDRAM_DDR_BankAddr
 PORT DDR_CAS_n =3D fpga_0_DDR_SDRAM_DDR_CAS_n
 PORT DDR_CE =3D fpga_0_DDR_SDRAM_DDR_CE
 PORT DDR_CS_n =3D fpga_0_DDR_SDRAM_DDR_CS_n
 PORT DDR_RAS_n =3D fpga_0_DDR_SDRAM_DDR_RAS_n
 PORT DDR_WE_n =3D fpga_0_DDR_SDRAM_DDR_WE_n
 PORT DDR_DM =3D fpga_0_DDR_SDRAM_DDR_DM
 PORT DDR_DQS =3D fpga_0_DDR_SDRAM_DDR_DQS
 PORT DDR_DQ =3D fpga_0_DDR_SDRAM_DDR_DQ
 PORT DDR_Clk =3D fpga_0_DDR_SDRAM_DDR_Clk
 PORT DDR_Clk_n =3D fpga_0_DDR_SDRAM_DDR_Clk_n
 PORT MPMC_Clk0 =3D sys_clk_s
 PORT MPMC_Clk90 =3D DDR_SDRAM_mpmc_clk_90_s
 PORT SDMA2_Clk =3D sys_clk_s
 PORT MPMC_Clk_200MHz =3D clk_200mhz_s
 PORT MPMC_Rst =3D sys_periph_reset
 PORT SDMA2_Rx_IntOut =3D DDR_SDRAM_SDMA2_Rx_IntOut
 PORT SDMA2_Tx_IntOut =3D DDR_SDRAM_SDMA2_Tx_IntOut
END

BEGIN xps_ll_temac
 PARAMETER INSTANCE =3D TriMode_MAC_GMII
 PARAMETER HW_VER =3D 1.01.a
 PARAMETER C_SPLB_CLK_PERIOD_PS =3D 10000
 PARAMETER C_PHY_TYPE =3D 1
 PARAMETER C_NUM_IDELAYCTRL =3D 4
 PARAMETER C_IDELAYCTRL_LOC =3D =
IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3
 PARAMETER C_TEMAC_TYPE =3D 1
 PARAMETER C_BUS2CORE_CLK_RATIO =3D 1
 PARAMETER C_BASEADDR =3D 0x81c00000
 PARAMETER C_HIGHADDR =3D 0x81c0ffff
 BUS_INTERFACE SPLB =3D plb
 BUS_INTERFACE LLINK0 =3D TriMode_MAC_GMII_LLINK0
 PORT GMII_TXD_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TXD_0
 PORT GMII_TX_EN_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0
 PORT GMII_TX_ER_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0
 PORT GMII_TX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0
 PORT GMII_RXD_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RXD_0
 PORT GMII_RX_DV_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0
 PORT GMII_RX_ER_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0
 PORT GMII_RX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0
 PORT MII_TX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0
 PORT MDIO_0 =3D fpga_0_TriMode_MAC_GMII_MDIO_0
 PORT MDC_0 =3D fpga_0_TriMode_MAC_GMII_MDC_0
 PORT TemacPhy_RST_n =3D fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n
 PORT GTX_CLK_0 =3D temac_clk_s
 PORT REFCLK =3D clk_200mhz_s
 PORT LlinkTemac0_CLK =3D sys_clk_s
 PORT TemacIntc0_Irpt =3D TriMode_MAC_GMII_TemacIntc0_Irpt
END

BEGIN util_bus_split
 PARAMETER INSTANCE =3D SysACE_CompactFlash_util_bus_split_0
 PARAMETER HW_VER =3D 1.00.a
 PARAMETER C_SIZE_IN =3D 7
 PARAMETER C_LEFT_POS =3D 0
 PARAMETER C_SPLIT =3D 6
 PORT Sig =3D fpga_0_SysACE_CompactFlash_SysACE_MPA_split
 PORT Out1 =3D fpga_0_SysACE_CompactFlash_SysACE_MPA
END

BEGIN plb_v46
 PARAMETER INSTANCE =3D ppc405_0_iplb1
 PARAMETER HW_VER =3D 1.02.a
 PORT PLB_Clk =3D sys_clk_s
 PORT SYS_Rst =3D sys_bus_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE =3D ppc405_0_dplb1
 PARAMETER HW_VER =3D 1.02.a
 PORT PLB_Clk =3D sys_clk_s
 PORT SYS_Rst =3D sys_bus_reset
END

BEGIN clock_generator
 PARAMETER INSTANCE =3D clock_generator_0
 PARAMETER HW_VER =3D 2.00.a
 PARAMETER C_EXT_RESET_HIGH =3D 1
 PARAMETER C_CLKIN_FREQ =3D 100000000
 PARAMETER C_CLKOUT0_FREQ =3D 100000000
 PARAMETER C_CLKOUT0_BUF =3D TRUE
 PARAMETER C_CLKOUT0_PHASE =3D 0
 PARAMETER C_CLKOUT0_GROUP =3D DCM0
 PARAMETER C_CLKOUT1_FREQ =3D 100000000
 PARAMETER C_CLKOUT1_BUF =3D TRUE
 PARAMETER C_CLKOUT1_PHASE =3D 90
 PARAMETER C_CLKOUT1_GROUP =3D DCM0
 PARAMETER C_CLKOUT2_FREQ =3D 300000000
 PARAMETER C_CLKOUT2_BUF =3D TRUE
 PARAMETER C_CLKOUT2_PHASE =3D 0
 PARAMETER C_CLKOUT2_GROUP =3D DCM0
 PARAMETER C_CLKOUT3_FREQ =3D 200000000
 PARAMETER C_CLKOUT3_BUF =3D TRUE
 PARAMETER C_CLKOUT3_PHASE =3D 0
 PARAMETER C_CLKOUT3_GROUP =3D NONE
 PARAMETER C_CLKOUT4_FREQ =3D 125000000
 PARAMETER C_CLKOUT4_BUF =3D TRUE
 PARAMETER C_CLKOUT4_PHASE =3D 0
 PARAMETER C_CLKOUT4_GROUP =3D NONE
 PORT CLKOUT0 =3D sys_clk_s
 PORT CLKOUT1 =3D DDR_SDRAM_mpmc_clk_90_s
 PORT CLKOUT2 =3D proc_clk_s
 PORT CLKOUT3 =3D clk_200mhz_s
 PORT CLKOUT4 =3D temac_clk_s
 PORT CLKIN =3D dcm_clk_s
 PORT LOCKED =3D Dcm_all_locked
 PORT RST =3D net_gnd
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE =3D proc_sys_reset_0
 PARAMETER HW_VER =3D 2.00.a
 PARAMETER C_EXT_RESET_HIGH =3D 0
 BUS_INTERFACE RESETPPC0 =3D ppc_reset_bus
 PORT Slowest_sync_clk =3D sys_clk_s
 PORT Dcm_locked =3D Dcm_all_locked
 PORT Ext_Reset_In =3D sys_rst_s
 PORT Bus_Struct_Reset =3D sys_bus_reset
 PORT Peripheral_Reset =3D sys_periph_reset
END

BEGIN xps_intc
 PARAMETER INSTANCE =3D xps_intc_0
 PARAMETER HW_VER =3D 1.00.a
 PARAMETER C_BASEADDR =3D 0x81800000
 PARAMETER C_HIGHADDR =3D 0x8180ffff
 BUS_INTERFACE SPLB =3D plb
 PORT Irq =3D EICC405EXTINPUTIRQ
 PORT Intr =3D RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt & =
IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & =
TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut & =
DDR_SDRAM_SDMA2_Tx_IntOut
END



	#address-cells =3D <1>;
	#size-cells =3D <1>;
	compatible =3D "xlnx,virtex";
	model =3D "testing";
	DDR_SDRAM: memory@0 {
		device_type =3D "memory";
		reg =3D < 0 8000000 >;
	} ;
	chosen {
		bootargs =3D "console=3DttyS0,9600 ip=3Don =
nfsroot=3D172.16.40.76:/v2pclients/jhl26,tcp";=20
		linux,stdout-path =3D "/plb@0/serial@83e00000";
	} ;
	cpus {
		#address-cells =3D <1>;
		#cpus =3D <1>;
		#size-cells =3D <0>;
		ppc405_0: cpu@0 {
			clock-frequency =3D <11e1a300>;
			compatible =3D "PowerPC,405", "ibm,ppc405";
			d-cache-line-size =3D <20>;
			d-cache-size =3D <4000>;
			device_type =3D "cpu";
			i-cache-line-size =3D <20>;
			i-cache-size =3D <4000>;
			model =3D "PowerPC,405";
			reg =3D <0>;
			timebase-frequency =3D <11e1a300>;
			xlnx,apu-control =3D <de00>;
			xlnx,apu-udi-1 =3D <a18983>;
			xlnx,apu-udi-2 =3D <a38983>;
			xlnx,apu-udi-3 =3D <a589c3>;
			xlnx,apu-udi-4 =3D <a789c3>;
			xlnx,apu-udi-5 =3D <a98c03>;
			xlnx,apu-udi-6 =3D <ab8c03>;
			xlnx,apu-udi-7 =3D <ad8c43>;
			xlnx,apu-udi-8 =3D <af8c43>;
			xlnx,deterministic-mult =3D <0>;
			xlnx,disable-operand-forwarding =3D <1>;
			xlnx,fastest-plb-clock =3D "DPLB0";
			xlnx,generate-plb-timespecs =3D <1>;
			xlnx,mmu-enable =3D <1>;
			xlnx,pvr-high =3D <0>;
			xlnx,pvr-low =3D <0>;
		} ;
	} ;
	plb: plb@0 {
		#address-cells =3D <1>;
		#size-cells =3D <1>;
		compatible =3D "xlnx,plb-v46-1.02.a";
		ranges ;
		IIC_EEPROM: i2c@81600000 {
			compatible =3D "xlnx,xps-iic-2.00.a";
			interrupt-parent =3D <&xps_intc_0>;
			interrupts =3D < 4 2 >;
			reg =3D < 81600000 10000 >;
			xlnx,clk-freq =3D <5f5e100>;
			xlnx,family =3D "virtex4";
			xlnx,gpo-width =3D <1>;
			xlnx,iic-freq =3D <186a0>;
			xlnx,scl-inertial-delay =3D <0>;
			xlnx,sda-inertial-delay =3D <0>;
			xlnx,ten-bit-adr =3D <0>;
		} ;
		LEDs_4Bit: gpio@81400000 {
			compatible =3D "xlnx,xps-gpio-1.00.a";
			interrupt-parent =3D <&xps_intc_0>;
			interrupts =3D < 5 2 >;
			reg =3D < 81400000 10000 >;
			xlnx,all-inputs =3D <0>;
			xlnx,all-inputs-2 =3D <0>;
			xlnx,dout-default =3D <0>;
			xlnx,dout-default-2 =3D <0>;
			xlnx,family =3D "virtex4";
			xlnx,gpio-width =3D <4>;
			xlnx,interrupt-present =3D <1>;
			xlnx,is-bidir =3D <1>;
			xlnx,is-bidir-2 =3D <1>;
			xlnx,is-dual =3D <0>;
			xlnx,tri-default =3D <ffffffff>;
			xlnx,tri-default-2 =3D <ffffffff>;
		} ;
		RS232_Uart: serial@83e00000 {
			compatible =3D "xlnx,xps-uart16550-2.00.a";
//			compatible =3D "ns16550";=20
			device_type =3D "serial";
			interrupt-parent =3D <&xps_intc_0>;=20
			interrupts =3D < 6 2 >;=20
			reg =3D < 83e00000 10000 >;
			current-speed =3D <d#9600>;
			clock-frequency =3D <d#100000000>;  /* added by jhl */
			reg-shift =3D <2>;
			xlnx,family =3D "virtex4";
			xlnx,has-external-rclk =3D <0>;
			xlnx,has-external-xin =3D <0>;
			xlnx,is-a-16550 =3D <1>;
		} ;
		SysACE_CompactFlash: sysace@83600000 {
			compatible =3D "xlnx,xps-sysace-1.00.a";
			interrupt-parent =3D <&xps_intc_0>;
			interrupts =3D < 3 2 >;
			reg =3D < 83600000 10000 >;
			xlnx,family =3D "virtex4";
			xlnx,mem-width =3D <10>;
		} ;
		TriMode_MAC_GMII: xps-ll-temac@81c00000 {
			#address-cells =3D <1>;
			#size-cells =3D <1>;
			compatible =3D "xlnx,compound";
			ethernet@81c00000 {
				compatible =3D "xlnx,xps-ll-temac-1.01.a";
				device_type =3D "network";
				interrupt-parent =3D <&xps_intc_0>;
				interrupts =3D < 2 2 >;
				llink-connected =3D <&PIM2>;
				local-mac-address =3D [ 02 00 00 00 00 01 ];
				reg =3D < 81c00000 40 >;
				xlnx,bus2core-clk-ratio =3D <1>;
				xlnx,phy-type =3D <1>;
				xlnx,phyaddr =3D <1>;
				xlnx,rxcsum =3D <0>;
				xlnx,rxfifo =3D <1000>;
				xlnx,temac-type =3D <1>;
				xlnx,txcsum =3D <0>;
				xlnx,txfifo =3D <1000>;
			} ;
		} ;
		mpmc@0 {
			#address-cells =3D <1>;
			#size-cells =3D <1>;
			compatible =3D "xlnx,mpmc-4.00.a";
			PIM2: sdma@84600100 {
				compatible =3D "xlnx,ll-dma-1.00.a";
				interrupt-parent =3D <&xps_intc_0>;
				interrupts =3D < 1 2 0 2 >;
				reg =3D < 84600100 80 >;
			} ;
		} ;
		xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {
			compatible =3D "xlnx,xps-bram-if-cntlr-1.00.a";
			reg =3D < ffffe000 2000 >;
			xlnx,family =3D "virtex4";
		} ;
		xps_intc_0: interrupt-controller@81800000 {
			#interrupt-cells =3D <2>;
			compatible =3D "xlnx,xps-intc-1.00.a";
			interrupt-controller ;
			reg =3D < 81800000 10000 >;
			xlnx,num-intr-inputs =3D <7>;
		} ;
	} ;
	ppc405_0_dplb1: plb@1 {
		#address-cells =3D <1>;
		#size-cells =3D <1>;
		compatible =3D "xlnx,plb-v46-1.02.a";
		ranges ;
	} ;
}  ;



-----Original Message-----
From: Magnus Hjorth [mailto:mh@omnisys.se]=20
Sent: Saturday, March 29, 2008 6:54 AM
To: git
Cc: linuxppc-embedded@ozlabs.org
Subject: Xilinx LLTEMAC driver issues

Hi,

I'm having some networking troubles with the Xilinx LLTEMAC driver from =
the
Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
xps_ll_temac v1.00.b=20

The weird thing is, that it sort of half works. It successfully makes a =
DHCP
request and gets its IP address. I tried setting up a tftpd server, and =
I can
see UDP requests coming in but the response doesn't seem to come out. I =
also
tried running a TCP server on the board, and it can see and accept =
incoming
connections but after that no data seems to get through. I can ping out =
and
get around 40% packet loss.

Looking at /proc/interrupts, I can see both TxDma interrupts and RxDma
interrupts. No eth0 interrupts but that seems to be OK judging by the =
driver
source comments. Ifconfig shows no collistions, no dropped packets, no =
errors,
so the system seems to think that everything is OK.=20

Clues anyone? I'm starting to run out of ideas...

Best regards,
Magnus


--

Magnus Hjorth, M.Sc.
Omnisys Instruments AB
Gruvgatan 8
SE-421 30  V=E4stra Fr=F6lunda, SWEDEN
Phone: +46 31 734 34 09
Fax: +46 31 734 34 29
http://www.omnisys.se

RE: Xilinx LLTEMAC driver issues

[Magnus Hjorth]

Hi John,

Thanks for the very fast reply! Right now I'm not at work so I don't
have the board or EDK here to test anything. 

I'm using checksum offload, but I don't know if DRE is enabled or not. I
can't recall seeing any setting to enable/disable DRE.. 

A few things that crossed my mind:

Last year I did a design with EDK 8.2, back then there was an issue with
the ML403 boards having an old revision of the FPGA which wasn't
compatible with some versions of the IP core. There are no such version
issues with the xps_ll_temac? 

I don't think that I had phy-addr set in the DTS file. Will test that on
Monday. 

Best regards,
Magnus


On Sat, 2008-03-29 at 07:58 -0600, John Linn wrote:
> Hi Magnus,
> 
> Sorry to hear you're having problems with it.
> 
> I am doing testing on an ML405 which is the same board but with a bigger FPGA, but with ppc arch and I don't see this issue. I have done limited testing with powerpc arch and the LL TEMAC, but I didn't see this issue there either.  Powerpc arch is definitely less mature in my experience than the ppc arch. I'll do a quick test with my powerpc arch and make sure again I'm not seeing it.
> 
> My kernel is from the Xilinx Git tree, but there have been a number of changes we have pushed out so I don't know how long ago you pulled from the Git tree.
> 
> My EDK project is 10.1 so it's a little newer. I am using LL TEMAC 1.01a so it's a little newer.  I reviewed the change log for the LL TEMAC and don't see any big problems that were fixed in the newer versions, more new features.  I'll check with some others here to see if I missed something there.
> 
> I am using DMA also, but no DRE or checksum offload.  You didn't say anything about those. I'm going to insert my mhs file that describes my system to let you compare your system configuration. It's not clear to me yet if you have a h/w or s/w problem.  
> 
> I'll also insert some of my device tree with the LL TEMAC so you can compare (ignore 16550 stuff as we are still working on that).
> 
> Since you can't ping reliably I would probably focus on that since it's simpler than the other issues you're seeing.
> 
> Thanks,
> John
> 
> 
> 
> # ##############################################################################
> # Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build EDK_K_SP1.1
> # Thu Feb 14 14:11:12 2008
> # Target Board:  Xilinx Virtex 4 ML405 Evaluation Platform Rev 1
> # Family:    virtex4
> # Device:    xc4vfx20
> # Package:   ff672
> # Speed Grade:  -10
> # Processor: ppc405_0
> # Processor clock frequency: 300.00 MHz
> # Bus clock frequency: 100.00 MHz
> # On Chip Memory :   8 KB
> # Total Off Chip Memory : 128 MB
> # - DDR_SDRAM = 128 MB
> # ##############################################################################
>  PARAMETER VERSION = 2.1.0
> 
> 
>  PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I
>  PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O
>  PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
>  PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO
>  PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO
>  PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]
>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
>  PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
>  PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
>  PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
>  PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0]
>  PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
>  PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [3:0]
>  PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [3:0]
>  PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [31:0]
>  PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR = O, VEC = [7:0]
>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR = O
>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR = O
>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR = O
>  PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR = I, VEC = [7:0]
>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR = I
>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR = I
>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR = I
>  PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR = I
>  PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin = fpga_0_TriMode_MAC_GMII_MDIO_0, DIR = IO
>  PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin = fpga_0_TriMode_MAC_GMII_MDC_0, DIR = O
>  PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR = O
>  PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
>  PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
> 
> 
> BEGIN ppc405_virtex4
>  PARAMETER INSTANCE = ppc405_0
>  PARAMETER HW_VER = 2.01.a
>  PARAMETER C_FASTEST_PLB_CLOCK = DPLB1
>  PARAMETER C_IDCR_BASEADDR = 0b0100000000
>  PARAMETER C_IDCR_HIGHADDR = 0b0111111111
>  BUS_INTERFACE JTAGPPC = jtagppc_0_0
>  BUS_INTERFACE IPLB0 = plb
>  BUS_INTERFACE DPLB0 = plb
>  BUS_INTERFACE IPLB1 = ppc405_0_iplb1
>  BUS_INTERFACE DPLB1 = ppc405_0_dplb1
>  BUS_INTERFACE RESETPPC = ppc_reset_bus
>  PORT CPMC405CLOCK = proc_clk_s
>  PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
> END
> 
> BEGIN jtagppc_cntlr
>  PARAMETER INSTANCE = jtagppc_0
>  PARAMETER HW_VER = 2.01.a
>  BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
> END
> 
> BEGIN plb_v46
>  PARAMETER INSTANCE = plb
>  PARAMETER C_DCR_INTFCE = 0
>  PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
>  PARAMETER HW_VER = 1.02.a
>  PORT PLB_Clk = sys_clk_s
>  PORT SYS_Rst = sys_bus_reset
> END
> 
> BEGIN xps_bram_if_cntlr
>  PARAMETER INSTANCE = xps_bram_if_cntlr_1
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_SPLB_NATIVE_DWIDTH = 64
>  PARAMETER C_BASEADDR = 0xffffe000
>  PARAMETER C_HIGHADDR = 0xffffffff
>  BUS_INTERFACE SPLB = plb
>  BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
> END
> 
> BEGIN bram_block
>  PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
>  PARAMETER HW_VER = 1.00.a
>  BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
> END
> 
> BEGIN xps_uart16550
>  PARAMETER INSTANCE = RS232_Uart
>  PARAMETER HW_VER = 2.00.a
>  PARAMETER C_IS_A_16550 = 1
>  PARAMETER C_BASEADDR = 0x83e00000
>  PARAMETER C_HIGHADDR = 0x83e0ffff
>  BUS_INTERFACE SPLB = plb
>  PORT sin = fpga_0_RS232_Uart_sin
>  PORT sout = fpga_0_RS232_Uart_sout
>  PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt
> END
> 
> BEGIN xps_gpio
>  PARAMETER INSTANCE = LEDs_4Bit
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_INTERRUPT_PRESENT = 1
>  PARAMETER C_GPIO_WIDTH = 4
>  PARAMETER C_IS_DUAL = 0
>  PARAMETER C_IS_BIDIR = 1
>  PARAMETER C_ALL_INPUTS = 0
>  PARAMETER C_BASEADDR = 0x81400000
>  PARAMETER C_HIGHADDR = 0x8140ffff
>  BUS_INTERFACE SPLB = plb
>  PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
>  PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
> END
> 
> BEGIN xps_iic
>  PARAMETER INSTANCE = IIC_EEPROM
>  PARAMETER HW_VER = 2.00.a
>  PARAMETER C_CLK_FREQ = 100000000
>  PARAMETER C_IIC_FREQ = 100000
>  PARAMETER C_TEN_BIT_ADR = 0
>  PARAMETER C_BASEADDR = 0x81600000
>  PARAMETER C_HIGHADDR = 0x8160ffff
>  BUS_INTERFACE SPLB = plb
>  PORT Scl = fpga_0_IIC_EEPROM_Scl
>  PORT Sda = fpga_0_IIC_EEPROM_Sda
>  PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt
> END
> 
> BEGIN xps_sysace
>  PARAMETER INSTANCE = SysACE_CompactFlash
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_MEM_WIDTH = 16
>  PARAMETER C_BASEADDR = 0x83600000
>  PARAMETER C_HIGHADDR = 0x8360ffff
>  BUS_INTERFACE SPLB = plb
>  PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
>  PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_split
>  PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
>  PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
>  PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
>  PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
>  PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
>  PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
> END
> 
> BEGIN mpmc
>  PARAMETER INSTANCE = DDR_SDRAM
>  PARAMETER HW_VER = 4.00.a
>  PARAMETER C_NUM_PORTS = 3
>  PARAMETER C_MEM_PARTNO = HYB25D512160BE-5
>  PARAMETER C_MEM_DATA_WIDTH = 32
>  PARAMETER C_MEM_DQS_WIDTH = 4
>  PARAMETER C_MEM_DM_WIDTH = 4
>  PARAMETER C_MEM_TYPE = DDR
>  PARAMETER C_NUM_IDELAYCTRL = 2
>  PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
>  PARAMETER C_PIM0_BASETYPE = 2
>  PARAMETER C_PIM1_BASETYPE = 2
>  PARAMETER C_PIM2_BASETYPE = 3
>  PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
>  PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 1
>  PARAMETER C_MPMC_BASEADDR = 0x00000000
>  PARAMETER C_MPMC_HIGHADDR = 0x07ffffff
>  PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000
>  PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460ffff
>  BUS_INTERFACE SPLB0 = ppc405_0_iplb1
>  BUS_INTERFACE SPLB1 = ppc405_0_dplb1
>  BUS_INTERFACE SDMA_LL2 = TriMode_MAC_GMII_LLINK0
>  BUS_INTERFACE SDMA_CTRL2 = plb
>  PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
>  PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
>  PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
>  PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
>  PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
>  PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
>  PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
>  PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
>  PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
>  PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
>  PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
>  PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
>  PORT MPMC_Clk0 = sys_clk_s
>  PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
>  PORT SDMA2_Clk = sys_clk_s
>  PORT MPMC_Clk_200MHz = clk_200mhz_s
>  PORT MPMC_Rst = sys_periph_reset
>  PORT SDMA2_Rx_IntOut = DDR_SDRAM_SDMA2_Rx_IntOut
>  PORT SDMA2_Tx_IntOut = DDR_SDRAM_SDMA2_Tx_IntOut
> END
> 
> BEGIN xps_ll_temac
>  PARAMETER INSTANCE = TriMode_MAC_GMII
>  PARAMETER HW_VER = 1.01.a
>  PARAMETER C_SPLB_CLK_PERIOD_PS = 10000
>  PARAMETER C_PHY_TYPE = 1
>  PARAMETER C_NUM_IDELAYCTRL = 4
>  PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3
>  PARAMETER C_TEMAC_TYPE = 1
>  PARAMETER C_BUS2CORE_CLK_RATIO = 1
>  PARAMETER C_BASEADDR = 0x81c00000
>  PARAMETER C_HIGHADDR = 0x81c0ffff
>  BUS_INTERFACE SPLB = plb
>  BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_LLINK0
>  PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0
>  PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0
>  PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0
>  PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0
>  PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0
>  PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0
>  PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0
>  PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0
>  PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0
>  PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0
>  PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0
>  PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n
>  PORT GTX_CLK_0 = temac_clk_s
>  PORT REFCLK = clk_200mhz_s
>  PORT LlinkTemac0_CLK = sys_clk_s
>  PORT TemacIntc0_Irpt = TriMode_MAC_GMII_TemacIntc0_Irpt
> END
> 
> BEGIN util_bus_split
>  PARAMETER INSTANCE = SysACE_CompactFlash_util_bus_split_0
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_SIZE_IN = 7
>  PARAMETER C_LEFT_POS = 0
>  PARAMETER C_SPLIT = 6
>  PORT Sig = fpga_0_SysACE_CompactFlash_SysACE_MPA_split
>  PORT Out1 = fpga_0_SysACE_CompactFlash_SysACE_MPA
> END
> 
> BEGIN plb_v46
>  PARAMETER INSTANCE = ppc405_0_iplb1
>  PARAMETER HW_VER = 1.02.a
>  PORT PLB_Clk = sys_clk_s
>  PORT SYS_Rst = sys_bus_reset
> END
> 
> BEGIN plb_v46
>  PARAMETER INSTANCE = ppc405_0_dplb1
>  PARAMETER HW_VER = 1.02.a
>  PORT PLB_Clk = sys_clk_s
>  PORT SYS_Rst = sys_bus_reset
> END
> 
> BEGIN clock_generator
>  PARAMETER INSTANCE = clock_generator_0
>  PARAMETER HW_VER = 2.00.a
>  PARAMETER C_EXT_RESET_HIGH = 1
>  PARAMETER C_CLKIN_FREQ = 100000000
>  PARAMETER C_CLKOUT0_FREQ = 100000000
>  PARAMETER C_CLKOUT0_BUF = TRUE
>  PARAMETER C_CLKOUT0_PHASE = 0
>  PARAMETER C_CLKOUT0_GROUP = DCM0
>  PARAMETER C_CLKOUT1_FREQ = 100000000
>  PARAMETER C_CLKOUT1_BUF = TRUE
>  PARAMETER C_CLKOUT1_PHASE = 90
>  PARAMETER C_CLKOUT1_GROUP = DCM0
>  PARAMETER C_CLKOUT2_FREQ = 300000000
>  PARAMETER C_CLKOUT2_BUF = TRUE
>  PARAMETER C_CLKOUT2_PHASE = 0
>  PARAMETER C_CLKOUT2_GROUP = DCM0
>  PARAMETER C_CLKOUT3_FREQ = 200000000
>  PARAMETER C_CLKOUT3_BUF = TRUE
>  PARAMETER C_CLKOUT3_PHASE = 0
>  PARAMETER C_CLKOUT3_GROUP = NONE
>  PARAMETER C_CLKOUT4_FREQ = 125000000
>  PARAMETER C_CLKOUT4_BUF = TRUE
>  PARAMETER C_CLKOUT4_PHASE = 0
>  PARAMETER C_CLKOUT4_GROUP = NONE
>  PORT CLKOUT0 = sys_clk_s
>  PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_90_s
>  PORT CLKOUT2 = proc_clk_s
>  PORT CLKOUT3 = clk_200mhz_s
>  PORT CLKOUT4 = temac_clk_s
>  PORT CLKIN = dcm_clk_s
>  PORT LOCKED = Dcm_all_locked
>  PORT RST = net_gnd
> END
> 
> BEGIN proc_sys_reset
>  PARAMETER INSTANCE = proc_sys_reset_0
>  PARAMETER HW_VER = 2.00.a
>  PARAMETER C_EXT_RESET_HIGH = 0
>  BUS_INTERFACE RESETPPC0 = ppc_reset_bus
>  PORT Slowest_sync_clk = sys_clk_s
>  PORT Dcm_locked = Dcm_all_locked
>  PORT Ext_Reset_In = sys_rst_s
>  PORT Bus_Struct_Reset = sys_bus_reset
>  PORT Peripheral_Reset = sys_periph_reset
> END
> 
> BEGIN xps_intc
>  PARAMETER INSTANCE = xps_intc_0
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_BASEADDR = 0x81800000
>  PARAMETER C_HIGHADDR = 0x8180ffff
>  BUS_INTERFACE SPLB = plb
>  PORT Irq = EICC405EXTINPUTIRQ
>  PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt & IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut & DDR_SDRAM_SDMA2_Tx_IntOut
> END
> 
> 
> 
> 	#address-cells = <1>;
> 	#size-cells = <1>;
> 	compatible = "xlnx,virtex";
> 	model = "testing";
> 	DDR_SDRAM: memory@0 {
> 		device_type = "memory";
> 		reg = < 0 8000000 >;
> 	} ;
> 	chosen {
> 		bootargs = "console=ttyS0,9600 ip=on nfsroot=172.16.40.76:/v2pclients/jhl26,tcp"; 
> 		linux,stdout-path = "/plb@0/serial@83e00000";
> 	} ;
> 	cpus {
> 		#address-cells = <1>;
> 		#cpus = <1>;
> 		#size-cells = <0>;
> 		ppc405_0: cpu@0 {
> 			clock-frequency = <11e1a300>;
> 			compatible = "PowerPC,405", "ibm,ppc405";
> 			d-cache-line-size = <20>;
> 			d-cache-size = <4000>;
> 			device_type = "cpu";
> 			i-cache-line-size = <20>;
> 			i-cache-size = <4000>;
> 			model = "PowerPC,405";
> 			reg = <0>;
> 			timebase-frequency = <11e1a300>;
> 			xlnx,apu-control = <de00>;
> 			xlnx,apu-udi-1 = <a18983>;
> 			xlnx,apu-udi-2 = <a38983>;
> 			xlnx,apu-udi-3 = <a589c3>;
> 			xlnx,apu-udi-4 = <a789c3>;
> 			xlnx,apu-udi-5 = <a98c03>;
> 			xlnx,apu-udi-6 = <ab8c03>;
> 			xlnx,apu-udi-7 = <ad8c43>;
> 			xlnx,apu-udi-8 = <af8c43>;
> 			xlnx,deterministic-mult = <0>;
> 			xlnx,disable-operand-forwarding = <1>;
> 			xlnx,fastest-plb-clock = "DPLB0";
> 			xlnx,generate-plb-timespecs = <1>;
> 			xlnx,mmu-enable = <1>;
> 			xlnx,pvr-high = <0>;
> 			xlnx,pvr-low = <0>;
> 		} ;
> 	} ;
> 	plb: plb@0 {
> 		#address-cells = <1>;
> 		#size-cells = <1>;
> 		compatible = "xlnx,plb-v46-1.02.a";
> 		ranges ;
> 		IIC_EEPROM: i2c@81600000 {
> 			compatible = "xlnx,xps-iic-2.00.a";
> 			interrupt-parent = <&xps_intc_0>;
> 			interrupts = < 4 2 >;
> 			reg = < 81600000 10000 >;
> 			xlnx,clk-freq = <5f5e100>;
> 			xlnx,family = "virtex4";
> 			xlnx,gpo-width = <1>;
> 			xlnx,iic-freq = <186a0>;
> 			xlnx,scl-inertial-delay = <0>;
> 			xlnx,sda-inertial-delay = <0>;
> 			xlnx,ten-bit-adr = <0>;
> 		} ;
> 		LEDs_4Bit: gpio@81400000 {
> 			compatible = "xlnx,xps-gpio-1.00.a";
> 			interrupt-parent = <&xps_intc_0>;
> 			interrupts = < 5 2 >;
> 			reg = < 81400000 10000 >;
> 			xlnx,all-inputs = <0>;
> 			xlnx,all-inputs-2 = <0>;
> 			xlnx,dout-default = <0>;
> 			xlnx,dout-default-2 = <0>;
> 			xlnx,family = "virtex4";
> 			xlnx,gpio-width = <4>;
> 			xlnx,interrupt-present = <1>;
> 			xlnx,is-bidir = <1>;
> 			xlnx,is-bidir-2 = <1>;
> 			xlnx,is-dual = <0>;
> 			xlnx,tri-default = <ffffffff>;
> 			xlnx,tri-default-2 = <ffffffff>;
> 		} ;
> 		RS232_Uart: serial@83e00000 {
> 			compatible = "xlnx,xps-uart16550-2.00.a";
> //			compatible = "ns16550"; 
> 			device_type = "serial";
> 			interrupt-parent = <&xps_intc_0>; 
> 			interrupts = < 6 2 >; 
> 			reg = < 83e00000 10000 >;
> 			current-speed = <d#9600>;
> 			clock-frequency = <d#100000000>;  /* added by jhl */
> 			reg-shift = <2>;
> 			xlnx,family = "virtex4";
> 			xlnx,has-external-rclk = <0>;
> 			xlnx,has-external-xin = <0>;
> 			xlnx,is-a-16550 = <1>;
> 		} ;
> 		SysACE_CompactFlash: sysace@83600000 {
> 			compatible = "xlnx,xps-sysace-1.00.a";
> 			interrupt-parent = <&xps_intc_0>;
> 			interrupts = < 3 2 >;
> 			reg = < 83600000 10000 >;
> 			xlnx,family = "virtex4";
> 			xlnx,mem-width = <10>;
> 		} ;
> 		TriMode_MAC_GMII: xps-ll-temac@81c00000 {
> 			#address-cells = <1>;
> 			#size-cells = <1>;
> 			compatible = "xlnx,compound";
> 			ethernet@81c00000 {
> 				compatible = "xlnx,xps-ll-temac-1.01.a";
> 				device_type = "network";
> 				interrupt-parent = <&xps_intc_0>;
> 				interrupts = < 2 2 >;
> 				llink-connected = <&PIM2>;
> 				local-mac-address = [ 02 00 00 00 00 01 ];
> 				reg = < 81c00000 40 >;
> 				xlnx,bus2core-clk-ratio = <1>;
> 				xlnx,phy-type = <1>;
> 				xlnx,phyaddr = <1>;
> 				xlnx,rxcsum = <0>;
> 				xlnx,rxfifo = <1000>;
> 				xlnx,temac-type = <1>;
> 				xlnx,txcsum = <0>;
> 				xlnx,txfifo = <1000>;
> 			} ;
> 		} ;
> 		mpmc@0 {
> 			#address-cells = <1>;
> 			#size-cells = <1>;
> 			compatible = "xlnx,mpmc-4.00.a";
> 			PIM2: sdma@84600100 {
> 				compatible = "xlnx,ll-dma-1.00.a";
> 				interrupt-parent = <&xps_intc_0>;
> 				interrupts = < 1 2 0 2 >;
> 				reg = < 84600100 80 >;
> 			} ;
> 		} ;
> 		xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {
> 			compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
> 			reg = < ffffe000 2000 >;
> 			xlnx,family = "virtex4";
> 		} ;
> 		xps_intc_0: interrupt-controller@81800000 {
> 			#interrupt-cells = <2>;
> 			compatible = "xlnx,xps-intc-1.00.a";
> 			interrupt-controller ;
> 			reg = < 81800000 10000 >;
> 			xlnx,num-intr-inputs = <7>;
> 		} ;
> 	} ;
> 	ppc405_0_dplb1: plb@1 {
> 		#address-cells = <1>;
> 		#size-cells = <1>;
> 		compatible = "xlnx,plb-v46-1.02.a";
> 		ranges ;
> 	} ;
> }  ;
> 
> 
> 
> -----Original Message-----
> From: Magnus Hjorth [mailto:mh@omnisys.se] 
> Sent: Saturday, March 29, 2008 6:54 AM
> To: git
> Cc: linuxppc-embedded@ozlabs.org
> Subject: Xilinx LLTEMAC driver issues
> 
> Hi,
> 
> I'm having some networking troubles with the Xilinx LLTEMAC driver from the
> Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
> xps_ll_temac v1.00.b 
> 
> The weird thing is, that it sort of half works. It successfully makes a DHCP
> request and gets its IP address. I tried setting up a tftpd server, and I can
> see UDP requests coming in but the response doesn't seem to come out. I also
> tried running a TCP server on the board, and it can see and accept incoming
> connections but after that no data seems to get through. I can ping out and
> get around 40% packet loss.
> 
> Looking at /proc/interrupts, I can see both TxDma interrupts and RxDma
> interrupts. No eth0 interrupts but that seems to be OK judging by the driver
> source comments. Ifconfig shows no collistions, no dropped packets, no errors,
> so the system seems to think that everything is OK. 
> 
> Clues anyone? I'm starting to run out of ideas...
> 
> Best regards,
> Magnus
> 
> 
> --
> 
> Magnus Hjorth, M.Sc.
> Omnisys Instruments AB
> Gruvgatan 8
> SE-421 30  Västra Frölunda, SWEDEN
> Phone: +46 31 734 34 09
> Fax: +46 31 734 34 29
> http://www.omnisys.se

RE: Xilinx LLTEMAC driver issues

[Stephen Neuendorffer]

[-- Attachment #1: Type: text/plain, Size: 21975 bytes --]


I did have trouble with the 1.00 versions of the core,  if you can get EDK 10.1 with version 1.01a of the ll_temac core, that's probably worth a try.

Steve

-----Original Message-----
From: Magnus Hjorth [mailto:mh@omnisys.se]
Sent: Sat 3/29/2008 7:50 AM
To: John Linn
Cc: git; linuxppc-embedded@ozlabs.org
Subject: RE: Xilinx LLTEMAC driver issues
 
Hi John,

Thanks for the very fast reply! Right now I'm not at work so I don't
have the board or EDK here to test anything. 

I'm using checksum offload, but I don't know if DRE is enabled or not. I
can't recall seeing any setting to enable/disable DRE.. 

A few things that crossed my mind:

Last year I did a design with EDK 8.2, back then there was an issue with
the ML403 boards having an old revision of the FPGA which wasn't
compatible with some versions of the IP core. There are no such version
issues with the xps_ll_temac? 

I don't think that I had phy-addr set in the DTS file. Will test that on
Monday. 

Best regards,
Magnus


On Sat, 2008-03-29 at 07:58 -0600, John Linn wrote:
> Hi Magnus,
> 
> Sorry to hear you're having problems with it.
> 
> I am doing testing on an ML405 which is the same board but with a bigger FPGA, but with ppc arch and I don't see this issue. I have done limited testing with powerpc arch and the LL TEMAC, but I didn't see this issue there either.  Powerpc arch is definitely less mature in my experience than the ppc arch. I'll do a quick test with my powerpc arch and make sure again I'm not seeing it.
> 
> My kernel is from the Xilinx Git tree, but there have been a number of changes we have pushed out so I don't know how long ago you pulled from the Git tree.
> 
> My EDK project is 10.1 so it's a little newer. I am using LL TEMAC 1.01a so it's a little newer.  I reviewed the change log for the LL TEMAC and don't see any big problems that were fixed in the newer versions, more new features.  I'll check with some others here to see if I missed something there.
> 
> I am using DMA also, but no DRE or checksum offload.  You didn't say anything about those. I'm going to insert my mhs file that describes my system to let you compare your system configuration. It's not clear to me yet if you have a h/w or s/w problem.  
> 
> I'll also insert some of my device tree with the LL TEMAC so you can compare (ignore 16550 stuff as we are still working on that).
> 
> Since you can't ping reliably I would probably focus on that since it's simpler than the other issues you're seeing.
> 
> Thanks,
> John
> 
> 
> 
> # ##############################################################################
> # Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build EDK_K_SP1.1
> # Thu Feb 14 14:11:12 2008
> # Target Board:  Xilinx Virtex 4 ML405 Evaluation Platform Rev 1
> # Family:    virtex4
> # Device:    xc4vfx20
> # Package:   ff672
> # Speed Grade:  -10
> # Processor: ppc405_0
> # Processor clock frequency: 300.00 MHz
> # Bus clock frequency: 100.00 MHz
> # On Chip Memory :   8 KB
> # Total Off Chip Memory : 128 MB
> # - DDR_SDRAM = 128 MB
> # ##############################################################################
>  PARAMETER VERSION = 2.1.0
> 
> 
>  PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I
>  PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O
>  PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
>  PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO
>  PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO
>  PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]
>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
>  PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
>  PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
>  PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
>  PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0]
>  PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
>  PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O
>  PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [3:0]
>  PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [3:0]
>  PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [31:0]
>  PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR = O, VEC = [7:0]
>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR = O
>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR = O
>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR = O
>  PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR = I, VEC = [7:0]
>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR = I
>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR = I
>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR = I
>  PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR = I
>  PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin = fpga_0_TriMode_MAC_GMII_MDIO_0, DIR = IO
>  PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin = fpga_0_TriMode_MAC_GMII_MDC_0, DIR = O
>  PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR = O
>  PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
>  PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
> 
> 
> BEGIN ppc405_virtex4
>  PARAMETER INSTANCE = ppc405_0
>  PARAMETER HW_VER = 2.01.a
>  PARAMETER C_FASTEST_PLB_CLOCK = DPLB1
>  PARAMETER C_IDCR_BASEADDR = 0b0100000000
>  PARAMETER C_IDCR_HIGHADDR = 0b0111111111
>  BUS_INTERFACE JTAGPPC = jtagppc_0_0
>  BUS_INTERFACE IPLB0 = plb
>  BUS_INTERFACE DPLB0 = plb
>  BUS_INTERFACE IPLB1 = ppc405_0_iplb1
>  BUS_INTERFACE DPLB1 = ppc405_0_dplb1
>  BUS_INTERFACE RESETPPC = ppc_reset_bus
>  PORT CPMC405CLOCK = proc_clk_s
>  PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
> END
> 
> BEGIN jtagppc_cntlr
>  PARAMETER INSTANCE = jtagppc_0
>  PARAMETER HW_VER = 2.01.a
>  BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
> END
> 
> BEGIN plb_v46
>  PARAMETER INSTANCE = plb
>  PARAMETER C_DCR_INTFCE = 0
>  PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
>  PARAMETER HW_VER = 1.02.a
>  PORT PLB_Clk = sys_clk_s
>  PORT SYS_Rst = sys_bus_reset
> END
> 
> BEGIN xps_bram_if_cntlr
>  PARAMETER INSTANCE = xps_bram_if_cntlr_1
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_SPLB_NATIVE_DWIDTH = 64
>  PARAMETER C_BASEADDR = 0xffffe000
>  PARAMETER C_HIGHADDR = 0xffffffff
>  BUS_INTERFACE SPLB = plb
>  BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
> END
> 
> BEGIN bram_block
>  PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
>  PARAMETER HW_VER = 1.00.a
>  BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
> END
> 
> BEGIN xps_uart16550
>  PARAMETER INSTANCE = RS232_Uart
>  PARAMETER HW_VER = 2.00.a
>  PARAMETER C_IS_A_16550 = 1
>  PARAMETER C_BASEADDR = 0x83e00000
>  PARAMETER C_HIGHADDR = 0x83e0ffff
>  BUS_INTERFACE SPLB = plb
>  PORT sin = fpga_0_RS232_Uart_sin
>  PORT sout = fpga_0_RS232_Uart_sout
>  PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt
> END
> 
> BEGIN xps_gpio
>  PARAMETER INSTANCE = LEDs_4Bit
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_INTERRUPT_PRESENT = 1
>  PARAMETER C_GPIO_WIDTH = 4
>  PARAMETER C_IS_DUAL = 0
>  PARAMETER C_IS_BIDIR = 1
>  PARAMETER C_ALL_INPUTS = 0
>  PARAMETER C_BASEADDR = 0x81400000
>  PARAMETER C_HIGHADDR = 0x8140ffff
>  BUS_INTERFACE SPLB = plb
>  PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
>  PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
> END
> 
> BEGIN xps_iic
>  PARAMETER INSTANCE = IIC_EEPROM
>  PARAMETER HW_VER = 2.00.a
>  PARAMETER C_CLK_FREQ = 100000000
>  PARAMETER C_IIC_FREQ = 100000
>  PARAMETER C_TEN_BIT_ADR = 0
>  PARAMETER C_BASEADDR = 0x81600000
>  PARAMETER C_HIGHADDR = 0x8160ffff
>  BUS_INTERFACE SPLB = plb
>  PORT Scl = fpga_0_IIC_EEPROM_Scl
>  PORT Sda = fpga_0_IIC_EEPROM_Sda
>  PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt
> END
> 
> BEGIN xps_sysace
>  PARAMETER INSTANCE = SysACE_CompactFlash
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_MEM_WIDTH = 16
>  PARAMETER C_BASEADDR = 0x83600000
>  PARAMETER C_HIGHADDR = 0x8360ffff
>  BUS_INTERFACE SPLB = plb
>  PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
>  PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_split
>  PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
>  PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
>  PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
>  PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
>  PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
>  PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
> END
> 
> BEGIN mpmc
>  PARAMETER INSTANCE = DDR_SDRAM
>  PARAMETER HW_VER = 4.00.a
>  PARAMETER C_NUM_PORTS = 3
>  PARAMETER C_MEM_PARTNO = HYB25D512160BE-5
>  PARAMETER C_MEM_DATA_WIDTH = 32
>  PARAMETER C_MEM_DQS_WIDTH = 4
>  PARAMETER C_MEM_DM_WIDTH = 4
>  PARAMETER C_MEM_TYPE = DDR
>  PARAMETER C_NUM_IDELAYCTRL = 2
>  PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
>  PARAMETER C_PIM0_BASETYPE = 2
>  PARAMETER C_PIM1_BASETYPE = 2
>  PARAMETER C_PIM2_BASETYPE = 3
>  PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
>  PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 1
>  PARAMETER C_MPMC_BASEADDR = 0x00000000
>  PARAMETER C_MPMC_HIGHADDR = 0x07ffffff
>  PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000
>  PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460ffff
>  BUS_INTERFACE SPLB0 = ppc405_0_iplb1
>  BUS_INTERFACE SPLB1 = ppc405_0_dplb1
>  BUS_INTERFACE SDMA_LL2 = TriMode_MAC_GMII_LLINK0
>  BUS_INTERFACE SDMA_CTRL2 = plb
>  PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
>  PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
>  PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
>  PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
>  PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
>  PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
>  PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
>  PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
>  PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
>  PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
>  PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
>  PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
>  PORT MPMC_Clk0 = sys_clk_s
>  PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
>  PORT SDMA2_Clk = sys_clk_s
>  PORT MPMC_Clk_200MHz = clk_200mhz_s
>  PORT MPMC_Rst = sys_periph_reset
>  PORT SDMA2_Rx_IntOut = DDR_SDRAM_SDMA2_Rx_IntOut
>  PORT SDMA2_Tx_IntOut = DDR_SDRAM_SDMA2_Tx_IntOut
> END
> 
> BEGIN xps_ll_temac
>  PARAMETER INSTANCE = TriMode_MAC_GMII
>  PARAMETER HW_VER = 1.01.a
>  PARAMETER C_SPLB_CLK_PERIOD_PS = 10000
>  PARAMETER C_PHY_TYPE = 1
>  PARAMETER C_NUM_IDELAYCTRL = 4
>  PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3
>  PARAMETER C_TEMAC_TYPE = 1
>  PARAMETER C_BUS2CORE_CLK_RATIO = 1
>  PARAMETER C_BASEADDR = 0x81c00000
>  PARAMETER C_HIGHADDR = 0x81c0ffff
>  BUS_INTERFACE SPLB = plb
>  BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_LLINK0
>  PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0
>  PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0
>  PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0
>  PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0
>  PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0
>  PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0
>  PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0
>  PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0
>  PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0
>  PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0
>  PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0
>  PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n
>  PORT GTX_CLK_0 = temac_clk_s
>  PORT REFCLK = clk_200mhz_s
>  PORT LlinkTemac0_CLK = sys_clk_s
>  PORT TemacIntc0_Irpt = TriMode_MAC_GMII_TemacIntc0_Irpt
> END
> 
> BEGIN util_bus_split
>  PARAMETER INSTANCE = SysACE_CompactFlash_util_bus_split_0
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_SIZE_IN = 7
>  PARAMETER C_LEFT_POS = 0
>  PARAMETER C_SPLIT = 6
>  PORT Sig = fpga_0_SysACE_CompactFlash_SysACE_MPA_split
>  PORT Out1 = fpga_0_SysACE_CompactFlash_SysACE_MPA
> END
> 
> BEGIN plb_v46
>  PARAMETER INSTANCE = ppc405_0_iplb1
>  PARAMETER HW_VER = 1.02.a
>  PORT PLB_Clk = sys_clk_s
>  PORT SYS_Rst = sys_bus_reset
> END
> 
> BEGIN plb_v46
>  PARAMETER INSTANCE = ppc405_0_dplb1
>  PARAMETER HW_VER = 1.02.a
>  PORT PLB_Clk = sys_clk_s
>  PORT SYS_Rst = sys_bus_reset
> END
> 
> BEGIN clock_generator
>  PARAMETER INSTANCE = clock_generator_0
>  PARAMETER HW_VER = 2.00.a
>  PARAMETER C_EXT_RESET_HIGH = 1
>  PARAMETER C_CLKIN_FREQ = 100000000
>  PARAMETER C_CLKOUT0_FREQ = 100000000
>  PARAMETER C_CLKOUT0_BUF = TRUE
>  PARAMETER C_CLKOUT0_PHASE = 0
>  PARAMETER C_CLKOUT0_GROUP = DCM0
>  PARAMETER C_CLKOUT1_FREQ = 100000000
>  PARAMETER C_CLKOUT1_BUF = TRUE
>  PARAMETER C_CLKOUT1_PHASE = 90
>  PARAMETER C_CLKOUT1_GROUP = DCM0
>  PARAMETER C_CLKOUT2_FREQ = 300000000
>  PARAMETER C_CLKOUT2_BUF = TRUE
>  PARAMETER C_CLKOUT2_PHASE = 0
>  PARAMETER C_CLKOUT2_GROUP = DCM0
>  PARAMETER C_CLKOUT3_FREQ = 200000000
>  PARAMETER C_CLKOUT3_BUF = TRUE
>  PARAMETER C_CLKOUT3_PHASE = 0
>  PARAMETER C_CLKOUT3_GROUP = NONE
>  PARAMETER C_CLKOUT4_FREQ = 125000000
>  PARAMETER C_CLKOUT4_BUF = TRUE
>  PARAMETER C_CLKOUT4_PHASE = 0
>  PARAMETER C_CLKOUT4_GROUP = NONE
>  PORT CLKOUT0 = sys_clk_s
>  PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_90_s
>  PORT CLKOUT2 = proc_clk_s
>  PORT CLKOUT3 = clk_200mhz_s
>  PORT CLKOUT4 = temac_clk_s
>  PORT CLKIN = dcm_clk_s
>  PORT LOCKED = Dcm_all_locked
>  PORT RST = net_gnd
> END
> 
> BEGIN proc_sys_reset
>  PARAMETER INSTANCE = proc_sys_reset_0
>  PARAMETER HW_VER = 2.00.a
>  PARAMETER C_EXT_RESET_HIGH = 0
>  BUS_INTERFACE RESETPPC0 = ppc_reset_bus
>  PORT Slowest_sync_clk = sys_clk_s
>  PORT Dcm_locked = Dcm_all_locked
>  PORT Ext_Reset_In = sys_rst_s
>  PORT Bus_Struct_Reset = sys_bus_reset
>  PORT Peripheral_Reset = sys_periph_reset
> END
> 
> BEGIN xps_intc
>  PARAMETER INSTANCE = xps_intc_0
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_BASEADDR = 0x81800000
>  PARAMETER C_HIGHADDR = 0x8180ffff
>  BUS_INTERFACE SPLB = plb
>  PORT Irq = EICC405EXTINPUTIRQ
>  PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt & IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut & DDR_SDRAM_SDMA2_Tx_IntOut
> END
> 
> 
> 
> 	#address-cells = <1>;
> 	#size-cells = <1>;
> 	compatible = "xlnx,virtex";
> 	model = "testing";
> 	DDR_SDRAM: memory@0 {
> 		device_type = "memory";
> 		reg = < 0 8000000 >;
> 	} ;
> 	chosen {
> 		bootargs = "console=ttyS0,9600 ip=on nfsroot=172.16.40.76:/v2pclients/jhl26,tcp"; 
> 		linux,stdout-path = "/plb@0/serial@83e00000";
> 	} ;
> 	cpus {
> 		#address-cells = <1>;
> 		#cpus = <1>;
> 		#size-cells = <0>;
> 		ppc405_0: cpu@0 {
> 			clock-frequency = <11e1a300>;
> 			compatible = "PowerPC,405", "ibm,ppc405";
> 			d-cache-line-size = <20>;
> 			d-cache-size = <4000>;
> 			device_type = "cpu";
> 			i-cache-line-size = <20>;
> 			i-cache-size = <4000>;
> 			model = "PowerPC,405";
> 			reg = <0>;
> 			timebase-frequency = <11e1a300>;
> 			xlnx,apu-control = <de00>;
> 			xlnx,apu-udi-1 = <a18983>;
> 			xlnx,apu-udi-2 = <a38983>;
> 			xlnx,apu-udi-3 = <a589c3>;
> 			xlnx,apu-udi-4 = <a789c3>;
> 			xlnx,apu-udi-5 = <a98c03>;
> 			xlnx,apu-udi-6 = <ab8c03>;
> 			xlnx,apu-udi-7 = <ad8c43>;
> 			xlnx,apu-udi-8 = <af8c43>;
> 			xlnx,deterministic-mult = <0>;
> 			xlnx,disable-operand-forwarding = <1>;
> 			xlnx,fastest-plb-clock = "DPLB0";
> 			xlnx,generate-plb-timespecs = <1>;
> 			xlnx,mmu-enable = <1>;
> 			xlnx,pvr-high = <0>;
> 			xlnx,pvr-low = <0>;
> 		} ;
> 	} ;
> 	plb: plb@0 {
> 		#address-cells = <1>;
> 		#size-cells = <1>;
> 		compatible = "xlnx,plb-v46-1.02.a";
> 		ranges ;
> 		IIC_EEPROM: i2c@81600000 {
> 			compatible = "xlnx,xps-iic-2.00.a";
> 			interrupt-parent = <&xps_intc_0>;
> 			interrupts = < 4 2 >;
> 			reg = < 81600000 10000 >;
> 			xlnx,clk-freq = <5f5e100>;
> 			xlnx,family = "virtex4";
> 			xlnx,gpo-width = <1>;
> 			xlnx,iic-freq = <186a0>;
> 			xlnx,scl-inertial-delay = <0>;
> 			xlnx,sda-inertial-delay = <0>;
> 			xlnx,ten-bit-adr = <0>;
> 		} ;
> 		LEDs_4Bit: gpio@81400000 {
> 			compatible = "xlnx,xps-gpio-1.00.a";
> 			interrupt-parent = <&xps_intc_0>;
> 			interrupts = < 5 2 >;
> 			reg = < 81400000 10000 >;
> 			xlnx,all-inputs = <0>;
> 			xlnx,all-inputs-2 = <0>;
> 			xlnx,dout-default = <0>;
> 			xlnx,dout-default-2 = <0>;
> 			xlnx,family = "virtex4";
> 			xlnx,gpio-width = <4>;
> 			xlnx,interrupt-present = <1>;
> 			xlnx,is-bidir = <1>;
> 			xlnx,is-bidir-2 = <1>;
> 			xlnx,is-dual = <0>;
> 			xlnx,tri-default = <ffffffff>;
> 			xlnx,tri-default-2 = <ffffffff>;
> 		} ;
> 		RS232_Uart: serial@83e00000 {
> 			compatible = "xlnx,xps-uart16550-2.00.a";
> //			compatible = "ns16550"; 
> 			device_type = "serial";
> 			interrupt-parent = <&xps_intc_0>; 
> 			interrupts = < 6 2 >; 
> 			reg = < 83e00000 10000 >;
> 			current-speed = <d#9600>;
> 			clock-frequency = <d#100000000>;  /* added by jhl */
> 			reg-shift = <2>;
> 			xlnx,family = "virtex4";
> 			xlnx,has-external-rclk = <0>;
> 			xlnx,has-external-xin = <0>;
> 			xlnx,is-a-16550 = <1>;
> 		} ;
> 		SysACE_CompactFlash: sysace@83600000 {
> 			compatible = "xlnx,xps-sysace-1.00.a";
> 			interrupt-parent = <&xps_intc_0>;
> 			interrupts = < 3 2 >;
> 			reg = < 83600000 10000 >;
> 			xlnx,family = "virtex4";
> 			xlnx,mem-width = <10>;
> 		} ;
> 		TriMode_MAC_GMII: xps-ll-temac@81c00000 {
> 			#address-cells = <1>;
> 			#size-cells = <1>;
> 			compatible = "xlnx,compound";
> 			ethernet@81c00000 {
> 				compatible = "xlnx,xps-ll-temac-1.01.a";
> 				device_type = "network";
> 				interrupt-parent = <&xps_intc_0>;
> 				interrupts = < 2 2 >;
> 				llink-connected = <&PIM2>;
> 				local-mac-address = [ 02 00 00 00 00 01 ];
> 				reg = < 81c00000 40 >;
> 				xlnx,bus2core-clk-ratio = <1>;
> 				xlnx,phy-type = <1>;
> 				xlnx,phyaddr = <1>;
> 				xlnx,rxcsum = <0>;
> 				xlnx,rxfifo = <1000>;
> 				xlnx,temac-type = <1>;
> 				xlnx,txcsum = <0>;
> 				xlnx,txfifo = <1000>;
> 			} ;
> 		} ;
> 		mpmc@0 {
> 			#address-cells = <1>;
> 			#size-cells = <1>;
> 			compatible = "xlnx,mpmc-4.00.a";
> 			PIM2: sdma@84600100 {
> 				compatible = "xlnx,ll-dma-1.00.a";
> 				interrupt-parent = <&xps_intc_0>;
> 				interrupts = < 1 2 0 2 >;
> 				reg = < 84600100 80 >;
> 			} ;
> 		} ;
> 		xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {
> 			compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
> 			reg = < ffffe000 2000 >;
> 			xlnx,family = "virtex4";
> 		} ;
> 		xps_intc_0: interrupt-controller@81800000 {
> 			#interrupt-cells = <2>;
> 			compatible = "xlnx,xps-intc-1.00.a";
> 			interrupt-controller ;
> 			reg = < 81800000 10000 >;
> 			xlnx,num-intr-inputs = <7>;
> 		} ;
> 	} ;
> 	ppc405_0_dplb1: plb@1 {
> 		#address-cells = <1>;
> 		#size-cells = <1>;
> 		compatible = "xlnx,plb-v46-1.02.a";
> 		ranges ;
> 	} ;
> }  ;
> 
> 
> 
> -----Original Message-----
> From: Magnus Hjorth [mailto:mh@omnisys.se] 
> Sent: Saturday, March 29, 2008 6:54 AM
> To: git
> Cc: linuxppc-embedded@ozlabs.org
> Subject: Xilinx LLTEMAC driver issues
> 
> Hi,
> 
> I'm having some networking troubles with the Xilinx LLTEMAC driver from the
> Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
> xps_ll_temac v1.00.b 
> 
> The weird thing is, that it sort of half works. It successfully makes a DHCP
> request and gets its IP address. I tried setting up a tftpd server, and I can
> see UDP requests coming in but the response doesn't seem to come out. I also
> tried running a TCP server on the board, and it can see and accept incoming
> connections but after that no data seems to get through. I can ping out and
> get around 40% packet loss.
> 
> Looking at /proc/interrupts, I can see both TxDma interrupts and RxDma
> interrupts. No eth0 interrupts but that seems to be OK judging by the driver
> source comments. Ifconfig shows no collistions, no dropped packets, no errors,
> so the system seems to think that everything is OK. 
> 
> Clues anyone? I'm starting to run out of ideas...
> 
> Best regards,
> Magnus
> 
> 
> --
> 
> Magnus Hjorth, M.Sc.
> Omnisys Instruments AB
> Gruvgatan 8
> SE-421 30  Västra Frölunda, SWEDEN
> Phone: +46 31 734 34 09
> Fax: +46 31 734 34 29
> http://www.omnisys.se




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Re: Xilinx LLTEMAC driver issues

[rza1]

Hi Magnus,

1.
I am using nearly the same versions then you and got the same problems 
too ;-).
I think there are some problems with the checksum offloading.
Try to sniff the some packages (e.g. wireshark)...
For me ICMP (ping) worked but udp and tcp not (because off a wrong 
checksum in the transport layer).
A quick solution is to just deactivate checksum offloading.

2.
I remember some problems with Virtex-4 presamples too.
There where problems with the hard-temac wrapper. You had to use 1.00.a 
and not b version.
But I don't have these problems with the EDK 9.2sp2/ISE9.2sp3 anymore.

all the best,
Robert

Magnus Hjorth wrote:
> Hi John,
>
> Thanks for the very fast reply! Right now I'm not at work so I don't
> have the board or EDK here to test anything. 
>
> I'm using checksum offload, but I don't know if DRE is enabled or not. I
> can't recall seeing any setting to enable/disable DRE.. 
>
> A few things that crossed my mind:
>
> Last year I did a design with EDK 8.2, back then there was an issue with
> the ML403 boards having an old revision of the FPGA which wasn't
> compatible with some versions of the IP core. There are no such version
> issues with the xps_ll_temac? 
>
> I don't think that I had phy-addr set in the DTS file. Will test that on
> Monday. 
>
> Best regards,
> Magnus
>
>
> On Sat, 2008-03-29 at 07:58 -0600, John Linn wrote:
>   
>> Hi Magnus,
>>
>> Sorry to hear you're having problems with it.
>>
>> I am doing testing on an ML405 which is the same board but with a bigger FPGA, but with ppc arch and I don't see this issue. I have done limited testing with powerpc arch and the LL TEMAC, but I didn't see this issue there either.  Powerpc arch is definitely less mature in my experience than the ppc arch. I'll do a quick test with my powerpc arch and make sure again I'm not seeing it.
>>
>> My kernel is from the Xilinx Git tree, but there have been a number of changes we have pushed out so I don't know how long ago you pulled from the Git tree.
>>
>> My EDK project is 10.1 so it's a little newer. I am using LL TEMAC 1.01a so it's a little newer.  I reviewed the change log for the LL TEMAC and don't see any big problems that were fixed in the newer versions, more new features.  I'll check with some others here to see if I missed something there.
>>
>> I am using DMA also, but no DRE or checksum offload.  You didn't say anything about those. I'm going to insert my mhs file that describes my system to let you compare your system configuration. It's not clear to me yet if you have a h/w or s/w problem.  
>>
>> I'll also insert some of my device tree with the LL TEMAC so you can compare (ignore 16550 stuff as we are still working on that).
>>
>> Since you can't ping reliably I would probably focus on that since it's simpler than the other issues you're seeing.
>>
>> Thanks,
>> John
>>
>>
>>
>> # ##############################################################################
>> # Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build EDK_K_SP1.1
>> # Thu Feb 14 14:11:12 2008
>> # Target Board:  Xilinx Virtex 4 ML405 Evaluation Platform Rev 1
>> # Family:    virtex4
>> # Device:    xc4vfx20
>> # Package:   ff672
>> # Speed Grade:  -10
>> # Processor: ppc405_0
>> # Processor clock frequency: 300.00 MHz
>> # Bus clock frequency: 100.00 MHz
>> # On Chip Memory :   8 KB
>> # Total Off Chip Memory : 128 MB
>> # - DDR_SDRAM = 128 MB
>> # ##############################################################################
>>  PARAMETER VERSION = 2.1.0
>>
>>
>>  PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I
>>  PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O
>>  PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
>>  PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO
>>  PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO
>>  PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
>>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]
>>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
>>  PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
>>  PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
>>  PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
>>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
>>  PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O
>>  PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O
>>  PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0]
>>  PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
>>  PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O
>>  PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
>>  PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O
>>  PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O
>>  PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O
>>  PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [3:0]
>>  PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [3:0]
>>  PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [31:0]
>>  PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR = O, VEC = [7:0]
>>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR = O
>>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR = O
>>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR = O
>>  PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR = I, VEC = [7:0]
>>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR = I
>>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR = I
>>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR = I
>>  PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR = I
>>  PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin = fpga_0_TriMode_MAC_GMII_MDIO_0, DIR = IO
>>  PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin = fpga_0_TriMode_MAC_GMII_MDC_0, DIR = O
>>  PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR = O
>>  PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
>>  PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
>>
>>
>> BEGIN ppc405_virtex4
>>  PARAMETER INSTANCE = ppc405_0
>>  PARAMETER HW_VER = 2.01.a
>>  PARAMETER C_FASTEST_PLB_CLOCK = DPLB1
>>  PARAMETER C_IDCR_BASEADDR = 0b0100000000
>>  PARAMETER C_IDCR_HIGHADDR = 0b0111111111
>>  BUS_INTERFACE JTAGPPC = jtagppc_0_0
>>  BUS_INTERFACE IPLB0 = plb
>>  BUS_INTERFACE DPLB0 = plb
>>  BUS_INTERFACE IPLB1 = ppc405_0_iplb1
>>  BUS_INTERFACE DPLB1 = ppc405_0_dplb1
>>  BUS_INTERFACE RESETPPC = ppc_reset_bus
>>  PORT CPMC405CLOCK = proc_clk_s
>>  PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
>> END
>>
>> BEGIN jtagppc_cntlr
>>  PARAMETER INSTANCE = jtagppc_0
>>  PARAMETER HW_VER = 2.01.a
>>  BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
>> END
>>
>> BEGIN plb_v46
>>  PARAMETER INSTANCE = plb
>>  PARAMETER C_DCR_INTFCE = 0
>>  PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
>>  PARAMETER HW_VER = 1.02.a
>>  PORT PLB_Clk = sys_clk_s
>>  PORT SYS_Rst = sys_bus_reset
>> END
>>
>> BEGIN xps_bram_if_cntlr
>>  PARAMETER INSTANCE = xps_bram_if_cntlr_1
>>  PARAMETER HW_VER = 1.00.a
>>  PARAMETER C_SPLB_NATIVE_DWIDTH = 64
>>  PARAMETER C_BASEADDR = 0xffffe000
>>  PARAMETER C_HIGHADDR = 0xffffffff
>>  BUS_INTERFACE SPLB = plb
>>  BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
>> END
>>
>> BEGIN bram_block
>>  PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
>>  PARAMETER HW_VER = 1.00.a
>>  BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
>> END
>>
>> BEGIN xps_uart16550
>>  PARAMETER INSTANCE = RS232_Uart
>>  PARAMETER HW_VER = 2.00.a
>>  PARAMETER C_IS_A_16550 = 1
>>  PARAMETER C_BASEADDR = 0x83e00000
>>  PARAMETER C_HIGHADDR = 0x83e0ffff
>>  BUS_INTERFACE SPLB = plb
>>  PORT sin = fpga_0_RS232_Uart_sin
>>  PORT sout = fpga_0_RS232_Uart_sout
>>  PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt
>> END
>>
>> BEGIN xps_gpio
>>  PARAMETER INSTANCE = LEDs_4Bit
>>  PARAMETER HW_VER = 1.00.a
>>  PARAMETER C_INTERRUPT_PRESENT = 1
>>  PARAMETER C_GPIO_WIDTH = 4
>>  PARAMETER C_IS_DUAL = 0
>>  PARAMETER C_IS_BIDIR = 1
>>  PARAMETER C_ALL_INPUTS = 0
>>  PARAMETER C_BASEADDR = 0x81400000
>>  PARAMETER C_HIGHADDR = 0x8140ffff
>>  BUS_INTERFACE SPLB = plb
>>  PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
>>  PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
>> END
>>
>> BEGIN xps_iic
>>  PARAMETER INSTANCE = IIC_EEPROM
>>  PARAMETER HW_VER = 2.00.a
>>  PARAMETER C_CLK_FREQ = 100000000
>>  PARAMETER C_IIC_FREQ = 100000
>>  PARAMETER C_TEN_BIT_ADR = 0
>>  PARAMETER C_BASEADDR = 0x81600000
>>  PARAMETER C_HIGHADDR = 0x8160ffff
>>  BUS_INTERFACE SPLB = plb
>>  PORT Scl = fpga_0_IIC_EEPROM_Scl
>>  PORT Sda = fpga_0_IIC_EEPROM_Sda
>>  PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt
>> END
>>
>> BEGIN xps_sysace
>>  PARAMETER INSTANCE = SysACE_CompactFlash
>>  PARAMETER HW_VER = 1.00.a
>>  PARAMETER C_MEM_WIDTH = 16
>>  PARAMETER C_BASEADDR = 0x83600000
>>  PARAMETER C_HIGHADDR = 0x8360ffff
>>  BUS_INTERFACE SPLB = plb
>>  PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
>>  PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_split
>>  PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
>>  PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
>>  PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
>>  PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
>>  PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
>>  PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
>> END
>>
>> BEGIN mpmc
>>  PARAMETER INSTANCE = DDR_SDRAM
>>  PARAMETER HW_VER = 4.00.a
>>  PARAMETER C_NUM_PORTS = 3
>>  PARAMETER C_MEM_PARTNO = HYB25D512160BE-5
>>  PARAMETER C_MEM_DATA_WIDTH = 32
>>  PARAMETER C_MEM_DQS_WIDTH = 4
>>  PARAMETER C_MEM_DM_WIDTH = 4
>>  PARAMETER C_MEM_TYPE = DDR
>>  PARAMETER C_NUM_IDELAYCTRL = 2
>>  PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
>>  PARAMETER C_PIM0_BASETYPE = 2
>>  PARAMETER C_PIM1_BASETYPE = 2
>>  PARAMETER C_PIM2_BASETYPE = 3
>>  PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
>>  PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 1
>>  PARAMETER C_MPMC_BASEADDR = 0x00000000
>>  PARAMETER C_MPMC_HIGHADDR = 0x07ffffff
>>  PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000
>>  PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460ffff
>>  BUS_INTERFACE SPLB0 = ppc405_0_iplb1
>>  BUS_INTERFACE SPLB1 = ppc405_0_dplb1
>>  BUS_INTERFACE SDMA_LL2 = TriMode_MAC_GMII_LLINK0
>>  BUS_INTERFACE SDMA_CTRL2 = plb
>>  PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
>>  PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
>>  PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
>>  PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
>>  PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
>>  PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
>>  PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
>>  PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
>>  PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
>>  PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
>>  PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
>>  PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
>>  PORT MPMC_Clk0 = sys_clk_s
>>  PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
>>  PORT SDMA2_Clk = sys_clk_s
>>  PORT MPMC_Clk_200MHz = clk_200mhz_s
>>  PORT MPMC_Rst = sys_periph_reset
>>  PORT SDMA2_Rx_IntOut = DDR_SDRAM_SDMA2_Rx_IntOut
>>  PORT SDMA2_Tx_IntOut = DDR_SDRAM_SDMA2_Tx_IntOut
>> END
>>
>> BEGIN xps_ll_temac
>>  PARAMETER INSTANCE = TriMode_MAC_GMII
>>  PARAMETER HW_VER = 1.01.a
>>  PARAMETER C_SPLB_CLK_PERIOD_PS = 10000
>>  PARAMETER C_PHY_TYPE = 1
>>  PARAMETER C_NUM_IDELAYCTRL = 4
>>  PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3
>>  PARAMETER C_TEMAC_TYPE = 1
>>  PARAMETER C_BUS2CORE_CLK_RATIO = 1
>>  PARAMETER C_BASEADDR = 0x81c00000
>>  PARAMETER C_HIGHADDR = 0x81c0ffff
>>  BUS_INTERFACE SPLB = plb
>>  BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_LLINK0
>>  PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0
>>  PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0
>>  PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0
>>  PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0
>>  PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0
>>  PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0
>>  PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0
>>  PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0
>>  PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0
>>  PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0
>>  PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0
>>  PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n
>>  PORT GTX_CLK_0 = temac_clk_s
>>  PORT REFCLK = clk_200mhz_s
>>  PORT LlinkTemac0_CLK = sys_clk_s
>>  PORT TemacIntc0_Irpt = TriMode_MAC_GMII_TemacIntc0_Irpt
>> END
>>
>> BEGIN util_bus_split
>>  PARAMETER INSTANCE = SysACE_CompactFlash_util_bus_split_0
>>  PARAMETER HW_VER = 1.00.a
>>  PARAMETER C_SIZE_IN = 7
>>  PARAMETER C_LEFT_POS = 0
>>  PARAMETER C_SPLIT = 6
>>  PORT Sig = fpga_0_SysACE_CompactFlash_SysACE_MPA_split
>>  PORT Out1 = fpga_0_SysACE_CompactFlash_SysACE_MPA
>> END
>>
>> BEGIN plb_v46
>>  PARAMETER INSTANCE = ppc405_0_iplb1
>>  PARAMETER HW_VER = 1.02.a
>>  PORT PLB_Clk = sys_clk_s
>>  PORT SYS_Rst = sys_bus_reset
>> END
>>
>> BEGIN plb_v46
>>  PARAMETER INSTANCE = ppc405_0_dplb1
>>  PARAMETER HW_VER = 1.02.a
>>  PORT PLB_Clk = sys_clk_s
>>  PORT SYS_Rst = sys_bus_reset
>> END
>>
>> BEGIN clock_generator
>>  PARAMETER INSTANCE = clock_generator_0
>>  PARAMETER HW_VER = 2.00.a
>>  PARAMETER C_EXT_RESET_HIGH = 1
>>  PARAMETER C_CLKIN_FREQ = 100000000
>>  PARAMETER C_CLKOUT0_FREQ = 100000000
>>  PARAMETER C_CLKOUT0_BUF = TRUE
>>  PARAMETER C_CLKOUT0_PHASE = 0
>>  PARAMETER C_CLKOUT0_GROUP = DCM0
>>  PARAMETER C_CLKOUT1_FREQ = 100000000
>>  PARAMETER C_CLKOUT1_BUF = TRUE
>>  PARAMETER C_CLKOUT1_PHASE = 90
>>  PARAMETER C_CLKOUT1_GROUP = DCM0
>>  PARAMETER C_CLKOUT2_FREQ = 300000000
>>  PARAMETER C_CLKOUT2_BUF = TRUE
>>  PARAMETER C_CLKOUT2_PHASE = 0
>>  PARAMETER C_CLKOUT2_GROUP = DCM0
>>  PARAMETER C_CLKOUT3_FREQ = 200000000
>>  PARAMETER C_CLKOUT3_BUF = TRUE
>>  PARAMETER C_CLKOUT3_PHASE = 0
>>  PARAMETER C_CLKOUT3_GROUP = NONE
>>  PARAMETER C_CLKOUT4_FREQ = 125000000
>>  PARAMETER C_CLKOUT4_BUF = TRUE
>>  PARAMETER C_CLKOUT4_PHASE = 0
>>  PARAMETER C_CLKOUT4_GROUP = NONE
>>  PORT CLKOUT0 = sys_clk_s
>>  PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_90_s
>>  PORT CLKOUT2 = proc_clk_s
>>  PORT CLKOUT3 = clk_200mhz_s
>>  PORT CLKOUT4 = temac_clk_s
>>  PORT CLKIN = dcm_clk_s
>>  PORT LOCKED = Dcm_all_locked
>>  PORT RST = net_gnd
>> END
>>
>> BEGIN proc_sys_reset
>>  PARAMETER INSTANCE = proc_sys_reset_0
>>  PARAMETER HW_VER = 2.00.a
>>  PARAMETER C_EXT_RESET_HIGH = 0
>>  BUS_INTERFACE RESETPPC0 = ppc_reset_bus
>>  PORT Slowest_sync_clk = sys_clk_s
>>  PORT Dcm_locked = Dcm_all_locked
>>  PORT Ext_Reset_In = sys_rst_s
>>  PORT Bus_Struct_Reset = sys_bus_reset
>>  PORT Peripheral_Reset = sys_periph_reset
>> END
>>
>> BEGIN xps_intc
>>  PARAMETER INSTANCE = xps_intc_0
>>  PARAMETER HW_VER = 1.00.a
>>  PARAMETER C_BASEADDR = 0x81800000
>>  PARAMETER C_HIGHADDR = 0x8180ffff
>>  BUS_INTERFACE SPLB = plb
>>  PORT Irq = EICC405EXTINPUTIRQ
>>  PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt & IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut & DDR_SDRAM_SDMA2_Tx_IntOut
>> END
>>
>>
>>
>> 	#address-cells = <1>;
>> 	#size-cells = <1>;
>> 	compatible = "xlnx,virtex";
>> 	model = "testing";
>> 	DDR_SDRAM: memory@0 {
>> 		device_type = "memory";
>> 		reg = < 0 8000000 >;
>> 	} ;
>> 	chosen {
>> 		bootargs = "console=ttyS0,9600 ip=on nfsroot=172.16.40.76:/v2pclients/jhl26,tcp"; 
>> 		linux,stdout-path = "/plb@0/serial@83e00000";
>> 	} ;
>> 	cpus {
>> 		#address-cells = <1>;
>> 		#cpus = <1>;
>> 		#size-cells = <0>;
>> 		ppc405_0: cpu@0 {
>> 			clock-frequency = <11e1a300>;
>> 			compatible = "PowerPC,405", "ibm,ppc405";
>> 			d-cache-line-size = <20>;
>> 			d-cache-size = <4000>;
>> 			device_type = "cpu";
>> 			i-cache-line-size = <20>;
>> 			i-cache-size = <4000>;
>> 			model = "PowerPC,405";
>> 			reg = <0>;
>> 			timebase-frequency = <11e1a300>;
>> 			xlnx,apu-control = <de00>;
>> 			xlnx,apu-udi-1 = <a18983>;
>> 			xlnx,apu-udi-2 = <a38983>;
>> 			xlnx,apu-udi-3 = <a589c3>;
>> 			xlnx,apu-udi-4 = <a789c3>;
>> 			xlnx,apu-udi-5 = <a98c03>;
>> 			xlnx,apu-udi-6 = <ab8c03>;
>> 			xlnx,apu-udi-7 = <ad8c43>;
>> 			xlnx,apu-udi-8 = <af8c43>;
>> 			xlnx,deterministic-mult = <0>;
>> 			xlnx,disable-operand-forwarding = <1>;
>> 			xlnx,fastest-plb-clock = "DPLB0";
>> 			xlnx,generate-plb-timespecs = <1>;
>> 			xlnx,mmu-enable = <1>;
>> 			xlnx,pvr-high = <0>;
>> 			xlnx,pvr-low = <0>;
>> 		} ;
>> 	} ;
>> 	plb: plb@0 {
>> 		#address-cells = <1>;
>> 		#size-cells = <1>;
>> 		compatible = "xlnx,plb-v46-1.02.a";
>> 		ranges ;
>> 		IIC_EEPROM: i2c@81600000 {
>> 			compatible = "xlnx,xps-iic-2.00.a";
>> 			interrupt-parent = <&xps_intc_0>;
>> 			interrupts = < 4 2 >;
>> 			reg = < 81600000 10000 >;
>> 			xlnx,clk-freq = <5f5e100>;
>> 			xlnx,family = "virtex4";
>> 			xlnx,gpo-width = <1>;
>> 			xlnx,iic-freq = <186a0>;
>> 			xlnx,scl-inertial-delay = <0>;
>> 			xlnx,sda-inertial-delay = <0>;
>> 			xlnx,ten-bit-adr = <0>;
>> 		} ;
>> 		LEDs_4Bit: gpio@81400000 {
>> 			compatible = "xlnx,xps-gpio-1.00.a";
>> 			interrupt-parent = <&xps_intc_0>;
>> 			interrupts = < 5 2 >;
>> 			reg = < 81400000 10000 >;
>> 			xlnx,all-inputs = <0>;
>> 			xlnx,all-inputs-2 = <0>;
>> 			xlnx,dout-default = <0>;
>> 			xlnx,dout-default-2 = <0>;
>> 			xlnx,family = "virtex4";
>> 			xlnx,gpio-width = <4>;
>> 			xlnx,interrupt-present = <1>;
>> 			xlnx,is-bidir = <1>;
>> 			xlnx,is-bidir-2 = <1>;
>> 			xlnx,is-dual = <0>;
>> 			xlnx,tri-default = <ffffffff>;
>> 			xlnx,tri-default-2 = <ffffffff>;
>> 		} ;
>> 		RS232_Uart: serial@83e00000 {
>> 			compatible = "xlnx,xps-uart16550-2.00.a";
>> //			compatible = "ns16550"; 
>> 			device_type = "serial";
>> 			interrupt-parent = <&xps_intc_0>; 
>> 			interrupts = < 6 2 >; 
>> 			reg = < 83e00000 10000 >;
>> 			current-speed = <d#9600>;
>> 			clock-frequency = <d#100000000>;  /* added by jhl */
>> 			reg-shift = <2>;
>> 			xlnx,family = "virtex4";
>> 			xlnx,has-external-rclk = <0>;
>> 			xlnx,has-external-xin = <0>;
>> 			xlnx,is-a-16550 = <1>;
>> 		} ;
>> 		SysACE_CompactFlash: sysace@83600000 {
>> 			compatible = "xlnx,xps-sysace-1.00.a";
>> 			interrupt-parent = <&xps_intc_0>;
>> 			interrupts = < 3 2 >;
>> 			reg = < 83600000 10000 >;
>> 			xlnx,family = "virtex4";
>> 			xlnx,mem-width = <10>;
>> 		} ;
>> 		TriMode_MAC_GMII: xps-ll-temac@81c00000 {
>> 			#address-cells = <1>;
>> 			#size-cells = <1>;
>> 			compatible = "xlnx,compound";
>> 			ethernet@81c00000 {
>> 				compatible = "xlnx,xps-ll-temac-1.01.a";
>> 				device_type = "network";
>> 				interrupt-parent = <&xps_intc_0>;
>> 				interrupts = < 2 2 >;
>> 				llink-connected = <&PIM2>;
>> 				local-mac-address = [ 02 00 00 00 00 01 ];
>> 				reg = < 81c00000 40 >;
>> 				xlnx,bus2core-clk-ratio = <1>;
>> 				xlnx,phy-type = <1>;
>> 				xlnx,phyaddr = <1>;
>> 				xlnx,rxcsum = <0>;
>> 				xlnx,rxfifo = <1000>;
>> 				xlnx,temac-type = <1>;
>> 				xlnx,txcsum = <0>;
>> 				xlnx,txfifo = <1000>;
>> 			} ;
>> 		} ;
>> 		mpmc@0 {
>> 			#address-cells = <1>;
>> 			#size-cells = <1>;
>> 			compatible = "xlnx,mpmc-4.00.a";
>> 			PIM2: sdma@84600100 {
>> 				compatible = "xlnx,ll-dma-1.00.a";
>> 				interrupt-parent = <&xps_intc_0>;
>> 				interrupts = < 1 2 0 2 >;
>> 				reg = < 84600100 80 >;
>> 			} ;
>> 		} ;
>> 		xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {
>> 			compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
>> 			reg = < ffffe000 2000 >;
>> 			xlnx,family = "virtex4";
>> 		} ;
>> 		xps_intc_0: interrupt-controller@81800000 {
>> 			#interrupt-cells = <2>;
>> 			compatible = "xlnx,xps-intc-1.00.a";
>> 			interrupt-controller ;
>> 			reg = < 81800000 10000 >;
>> 			xlnx,num-intr-inputs = <7>;
>> 		} ;
>> 	} ;
>> 	ppc405_0_dplb1: plb@1 {
>> 		#address-cells = <1>;
>> 		#size-cells = <1>;
>> 		compatible = "xlnx,plb-v46-1.02.a";
>> 		ranges ;
>> 	} ;
>> }  ;
>>
>>
>>
>> -----Original Message-----
>> From: Magnus Hjorth [mailto:mh@omnisys.se] 
>> Sent: Saturday, March 29, 2008 6:54 AM
>> To: git
>> Cc: linuxppc-embedded@ozlabs.org
>> Subject: Xilinx LLTEMAC driver issues
>>
>> Hi,
>>
>> I'm having some networking troubles with the Xilinx LLTEMAC driver from the
>> Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
>> xps_ll_temac v1.00.b 
>>
>> The weird thing is, that it sort of half works. It successfully makes a DHCP
>> request and gets its IP address. I tried setting up a tftpd server, and I can
>> see UDP requests coming in but the response doesn't seem to come out. I also
>> tried running a TCP server on the board, and it can see and accept incoming
>> connections but after that no data seems to get through. I can ping out and
>> get around 40% packet loss.
>>
>> Looking at /proc/interrupts, I can see both TxDma interrupts and RxDma
>> interrupts. No eth0 interrupts but that seems to be OK judging by the driver
>> source comments. Ifconfig shows no collistions, no dropped packets, no errors,
>> so the system seems to think that everything is OK. 
>>
>> Clues anyone? I'm starting to run out of ideas...
>>
>> Best regards,
>> Magnus
>>
>>
>> --
>>
>> Magnus Hjorth, M.Sc.
>> Omnisys Instruments AB
>> Gruvgatan 8
>> SE-421 30  Västra Frölunda, SWEDEN
>> Phone: +46 31 734 34 09
>> Fax: +46 31 734 34 29
>> http://www.omnisys.se
>>     
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded

RE: Xilinx LLTEMAC driver issues

[Magnus Hjorth]

Deactivating checksum offloading helped a lot! I still have some packet =
loss and not the best performance (TFTP transfer about 100 kbyte/s) but =
at least it works.=20

Thanks!

//Magnus

> -----Original Message-----
> From: rza1 [mailto:rza1@so-logic.net]
> Sent: den 31 mars 2008 11:14
> To: Magnus Hjorth
> Cc: John Linn; git; linuxppc-embedded@ozlabs.org
> Subject: Re: Xilinx LLTEMAC driver issues
>=20
> Hi Magnus,
>=20
> 1.
> I am using nearly the same versions then you and got the same problems
> too ;-).
> I think there are some problems with the checksum offloading.
> Try to sniff the some packages (e.g. wireshark)...
> For me ICMP (ping) worked but udp and tcp not (because off a wrong
> checksum in the transport layer).
> A quick solution is to just deactivate checksum offloading.
>=20
> 2.
> I remember some problems with Virtex-4 presamples too.
> There where problems with the hard-temac wrapper. You had to use =
1.00.a
> and not b version.
> But I don't have these problems with the EDK 9.2sp2/ISE9.2sp3 anymore.
>=20
> all the best,
> Robert
>=20
> Magnus Hjorth wrote:
> > Hi John,
> >
> > Thanks for the very fast reply! Right now I'm not at work so I don't
> > have the board or EDK here to test anything.
> >
> > I'm using checksum offload, but I don't know if DRE is enabled or =
not. I
> > can't recall seeing any setting to enable/disable DRE..
> >
> > A few things that crossed my mind:
> >
> > Last year I did a design with EDK 8.2, back then there was an issue =
with
> > the ML403 boards having an old revision of the FPGA which wasn't
> > compatible with some versions of the IP core. There are no such =
version
> > issues with the xps_ll_temac?
> >
> > I don't think that I had phy-addr set in the DTS file. Will test =
that on
> > Monday.
> >
> > Best regards,
> > Magnus
> >
> >
> > On Sat, 2008-03-29 at 07:58 -0600, John Linn wrote:
> >
> >> Hi Magnus,
> >>
> >> Sorry to hear you're having problems with it.
> >>
> >> I am doing testing on an ML405 which is the same board but with a =
bigger
> FPGA, but with ppc arch and I don't see this issue. I have done =
limited testing
> with powerpc arch and the LL TEMAC, but I didn't see this issue there =
either.
> Powerpc arch is definitely less mature in my experience than the ppc =
arch. I'll
> do a quick test with my powerpc arch and make sure again I'm not =
seeing it.
> >>
> >> My kernel is from the Xilinx Git tree, but there have been a number =
of
> changes we have pushed out so I don't know how long ago you pulled =
from the Git
> tree.
> >>
> >> My EDK project is 10.1 so it's a little newer. I am using LL TEMAC =
1.01a so
> it's a little newer.  I reviewed the change log for the LL TEMAC and =
don't see
> any big problems that were fixed in the newer versions, more new =
features.  I'll
> check with some others here to see if I missed something there.
> >>
> >> I am using DMA also, but no DRE or checksum offload.  You didn't =
say anything
> about those. I'm going to insert my mhs file that describes my system =
to let you
> compare your system configuration. It's not clear to me yet if you =
have a h/w or
> s/w problem.
> >>
> >> I'll also insert some of my device tree with the LL TEMAC so you =
can compare
> (ignore 16550 stuff as we are still working on that).
> >>
> >> Since you can't ping reliably I would probably focus on that since =
it's
> simpler than the other issues you're seeing.
> >>
> >> Thanks,
> >> John
> >>
> >>
> >>
> >> #
> =
#########################################################################=
#####
> >> # Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build
> EDK_K_SP1.1
> >> # Thu Feb 14 14:11:12 2008
> >> # Target Board:  Xilinx Virtex 4 ML405 Evaluation Platform Rev 1
> >> # Family:    virtex4
> >> # Device:    xc4vfx20
> >> # Package:   ff672
> >> # Speed Grade:  -10
> >> # Processor: ppc405_0
> >> # Processor clock frequency: 300.00 MHz
> >> # Bus clock frequency: 100.00 MHz
> >> # On Chip Memory :   8 KB
> >> # Total Off Chip Memory : 128 MB
> >> # - DDR_SDRAM =3D 128 MB
> >> #
> =
#########################################################################=
#####
> >>  PARAMETER VERSION =3D 2.1.0
> >>
> >>
> >>  PORT fpga_0_RS232_Uart_sin_pin =3D fpga_0_RS232_Uart_sin, DIR =3D =
I
> >>  PORT fpga_0_RS232_Uart_sout_pin =3D fpga_0_RS232_Uart_sout, DIR =
=3D O
> >>  PORT fpga_0_LEDs_4Bit_GPIO_IO_pin =3D fpga_0_LEDs_4Bit_GPIO_IO, =
DIR =3D IO, VEC
> =3D [0:3]
> >>  PORT fpga_0_IIC_EEPROM_Scl_pin =3D fpga_0_IIC_EEPROM_Scl, DIR =3D =
IO
> >>  PORT fpga_0_IIC_EEPROM_Sda_pin =3D fpga_0_IIC_EEPROM_Sda, DIR =3D =
IO
> >>  PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR =3D I
> >>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR =3D O, VEC =3D [6:1]
> >>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR =3D IO, VEC =3D [15:0]
> >>  PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR =3D O
> >>  PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR =3D O
> >>  PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR =3D O
> >>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR =3D I
> >>  PORT fpga_0_DDR_SDRAM_DDR_Clk_pin =3D fpga_0_DDR_SDRAM_DDR_Clk, =
DIR =3D O
> >>  PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin =3D =
fpga_0_DDR_SDRAM_DDR_Clk_n, DIR =3D O
> >>  PORT fpga_0_DDR_SDRAM_DDR_Addr_pin =3D fpga_0_DDR_SDRAM_DDR_Addr, =
DIR =3D O, VEC
> =3D [12:0]
> >>  PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =3D =
fpga_0_DDR_SDRAM_DDR_BankAddr, DIR
> =3D O, VEC =3D [1:0]
> >>  PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin =3D =
fpga_0_DDR_SDRAM_DDR_CAS_n, DIR =3D O
> >>  PORT fpga_0_DDR_SDRAM_DDR_CE_pin =3D fpga_0_DDR_SDRAM_DDR_CE, DIR =
=3D O
> >>  PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin =3D fpga_0_DDR_SDRAM_DDR_CS_n, =
DIR =3D O
> >>  PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin =3D =
fpga_0_DDR_SDRAM_DDR_RAS_n, DIR =3D O
> >>  PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin =3D fpga_0_DDR_SDRAM_DDR_WE_n, =
DIR =3D O
> >>  PORT fpga_0_DDR_SDRAM_DDR_DM_pin =3D fpga_0_DDR_SDRAM_DDR_DM, DIR =
=3D O, VEC =3D
> [3:0]
> >>  PORT fpga_0_DDR_SDRAM_DDR_DQS =3D fpga_0_DDR_SDRAM_DDR_DQS, DIR =
=3D IO, VEC =3D
> [3:0]
> >>  PORT fpga_0_DDR_SDRAM_DDR_DQ =3D fpga_0_DDR_SDRAM_DDR_DQ, DIR =3D =
IO, VEC =3D
> [31:0]
> >>  PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR =3D O, VEC =3D [7:0]
> >>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR =3D O
> >>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR =3D O
> >>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR =3D O
> >>  PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR =3D I, VEC =3D [7:0]
> >>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR =3D I
> >>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR =3D I
> >>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR =3D I
> >>  PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin =3D
> fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR =3D I
> >>  PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin =3D =
fpga_0_TriMode_MAC_GMII_MDIO_0,
> DIR =3D IO
> >>  PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin =3D =
fpga_0_TriMode_MAC_GMII_MDC_0, DIR
> =3D O
> >>  PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin =3D
> fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR =3D O
> >>  PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D CLK, CLK_FREQ =
=3D 100000000
> >>  PORT sys_rst_pin =3D sys_rst_s, DIR =3D I, RST_POLARITY =3D 0, =
SIGIS =3D RST
> >>
> >>
> >> BEGIN ppc405_virtex4
> >>  PARAMETER INSTANCE =3D ppc405_0
> >>  PARAMETER HW_VER =3D 2.01.a
> >>  PARAMETER C_FASTEST_PLB_CLOCK =3D DPLB1
> >>  PARAMETER C_IDCR_BASEADDR =3D 0b0100000000
> >>  PARAMETER C_IDCR_HIGHADDR =3D 0b0111111111
> >>  BUS_INTERFACE JTAGPPC =3D jtagppc_0_0
> >>  BUS_INTERFACE IPLB0 =3D plb
> >>  BUS_INTERFACE DPLB0 =3D plb
> >>  BUS_INTERFACE IPLB1 =3D ppc405_0_iplb1
> >>  BUS_INTERFACE DPLB1 =3D ppc405_0_dplb1
> >>  BUS_INTERFACE RESETPPC =3D ppc_reset_bus
> >>  PORT CPMC405CLOCK =3D proc_clk_s
> >>  PORT EICC405EXTINPUTIRQ =3D EICC405EXTINPUTIRQ
> >> END
> >>
> >> BEGIN jtagppc_cntlr
> >>  PARAMETER INSTANCE =3D jtagppc_0
> >>  PARAMETER HW_VER =3D 2.01.a
> >>  BUS_INTERFACE JTAGPPC0 =3D jtagppc_0_0
> >> END
> >>
> >> BEGIN plb_v46
> >>  PARAMETER INSTANCE =3D plb
> >>  PARAMETER C_DCR_INTFCE =3D 0
> >>  PARAMETER C_NUM_CLK_PLB2OPB_REARB =3D 100
> >>  PARAMETER HW_VER =3D 1.02.a
> >>  PORT PLB_Clk =3D sys_clk_s
> >>  PORT SYS_Rst =3D sys_bus_reset
> >> END
> >>
> >> BEGIN xps_bram_if_cntlr
> >>  PARAMETER INSTANCE =3D xps_bram_if_cntlr_1
> >>  PARAMETER HW_VER =3D 1.00.a
> >>  PARAMETER C_SPLB_NATIVE_DWIDTH =3D 64
> >>  PARAMETER C_BASEADDR =3D 0xffffe000
> >>  PARAMETER C_HIGHADDR =3D 0xffffffff
> >>  BUS_INTERFACE SPLB =3D plb
> >>  BUS_INTERFACE PORTA =3D xps_bram_if_cntlr_1_port
> >> END
> >>
> >> BEGIN bram_block
> >>  PARAMETER INSTANCE =3D plb_bram_if_cntlr_1_bram
> >>  PARAMETER HW_VER =3D 1.00.a
> >>  BUS_INTERFACE PORTA =3D xps_bram_if_cntlr_1_port
> >> END
> >>
> >> BEGIN xps_uart16550
> >>  PARAMETER INSTANCE =3D RS232_Uart
> >>  PARAMETER HW_VER =3D 2.00.a
> >>  PARAMETER C_IS_A_16550 =3D 1
> >>  PARAMETER C_BASEADDR =3D 0x83e00000
> >>  PARAMETER C_HIGHADDR =3D 0x83e0ffff
> >>  BUS_INTERFACE SPLB =3D plb
> >>  PORT sin =3D fpga_0_RS232_Uart_sin
> >>  PORT sout =3D fpga_0_RS232_Uart_sout
> >>  PORT IP2INTC_Irpt =3D RS232_Uart_IP2INTC_Irpt
> >> END
> >>
> >> BEGIN xps_gpio
> >>  PARAMETER INSTANCE =3D LEDs_4Bit
> >>  PARAMETER HW_VER =3D 1.00.a
> >>  PARAMETER C_INTERRUPT_PRESENT =3D 1
> >>  PARAMETER C_GPIO_WIDTH =3D 4
> >>  PARAMETER C_IS_DUAL =3D 0
> >>  PARAMETER C_IS_BIDIR =3D 1
> >>  PARAMETER C_ALL_INPUTS =3D 0
> >>  PARAMETER C_BASEADDR =3D 0x81400000
> >>  PARAMETER C_HIGHADDR =3D 0x8140ffff
> >>  BUS_INTERFACE SPLB =3D plb
> >>  PORT GPIO_IO =3D fpga_0_LEDs_4Bit_GPIO_IO
> >>  PORT IP2INTC_Irpt =3D LEDs_4Bit_IP2INTC_Irpt
> >> END
> >>
> >> BEGIN xps_iic
> >>  PARAMETER INSTANCE =3D IIC_EEPROM
> >>  PARAMETER HW_VER =3D 2.00.a
> >>  PARAMETER C_CLK_FREQ =3D 100000000
> >>  PARAMETER C_IIC_FREQ =3D 100000
> >>  PARAMETER C_TEN_BIT_ADR =3D 0
> >>  PARAMETER C_BASEADDR =3D 0x81600000
> >>  PARAMETER C_HIGHADDR =3D 0x8160ffff
> >>  BUS_INTERFACE SPLB =3D plb
> >>  PORT Scl =3D fpga_0_IIC_EEPROM_Scl
> >>  PORT Sda =3D fpga_0_IIC_EEPROM_Sda
> >>  PORT IIC2INTC_Irpt =3D IIC_EEPROM_IIC2INTC_Irpt
> >> END
> >>
> >> BEGIN xps_sysace
> >>  PARAMETER INSTANCE =3D SysACE_CompactFlash
> >>  PARAMETER HW_VER =3D 1.00.a
> >>  PARAMETER C_MEM_WIDTH =3D 16
> >>  PARAMETER C_BASEADDR =3D 0x83600000
> >>  PARAMETER C_HIGHADDR =3D 0x8360ffff
> >>  BUS_INTERFACE SPLB =3D plb
> >>  PORT SysACE_CLK =3D fpga_0_SysACE_CompactFlash_SysACE_CLK
> >>  PORT SysACE_MPA =3D fpga_0_SysACE_CompactFlash_SysACE_MPA_split
> >>  PORT SysACE_MPD =3D fpga_0_SysACE_CompactFlash_SysACE_MPD
> >>  PORT SysACE_CEN =3D fpga_0_SysACE_CompactFlash_SysACE_CEN
> >>  PORT SysACE_OEN =3D fpga_0_SysACE_CompactFlash_SysACE_OEN
> >>  PORT SysACE_WEN =3D fpga_0_SysACE_CompactFlash_SysACE_WEN
> >>  PORT SysACE_MPIRQ =3D fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
> >>  PORT SysACE_IRQ =3D SysACE_CompactFlash_SysACE_IRQ
> >> END
> >>
> >> BEGIN mpmc
> >>  PARAMETER INSTANCE =3D DDR_SDRAM
> >>  PARAMETER HW_VER =3D 4.00.a
> >>  PARAMETER C_NUM_PORTS =3D 3
> >>  PARAMETER C_MEM_PARTNO =3D HYB25D512160BE-5
> >>  PARAMETER C_MEM_DATA_WIDTH =3D 32
> >>  PARAMETER C_MEM_DQS_WIDTH =3D 4
> >>  PARAMETER C_MEM_DM_WIDTH =3D 4
> >>  PARAMETER C_MEM_TYPE =3D DDR
> >>  PARAMETER C_NUM_IDELAYCTRL =3D 2
> >>  PARAMETER C_IDELAYCTRL_LOC =3D IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
> >>  PARAMETER C_PIM0_BASETYPE =3D 2
> >>  PARAMETER C_PIM1_BASETYPE =3D 2
> >>  PARAMETER C_PIM2_BASETYPE =3D 3
> >>  PARAMETER C_MPMC_CLK0_PERIOD_PS =3D 10000
> >>  PARAMETER C_SDMA2_PI2LL_CLK_RATIO =3D 1
> >>  PARAMETER C_MPMC_BASEADDR =3D 0x00000000
> >>  PARAMETER C_MPMC_HIGHADDR =3D 0x07ffffff
> >>  PARAMETER C_SDMA_CTRL_BASEADDR =3D 0x84600000
> >>  PARAMETER C_SDMA_CTRL_HIGHADDR =3D 0x8460ffff
> >>  BUS_INTERFACE SPLB0 =3D ppc405_0_iplb1
> >>  BUS_INTERFACE SPLB1 =3D ppc405_0_dplb1
> >>  BUS_INTERFACE SDMA_LL2 =3D TriMode_MAC_GMII_LLINK0
> >>  BUS_INTERFACE SDMA_CTRL2 =3D plb
> >>  PORT DDR_Addr =3D fpga_0_DDR_SDRAM_DDR_Addr
> >>  PORT DDR_BankAddr =3D fpga_0_DDR_SDRAM_DDR_BankAddr
> >>  PORT DDR_CAS_n =3D fpga_0_DDR_SDRAM_DDR_CAS_n
> >>  PORT DDR_CE =3D fpga_0_DDR_SDRAM_DDR_CE
> >>  PORT DDR_CS_n =3D fpga_0_DDR_SDRAM_DDR_CS_n
> >>  PORT DDR_RAS_n =3D fpga_0_DDR_SDRAM_DDR_RAS_n
> >>  PORT DDR_WE_n =3D fpga_0_DDR_SDRAM_DDR_WE_n
> >>  PORT DDR_DM =3D fpga_0_DDR_SDRAM_DDR_DM
> >>  PORT DDR_DQS =3D fpga_0_DDR_SDRAM_DDR_DQS
> >>  PORT DDR_DQ =3D fpga_0_DDR_SDRAM_DDR_DQ
> >>  PORT DDR_Clk =3D fpga_0_DDR_SDRAM_DDR_Clk
> >>  PORT DDR_Clk_n =3D fpga_0_DDR_SDRAM_DDR_Clk_n
> >>  PORT MPMC_Clk0 =3D sys_clk_s
> >>  PORT MPMC_Clk90 =3D DDR_SDRAM_mpmc_clk_90_s
> >>  PORT SDMA2_Clk =3D sys_clk_s
> >>  PORT MPMC_Clk_200MHz =3D clk_200mhz_s
> >>  PORT MPMC_Rst =3D sys_periph_reset
> >>  PORT SDMA2_Rx_IntOut =3D DDR_SDRAM_SDMA2_Rx_IntOut
> >>  PORT SDMA2_Tx_IntOut =3D DDR_SDRAM_SDMA2_Tx_IntOut
> >> END
> >>
> >> BEGIN xps_ll_temac
> >>  PARAMETER INSTANCE =3D TriMode_MAC_GMII
> >>  PARAMETER HW_VER =3D 1.01.a
> >>  PARAMETER C_SPLB_CLK_PERIOD_PS =3D 10000
> >>  PARAMETER C_PHY_TYPE =3D 1
> >>  PARAMETER C_NUM_IDELAYCTRL =3D 4
> >>  PARAMETER C_IDELAYCTRL_LOC =3D IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-
> IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3
> >>  PARAMETER C_TEMAC_TYPE =3D 1
> >>  PARAMETER C_BUS2CORE_CLK_RATIO =3D 1
> >>  PARAMETER C_BASEADDR =3D 0x81c00000
> >>  PARAMETER C_HIGHADDR =3D 0x81c0ffff
> >>  BUS_INTERFACE SPLB =3D plb
> >>  BUS_INTERFACE LLINK0 =3D TriMode_MAC_GMII_LLINK0
> >>  PORT GMII_TXD_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TXD_0
> >>  PORT GMII_TX_EN_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0
> >>  PORT GMII_TX_ER_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0
> >>  PORT GMII_TX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0
> >>  PORT GMII_RXD_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RXD_0
> >>  PORT GMII_RX_DV_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0
> >>  PORT GMII_RX_ER_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0
> >>  PORT GMII_RX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0
> >>  PORT MII_TX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0
> >>  PORT MDIO_0 =3D fpga_0_TriMode_MAC_GMII_MDIO_0
> >>  PORT MDC_0 =3D fpga_0_TriMode_MAC_GMII_MDC_0
> >>  PORT TemacPhy_RST_n =3D fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n
> >>  PORT GTX_CLK_0 =3D temac_clk_s
> >>  PORT REFCLK =3D clk_200mhz_s
> >>  PORT LlinkTemac0_CLK =3D sys_clk_s
> >>  PORT TemacIntc0_Irpt =3D TriMode_MAC_GMII_TemacIntc0_Irpt
> >> END
> >>
> >> BEGIN util_bus_split
> >>  PARAMETER INSTANCE =3D SysACE_CompactFlash_util_bus_split_0
> >>  PARAMETER HW_VER =3D 1.00.a
> >>  PARAMETER C_SIZE_IN =3D 7
> >>  PARAMETER C_LEFT_POS =3D 0
> >>  PARAMETER C_SPLIT =3D 6
> >>  PORT Sig =3D fpga_0_SysACE_CompactFlash_SysACE_MPA_split
> >>  PORT Out1 =3D fpga_0_SysACE_CompactFlash_SysACE_MPA
> >> END
> >>
> >> BEGIN plb_v46
> >>  PARAMETER INSTANCE =3D ppc405_0_iplb1
> >>  PARAMETER HW_VER =3D 1.02.a
> >>  PORT PLB_Clk =3D sys_clk_s
> >>  PORT SYS_Rst =3D sys_bus_reset
> >> END
> >>
> >> BEGIN plb_v46
> >>  PARAMETER INSTANCE =3D ppc405_0_dplb1
> >>  PARAMETER HW_VER =3D 1.02.a
> >>  PORT PLB_Clk =3D sys_clk_s
> >>  PORT SYS_Rst =3D sys_bus_reset
> >> END
> >>
> >> BEGIN clock_generator
> >>  PARAMETER INSTANCE =3D clock_generator_0
> >>  PARAMETER HW_VER =3D 2.00.a
> >>  PARAMETER C_EXT_RESET_HIGH =3D 1
> >>  PARAMETER C_CLKIN_FREQ =3D 100000000
> >>  PARAMETER C_CLKOUT0_FREQ =3D 100000000
> >>  PARAMETER C_CLKOUT0_BUF =3D TRUE
> >>  PARAMETER C_CLKOUT0_PHASE =3D 0
> >>  PARAMETER C_CLKOUT0_GROUP =3D DCM0
> >>  PARAMETER C_CLKOUT1_FREQ =3D 100000000
> >>  PARAMETER C_CLKOUT1_BUF =3D TRUE
> >>  PARAMETER C_CLKOUT1_PHASE =3D 90
> >>  PARAMETER C_CLKOUT1_GROUP =3D DCM0
> >>  PARAMETER C_CLKOUT2_FREQ =3D 300000000
> >>  PARAMETER C_CLKOUT2_BUF =3D TRUE
> >>  PARAMETER C_CLKOUT2_PHASE =3D 0
> >>  PARAMETER C_CLKOUT2_GROUP =3D DCM0
> >>  PARAMETER C_CLKOUT3_FREQ =3D 200000000
> >>  PARAMETER C_CLKOUT3_BUF =3D TRUE
> >>  PARAMETER C_CLKOUT3_PHASE =3D 0
> >>  PARAMETER C_CLKOUT3_GROUP =3D NONE
> >>  PARAMETER C_CLKOUT4_FREQ =3D 125000000
> >>  PARAMETER C_CLKOUT4_BUF =3D TRUE
> >>  PARAMETER C_CLKOUT4_PHASE =3D 0
> >>  PARAMETER C_CLKOUT4_GROUP =3D NONE
> >>  PORT CLKOUT0 =3D sys_clk_s
> >>  PORT CLKOUT1 =3D DDR_SDRAM_mpmc_clk_90_s
> >>  PORT CLKOUT2 =3D proc_clk_s
> >>  PORT CLKOUT3 =3D clk_200mhz_s
> >>  PORT CLKOUT4 =3D temac_clk_s
> >>  PORT CLKIN =3D dcm_clk_s
> >>  PORT LOCKED =3D Dcm_all_locked
> >>  PORT RST =3D net_gnd
> >> END
> >>
> >> BEGIN proc_sys_reset
> >>  PARAMETER INSTANCE =3D proc_sys_reset_0
> >>  PARAMETER HW_VER =3D 2.00.a
> >>  PARAMETER C_EXT_RESET_HIGH =3D 0
> >>  BUS_INTERFACE RESETPPC0 =3D ppc_reset_bus
> >>  PORT Slowest_sync_clk =3D sys_clk_s
> >>  PORT Dcm_locked =3D Dcm_all_locked
> >>  PORT Ext_Reset_In =3D sys_rst_s
> >>  PORT Bus_Struct_Reset =3D sys_bus_reset
> >>  PORT Peripheral_Reset =3D sys_periph_reset
> >> END
> >>
> >> BEGIN xps_intc
> >>  PARAMETER INSTANCE =3D xps_intc_0
> >>  PARAMETER HW_VER =3D 1.00.a
> >>  PARAMETER C_BASEADDR =3D 0x81800000
> >>  PARAMETER C_HIGHADDR =3D 0x8180ffff
> >>  BUS_INTERFACE SPLB =3D plb
> >>  PORT Irq =3D EICC405EXTINPUTIRQ
> >>  PORT Intr =3D RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt &
> IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ &
> TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut &
> DDR_SDRAM_SDMA2_Tx_IntOut
> >> END
> >>
> >>
> >>
> >> 	#address-cells =3D <1>;
> >> 	#size-cells =3D <1>;
> >> 	compatible =3D "xlnx,virtex";
> >> 	model =3D "testing";
> >> 	DDR_SDRAM: memory@0 {
> >> 		device_type =3D "memory";
> >> 		reg =3D < 0 8000000 >;
> >> 	} ;
> >> 	chosen {
> >> 		bootargs =3D "console=3DttyS0,9600 ip=3Don
> nfsroot=3D172.16.40.76:/v2pclients/jhl26,tcp";
> >> 		linux,stdout-path =3D "/plb@0/serial@83e00000";
> >> 	} ;
> >> 	cpus {
> >> 		#address-cells =3D <1>;
> >> 		#cpus =3D <1>;
> >> 		#size-cells =3D <0>;
> >> 		ppc405_0: cpu@0 {
> >> 			clock-frequency =3D <11e1a300>;
> >> 			compatible =3D "PowerPC,405", "ibm,ppc405";
> >> 			d-cache-line-size =3D <20>;
> >> 			d-cache-size =3D <4000>;
> >> 			device_type =3D "cpu";
> >> 			i-cache-line-size =3D <20>;
> >> 			i-cache-size =3D <4000>;
> >> 			model =3D "PowerPC,405";
> >> 			reg =3D <0>;
> >> 			timebase-frequency =3D <11e1a300>;
> >> 			xlnx,apu-control =3D <de00>;
> >> 			xlnx,apu-udi-1 =3D <a18983>;
> >> 			xlnx,apu-udi-2 =3D <a38983>;
> >> 			xlnx,apu-udi-3 =3D <a589c3>;
> >> 			xlnx,apu-udi-4 =3D <a789c3>;
> >> 			xlnx,apu-udi-5 =3D <a98c03>;
> >> 			xlnx,apu-udi-6 =3D <ab8c03>;
> >> 			xlnx,apu-udi-7 =3D <ad8c43>;
> >> 			xlnx,apu-udi-8 =3D <af8c43>;
> >> 			xlnx,deterministic-mult =3D <0>;
> >> 			xlnx,disable-operand-forwarding =3D <1>;
> >> 			xlnx,fastest-plb-clock =3D "DPLB0";
> >> 			xlnx,generate-plb-timespecs =3D <1>;
> >> 			xlnx,mmu-enable =3D <1>;
> >> 			xlnx,pvr-high =3D <0>;
> >> 			xlnx,pvr-low =3D <0>;
> >> 		} ;
> >> 	} ;
> >> 	plb: plb@0 {
> >> 		#address-cells =3D <1>;
> >> 		#size-cells =3D <1>;
> >> 		compatible =3D "xlnx,plb-v46-1.02.a";
> >> 		ranges ;
> >> 		IIC_EEPROM: i2c@81600000 {
> >> 			compatible =3D "xlnx,xps-iic-2.00.a";
> >> 			interrupt-parent =3D <&xps_intc_0>;
> >> 			interrupts =3D < 4 2 >;
> >> 			reg =3D < 81600000 10000 >;
> >> 			xlnx,clk-freq =3D <5f5e100>;
> >> 			xlnx,family =3D "virtex4";
> >> 			xlnx,gpo-width =3D <1>;
> >> 			xlnx,iic-freq =3D <186a0>;
> >> 			xlnx,scl-inertial-delay =3D <0>;
> >> 			xlnx,sda-inertial-delay =3D <0>;
> >> 			xlnx,ten-bit-adr =3D <0>;
> >> 		} ;
> >> 		LEDs_4Bit: gpio@81400000 {
> >> 			compatible =3D "xlnx,xps-gpio-1.00.a";
> >> 			interrupt-parent =3D <&xps_intc_0>;
> >> 			interrupts =3D < 5 2 >;
> >> 			reg =3D < 81400000 10000 >;
> >> 			xlnx,all-inputs =3D <0>;
> >> 			xlnx,all-inputs-2 =3D <0>;
> >> 			xlnx,dout-default =3D <0>;
> >> 			xlnx,dout-default-2 =3D <0>;
> >> 			xlnx,family =3D "virtex4";
> >> 			xlnx,gpio-width =3D <4>;
> >> 			xlnx,interrupt-present =3D <1>;
> >> 			xlnx,is-bidir =3D <1>;
> >> 			xlnx,is-bidir-2 =3D <1>;
> >> 			xlnx,is-dual =3D <0>;
> >> 			xlnx,tri-default =3D <ffffffff>;
> >> 			xlnx,tri-default-2 =3D <ffffffff>;
> >> 		} ;
> >> 		RS232_Uart: serial@83e00000 {
> >> 			compatible =3D "xlnx,xps-uart16550-2.00.a";
> >> //			compatible =3D "ns16550";
> >> 			device_type =3D "serial";
> >> 			interrupt-parent =3D <&xps_intc_0>;
> >> 			interrupts =3D < 6 2 >;
> >> 			reg =3D < 83e00000 10000 >;
> >> 			current-speed =3D <d#9600>;
> >> 			clock-frequency =3D <d#100000000>;  /* added
> by jhl */
> >> 			reg-shift =3D <2>;
> >> 			xlnx,family =3D "virtex4";
> >> 			xlnx,has-external-rclk =3D <0>;
> >> 			xlnx,has-external-xin =3D <0>;
> >> 			xlnx,is-a-16550 =3D <1>;
> >> 		} ;
> >> 		SysACE_CompactFlash: sysace@83600000 {
> >> 			compatible =3D "xlnx,xps-sysace-1.00.a";
> >> 			interrupt-parent =3D <&xps_intc_0>;
> >> 			interrupts =3D < 3 2 >;
> >> 			reg =3D < 83600000 10000 >;
> >> 			xlnx,family =3D "virtex4";
> >> 			xlnx,mem-width =3D <10>;
> >> 		} ;
> >> 		TriMode_MAC_GMII: xps-ll-temac@81c00000 {
> >> 			#address-cells =3D <1>;
> >> 			#size-cells =3D <1>;
> >> 			compatible =3D "xlnx,compound";
> >> 			ethernet@81c00000 {
> >> 				compatible =3D "xlnx,xps-ll-temac-
> 1.01.a";
> >> 				device_type =3D "network";
> >> 				interrupt-parent =3D
> <&xps_intc_0>;
> >> 				interrupts =3D < 2 2 >;
> >> 				llink-connected =3D <&PIM2>;
> >> 				local-mac-address =3D [ 02 00 00
> 00 00 01 ];
> >> 				reg =3D < 81c00000 40 >;
> >> 				xlnx,bus2core-clk-ratio =3D <1>;
> >> 				xlnx,phy-type =3D <1>;
> >> 				xlnx,phyaddr =3D <1>;
> >> 				xlnx,rxcsum =3D <0>;
> >> 				xlnx,rxfifo =3D <1000>;
> >> 				xlnx,temac-type =3D <1>;
> >> 				xlnx,txcsum =3D <0>;
> >> 				xlnx,txfifo =3D <1000>;
> >> 			} ;
> >> 		} ;
> >> 		mpmc@0 {
> >> 			#address-cells =3D <1>;
> >> 			#size-cells =3D <1>;
> >> 			compatible =3D "xlnx,mpmc-4.00.a";
> >> 			PIM2: sdma@84600100 {
> >> 				compatible =3D "xlnx,ll-dma-
> 1.00.a";
> >> 				interrupt-parent =3D
> <&xps_intc_0>;
> >> 				interrupts =3D < 1 2 0 2 >;
> >> 				reg =3D < 84600100 80 >;
> >> 			} ;
> >> 		} ;
> >> 		xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {
> >> 			compatible =3D "xlnx,xps-bram-if-cntlr-
> 1.00.a";
> >> 			reg =3D < ffffe000 2000 >;
> >> 			xlnx,family =3D "virtex4";
> >> 		} ;
> >> 		xps_intc_0: interrupt-controller@81800000 {
> >> 			#interrupt-cells =3D <2>;
> >> 			compatible =3D "xlnx,xps-intc-1.00.a";
> >> 			interrupt-controller ;
> >> 			reg =3D < 81800000 10000 >;
> >> 			xlnx,num-intr-inputs =3D <7>;
> >> 		} ;
> >> 	} ;
> >> 	ppc405_0_dplb1: plb@1 {
> >> 		#address-cells =3D <1>;
> >> 		#size-cells =3D <1>;
> >> 		compatible =3D "xlnx,plb-v46-1.02.a";
> >> 		ranges ;
> >> 	} ;
> >> }  ;
> >>
> >>
> >>
> >> -----Original Message-----
> >> From: Magnus Hjorth [mailto:mh@omnisys.se]
> >> Sent: Saturday, March 29, 2008 6:54 AM
> >> To: git
> >> Cc: linuxppc-embedded@ozlabs.org
> >> Subject: Xilinx LLTEMAC driver issues
> >>
> >> Hi,
> >>
> >> I'm having some networking troubles with the Xilinx LLTEMAC driver =
from the
> >> Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
> >> xps_ll_temac v1.00.b
> >>
> >> The weird thing is, that it sort of half works. It successfully =
makes a DHCP
> >> request and gets its IP address. I tried setting up a tftpd server, =
and I can
> >> see UDP requests coming in but the response doesn't seem to come =
out. I also
> >> tried running a TCP server on the board, and it can see and accept =
incoming
> >> connections but after that no data seems to get through. I can ping =
out and
> >> get around 40% packet loss.
> >>
> >> Looking at /proc/interrupts, I can see both TxDma interrupts and =
RxDma
> >> interrupts. No eth0 interrupts but that seems to be OK judging by =
the driver
> >> source comments. Ifconfig shows no collistions, no dropped packets, =
no
> errors,
> >> so the system seems to think that everything is OK.
> >>
> >> Clues anyone? I'm starting to run out of ideas...
> >>
> >> Best regards,
> >> Magnus
> >>
> >>
> >> --
> >>
> >> Magnus Hjorth, M.Sc.
> >> Omnisys Instruments AB
> >> Gruvgatan 8
> >> SE-421 30  V=C3=A4stra Fr=C3=B6lunda, SWEDEN
> >> Phone: +46 31 734 34 09
> >> Fax: +46 31 734 34 29
> >> http://www.omnisys.se
> >>
> >
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded

Re: Xilinx LLTEMAC driver issues

[Johann Baudy]

[-- Attachment #1: Type: text/plain, Size: 31267 bytes --]

I've solved this checksum offloading issue with this below patch.
It may help, if you need performance. It certainly needs review but it works
on my side.

--- xilinxgit/drivers/net/xilinx_lltemac/xlltemac_main.c.orig    2008-03-21
09:11:43.000000000 +0100
+++ xilinxgit/drivers/net/xilinx_lltemac/xlltemac_main.c    2008-03-21
09:24:23.000000000 +0100
@@ -133,7 +133,7 @@
         (XLlDma_mBdRead((BdPtr), XLLDMA_BD_STSCTRL_USR0_OFFSET)) &
0xFFFFFFFE )

 #define BdCsumSetup(BdPtr, Start, Insert) \
-    XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, (Start) << 16 |
(Insert))
+    XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, ((Start) << 16) |
(Insert))

 /* Used for debugging */
 #define BdCsumInsert(BdPtr) \
@@ -1540,7 +1541,7 @@ static int xenet_DmaSend_internal(struct
     /*
      * if tx checksum offloading is enabled, when the ethernet stack
      * wants us to perform the checksum in hardware,
-     * skb->ip_summed is CHECKSUM_COMPLETE. Otherwise skb->ip_summed is
+     * skb->ip_summed is CHECKSUM_PARTIAL. Otherwise skb->ip_summed is
      * CHECKSUM_NONE, meaning the checksum is already done, or
      * CHECKSUM_UNNECESSARY, meaning checksumming is turned off (e.g.
      * loopback interface)
@@ -1565,9 +1566,11 @@ static int xenet_DmaSend_internal(struct
      * skb_transport_header(skb) points to the beginning of the ip header
      *
      */
-    if (skb->ip_summed == CHECKSUM_COMPLETE) {
+    if (skb->ip_summed == CHECKSUM_PARTIAL) {
+
+        unsigned int csum_start_off = skb_transport_offset(skb);
+        unsigned int csum_index_off = csum_start_off + skb->csum_offset;

-        unsigned char *raw = skb_transport_header(skb);
 #if 0
         {
             unsigned int csum = _xenet_tx_csum(skb);
@@ -1578,9 +1581,8 @@ static int xenet_DmaSend_internal(struct
         }
 #else
         BdCsumEnable(bd_ptr);
-        BdCsumSetup(bd_ptr, raw - skb->data,
-                (raw - skb->data) + skb->csum);
-
+        BdCsumSetup(bd_ptr, csum_start_off,
+                csum_index_off);
 #endif
         lp->tx_hw_csums++;
     }
@@ -3277,7 +3279,7 @@ static int __devinit xtenet_of_probe(str
     struct resource *r_irq = &r_irq_struct;    /* Interrupt resources */
     struct resource *r_mem = &r_mem_struct;    /* IO mem resources */
     struct xlltemac_platform_data *pdata = &pdata_struct;
-        void *mac_address;
+        const void *mac_address;
     int rc = 0;
     const phandle *llink_connected_handle;
     struct device_node *llink_connected_node;


On Mon, Mar 31, 2008 at 11:10 AM, Magnus Hjorth <mh@omnisys.se> wrote:

> Deactivating checksum offloading helped a lot! I still have some packet
> loss and not the best performance (TFTP transfer about 100 kbyte/s) but at
> least it works.
>
> Thanks!
>
> //Magnus
>
> > -----Original Message-----
> > From: rza1 [mailto:rza1@so-logic.net]
> > Sent: den 31 mars 2008 11:14
> > To: Magnus Hjorth
> > Cc: John Linn; git; linuxppc-embedded@ozlabs.org
> > Subject: Re: Xilinx LLTEMAC driver issues
> >
> > Hi Magnus,
> >
> > 1.
> > I am using nearly the same versions then you and got the same problems
> > too ;-).
> > I think there are some problems with the checksum offloading.
> > Try to sniff the some packages (e.g. wireshark)...
> > For me ICMP (ping) worked but udp and tcp not (because off a wrong
> > checksum in the transport layer).
> > A quick solution is to just deactivate checksum offloading.
> >
> > 2.
> > I remember some problems with Virtex-4 presamples too.
> > There where problems with the hard-temac wrapper. You had to use 1.00.a
> > and not b version.
> > But I don't have these problems with the EDK 9.2sp2/ISE9.2sp3 anymore.
> >
> > all the best,
> > Robert
> >
> > Magnus Hjorth wrote:
> > > Hi John,
> > >
> > > Thanks for the very fast reply! Right now I'm not at work so I don't
> > > have the board or EDK here to test anything.
> > >
> > > I'm using checksum offload, but I don't know if DRE is enabled or not.
> I
> > > can't recall seeing any setting to enable/disable DRE..
> > >
> > > A few things that crossed my mind:
> > >
> > > Last year I did a design with EDK 8.2, back then there was an issue
> with
> > > the ML403 boards having an old revision of the FPGA which wasn't
> > > compatible with some versions of the IP core. There are no such
> version
> > > issues with the xps_ll_temac?
> > >
> > > I don't think that I had phy-addr set in the DTS file. Will test that
> on
> > > Monday.
> > >
> > > Best regards,
> > > Magnus
> > >
> > >
> > > On Sat, 2008-03-29 at 07:58 -0600, John Linn wrote:
> > >
> > >> Hi Magnus,
> > >>
> > >> Sorry to hear you're having problems with it.
> > >>
> > >> I am doing testing on an ML405 which is the same board but with a
> bigger
> > FPGA, but with ppc arch and I don't see this issue. I have done limited
> testing
> > with powerpc arch and the LL TEMAC, but I didn't see this issue there
> either.
> > Powerpc arch is definitely less mature in my experience than the ppc
> arch. I'll
> > do a quick test with my powerpc arch and make sure again I'm not seeing
> it.
> > >>
> > >> My kernel is from the Xilinx Git tree, but there have been a number
> of
> > changes we have pushed out so I don't know how long ago you pulled from
> the Git
> > tree.
> > >>
> > >> My EDK project is 10.1 so it's a little newer. I am using LL TEMAC
> 1.01a so
> > it's a little newer.  I reviewed the change log for the LL TEMAC and
> don't see
> > any big problems that were fixed in the newer versions, more new
> features.  I'll
> > check with some others here to see if I missed something there.
> > >>
> > >> I am using DMA also, but no DRE or checksum offload.  You didn't say
> anything
> > about those. I'm going to insert my mhs file that describes my system to
> let you
> > compare your system configuration. It's not clear to me yet if you have
> a h/w or
> > s/w problem.
> > >>
> > >> I'll also insert some of my device tree with the LL TEMAC so you can
> compare
> > (ignore 16550 stuff as we are still working on that).
> > >>
> > >> Since you can't ping reliably I would probably focus on that since
> it's
> > simpler than the other issues you're seeing.
> > >>
> > >> Thanks,
> > >> John
> > >>
> > >>
> > >>
> > >> #
> >
> ##############################################################################
> > >> # Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build
> > EDK_K_SP1.1
> > >> # Thu Feb 14 14:11:12 2008
> > >> # Target Board:  Xilinx Virtex 4 ML405 Evaluation Platform Rev 1
> > >> # Family:    virtex4
> > >> # Device:    xc4vfx20
> > >> # Package:   ff672
> > >> # Speed Grade:  -10
> > >> # Processor: ppc405_0
> > >> # Processor clock frequency: 300.00 MHz
> > >> # Bus clock frequency: 100.00 MHz
> > >> # On Chip Memory :   8 KB
> > >> # Total Off Chip Memory : 128 MB
> > >> # - DDR_SDRAM = 128 MB
> > >> #
> >
> ##############################################################################
> > >>  PARAMETER VERSION = 2.1.0
> > >>
> > >>
> > >>  PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I
> > >>  PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O
> > >>  PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR =
> IO, VEC
> > = [0:3]
> > >>  PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO
> > >>  PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO
> > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin =
> > fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
> > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin =
> > fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]
> > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin =
> > fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
> > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin =
> > fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
> > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin =
> > fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
> > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin =
> > fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
> > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin =
> > fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
> > >>  PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR =
> O
> > >>  PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n,
> DIR = O
> > >>  PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR
> = O, VEC
> > = [12:0]
> > >>  PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =
> fpga_0_DDR_SDRAM_DDR_BankAddr, DIR
> > = O, VEC = [1:0]
> > >>  PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n,
> DIR = O
> > >>  PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
> > >>  PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR
> = O
> > >>  PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n,
> DIR = O
> > >>  PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR
> = O
> > >>  PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O,
> VEC =
> > [3:0]
> > >>  PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO,
> VEC =
> > [3:0]
> > >>  PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO,
> VEC =
> > [31:0]
> > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin =
> > fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR = O, VEC = [7:0]
> > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin =
> > fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR = O
> > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin =
> > fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR = O
> > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin =
> > fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR = O
> > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin =
> > fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR = I, VEC = [7:0]
> > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin =
> > fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR = I
> > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin =
> > fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR = I
> > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin =
> > fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR = I
> > >>  PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin =
> > fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR = I
> > >>  PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin =
> fpga_0_TriMode_MAC_GMII_MDIO_0,
> > DIR = IO
> > >>  PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin =
> fpga_0_TriMode_MAC_GMII_MDC_0, DIR
> > = O
> > >>  PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin =
> > fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR = O
> > >>  PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =
> 100000000
> > >>  PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
> > >>
> > >>
> > >> BEGIN ppc405_virtex4
> > >>  PARAMETER INSTANCE = ppc405_0
> > >>  PARAMETER HW_VER = 2.01.a
> > >>  PARAMETER C_FASTEST_PLB_CLOCK = DPLB1
> > >>  PARAMETER C_IDCR_BASEADDR = 0b0100000000
> > >>  PARAMETER C_IDCR_HIGHADDR = 0b0111111111
> > >>  BUS_INTERFACE JTAGPPC = jtagppc_0_0
> > >>  BUS_INTERFACE IPLB0 = plb
> > >>  BUS_INTERFACE DPLB0 = plb
> > >>  BUS_INTERFACE IPLB1 = ppc405_0_iplb1
> > >>  BUS_INTERFACE DPLB1 = ppc405_0_dplb1
> > >>  BUS_INTERFACE RESETPPC = ppc_reset_bus
> > >>  PORT CPMC405CLOCK = proc_clk_s
> > >>  PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
> > >> END
> > >>
> > >> BEGIN jtagppc_cntlr
> > >>  PARAMETER INSTANCE = jtagppc_0
> > >>  PARAMETER HW_VER = 2.01.a
> > >>  BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
> > >> END
> > >>
> > >> BEGIN plb_v46
> > >>  PARAMETER INSTANCE = plb
> > >>  PARAMETER C_DCR_INTFCE = 0
> > >>  PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
> > >>  PARAMETER HW_VER = 1.02.a
> > >>  PORT PLB_Clk = sys_clk_s
> > >>  PORT SYS_Rst = sys_bus_reset
> > >> END
> > >>
> > >> BEGIN xps_bram_if_cntlr
> > >>  PARAMETER INSTANCE = xps_bram_if_cntlr_1
> > >>  PARAMETER HW_VER = 1.00.a
> > >>  PARAMETER C_SPLB_NATIVE_DWIDTH = 64
> > >>  PARAMETER C_BASEADDR = 0xffffe000
> > >>  PARAMETER C_HIGHADDR = 0xffffffff
> > >>  BUS_INTERFACE SPLB = plb
> > >>  BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
> > >> END
> > >>
> > >> BEGIN bram_block
> > >>  PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
> > >>  PARAMETER HW_VER = 1.00.a
> > >>  BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
> > >> END
> > >>
> > >> BEGIN xps_uart16550
> > >>  PARAMETER INSTANCE = RS232_Uart
> > >>  PARAMETER HW_VER = 2.00.a
> > >>  PARAMETER C_IS_A_16550 = 1
> > >>  PARAMETER C_BASEADDR = 0x83e00000
> > >>  PARAMETER C_HIGHADDR = 0x83e0ffff
> > >>  BUS_INTERFACE SPLB = plb
> > >>  PORT sin = fpga_0_RS232_Uart_sin
> > >>  PORT sout = fpga_0_RS232_Uart_sout
> > >>  PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt
> > >> END
> > >>
> > >> BEGIN xps_gpio
> > >>  PARAMETER INSTANCE = LEDs_4Bit
> > >>  PARAMETER HW_VER = 1.00.a
> > >>  PARAMETER C_INTERRUPT_PRESENT = 1
> > >>  PARAMETER C_GPIO_WIDTH = 4
> > >>  PARAMETER C_IS_DUAL = 0
> > >>  PARAMETER C_IS_BIDIR = 1
> > >>  PARAMETER C_ALL_INPUTS = 0
> > >>  PARAMETER C_BASEADDR = 0x81400000
> > >>  PARAMETER C_HIGHADDR = 0x8140ffff
> > >>  BUS_INTERFACE SPLB = plb
> > >>  PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
> > >>  PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
> > >> END
> > >>
> > >> BEGIN xps_iic
> > >>  PARAMETER INSTANCE = IIC_EEPROM
> > >>  PARAMETER HW_VER = 2.00.a
> > >>  PARAMETER C_CLK_FREQ = 100000000
> > >>  PARAMETER C_IIC_FREQ = 100000
> > >>  PARAMETER C_TEN_BIT_ADR = 0
> > >>  PARAMETER C_BASEADDR = 0x81600000
> > >>  PARAMETER C_HIGHADDR = 0x8160ffff
> > >>  BUS_INTERFACE SPLB = plb
> > >>  PORT Scl = fpga_0_IIC_EEPROM_Scl
> > >>  PORT Sda = fpga_0_IIC_EEPROM_Sda
> > >>  PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt
> > >> END
> > >>
> > >> BEGIN xps_sysace
> > >>  PARAMETER INSTANCE = SysACE_CompactFlash
> > >>  PARAMETER HW_VER = 1.00.a
> > >>  PARAMETER C_MEM_WIDTH = 16
> > >>  PARAMETER C_BASEADDR = 0x83600000
> > >>  PARAMETER C_HIGHADDR = 0x8360ffff
> > >>  BUS_INTERFACE SPLB = plb
> > >>  PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
> > >>  PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_split
> > >>  PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
> > >>  PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
> > >>  PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
> > >>  PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
> > >>  PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
> > >>  PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
> > >> END
> > >>
> > >> BEGIN mpmc
> > >>  PARAMETER INSTANCE = DDR_SDRAM
> > >>  PARAMETER HW_VER = 4.00.a
> > >>  PARAMETER C_NUM_PORTS = 3
> > >>  PARAMETER C_MEM_PARTNO = HYB25D512160BE-5
> > >>  PARAMETER C_MEM_DATA_WIDTH = 32
> > >>  PARAMETER C_MEM_DQS_WIDTH = 4
> > >>  PARAMETER C_MEM_DM_WIDTH = 4
> > >>  PARAMETER C_MEM_TYPE = DDR
> > >>  PARAMETER C_NUM_IDELAYCTRL = 2
> > >>  PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
> > >>  PARAMETER C_PIM0_BASETYPE = 2
> > >>  PARAMETER C_PIM1_BASETYPE = 2
> > >>  PARAMETER C_PIM2_BASETYPE = 3
> > >>  PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
> > >>  PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 1
> > >>  PARAMETER C_MPMC_BASEADDR = 0x00000000
> > >>  PARAMETER C_MPMC_HIGHADDR = 0x07ffffff
> > >>  PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000
> > >>  PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460ffff
> > >>  BUS_INTERFACE SPLB0 = ppc405_0_iplb1
> > >>  BUS_INTERFACE SPLB1 = ppc405_0_dplb1
> > >>  BUS_INTERFACE SDMA_LL2 = TriMode_MAC_GMII_LLINK0
> > >>  BUS_INTERFACE SDMA_CTRL2 = plb
> > >>  PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
> > >>  PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
> > >>  PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
> > >>  PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
> > >>  PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
> > >>  PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
> > >>  PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
> > >>  PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
> > >>  PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
> > >>  PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
> > >>  PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
> > >>  PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
> > >>  PORT MPMC_Clk0 = sys_clk_s
> > >>  PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
> > >>  PORT SDMA2_Clk = sys_clk_s
> > >>  PORT MPMC_Clk_200MHz = clk_200mhz_s
> > >>  PORT MPMC_Rst = sys_periph_reset
> > >>  PORT SDMA2_Rx_IntOut = DDR_SDRAM_SDMA2_Rx_IntOut
> > >>  PORT SDMA2_Tx_IntOut = DDR_SDRAM_SDMA2_Tx_IntOut
> > >> END
> > >>
> > >> BEGIN xps_ll_temac
> > >>  PARAMETER INSTANCE = TriMode_MAC_GMII
> > >>  PARAMETER HW_VER = 1.01.a
> > >>  PARAMETER C_SPLB_CLK_PERIOD_PS = 10000
> > >>  PARAMETER C_PHY_TYPE = 1
> > >>  PARAMETER C_NUM_IDELAYCTRL = 4
> > >>  PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-
> > IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3
> > >>  PARAMETER C_TEMAC_TYPE = 1
> > >>  PARAMETER C_BUS2CORE_CLK_RATIO = 1
> > >>  PARAMETER C_BASEADDR = 0x81c00000
> > >>  PARAMETER C_HIGHADDR = 0x81c0ffff
> > >>  BUS_INTERFACE SPLB = plb
> > >>  BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_LLINK0
> > >>  PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0
> > >>  PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0
> > >>  PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0
> > >>  PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0
> > >>  PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0
> > >>  PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0
> > >>  PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0
> > >>  PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0
> > >>  PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0
> > >>  PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0
> > >>  PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0
> > >>  PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n
> > >>  PORT GTX_CLK_0 = temac_clk_s
> > >>  PORT REFCLK = clk_200mhz_s
> > >>  PORT LlinkTemac0_CLK = sys_clk_s
> > >>  PORT TemacIntc0_Irpt = TriMode_MAC_GMII_TemacIntc0_Irpt
> > >> END
> > >>
> > >> BEGIN util_bus_split
> > >>  PARAMETER INSTANCE = SysACE_CompactFlash_util_bus_split_0
> > >>  PARAMETER HW_VER = 1.00.a
> > >>  PARAMETER C_SIZE_IN = 7
> > >>  PARAMETER C_LEFT_POS = 0
> > >>  PARAMETER C_SPLIT = 6
> > >>  PORT Sig = fpga_0_SysACE_CompactFlash_SysACE_MPA_split
> > >>  PORT Out1 = fpga_0_SysACE_CompactFlash_SysACE_MPA
> > >> END
> > >>
> > >> BEGIN plb_v46
> > >>  PARAMETER INSTANCE = ppc405_0_iplb1
> > >>  PARAMETER HW_VER = 1.02.a
> > >>  PORT PLB_Clk = sys_clk_s
> > >>  PORT SYS_Rst = sys_bus_reset
> > >> END
> > >>
> > >> BEGIN plb_v46
> > >>  PARAMETER INSTANCE = ppc405_0_dplb1
> > >>  PARAMETER HW_VER = 1.02.a
> > >>  PORT PLB_Clk = sys_clk_s
> > >>  PORT SYS_Rst = sys_bus_reset
> > >> END
> > >>
> > >> BEGIN clock_generator
> > >>  PARAMETER INSTANCE = clock_generator_0
> > >>  PARAMETER HW_VER = 2.00.a
> > >>  PARAMETER C_EXT_RESET_HIGH = 1
> > >>  PARAMETER C_CLKIN_FREQ = 100000000
> > >>  PARAMETER C_CLKOUT0_FREQ = 100000000
> > >>  PARAMETER C_CLKOUT0_BUF = TRUE
> > >>  PARAMETER C_CLKOUT0_PHASE = 0
> > >>  PARAMETER C_CLKOUT0_GROUP = DCM0
> > >>  PARAMETER C_CLKOUT1_FREQ = 100000000
> > >>  PARAMETER C_CLKOUT1_BUF = TRUE
> > >>  PARAMETER C_CLKOUT1_PHASE = 90
> > >>  PARAMETER C_CLKOUT1_GROUP = DCM0
> > >>  PARAMETER C_CLKOUT2_FREQ = 300000000
> > >>  PARAMETER C_CLKOUT2_BUF = TRUE
> > >>  PARAMETER C_CLKOUT2_PHASE = 0
> > >>  PARAMETER C_CLKOUT2_GROUP = DCM0
> > >>  PARAMETER C_CLKOUT3_FREQ = 200000000
> > >>  PARAMETER C_CLKOUT3_BUF = TRUE
> > >>  PARAMETER C_CLKOUT3_PHASE = 0
> > >>  PARAMETER C_CLKOUT3_GROUP = NONE
> > >>  PARAMETER C_CLKOUT4_FREQ = 125000000
> > >>  PARAMETER C_CLKOUT4_BUF = TRUE
> > >>  PARAMETER C_CLKOUT4_PHASE = 0
> > >>  PARAMETER C_CLKOUT4_GROUP = NONE
> > >>  PORT CLKOUT0 = sys_clk_s
> > >>  PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_90_s
> > >>  PORT CLKOUT2 = proc_clk_s
> > >>  PORT CLKOUT3 = clk_200mhz_s
> > >>  PORT CLKOUT4 = temac_clk_s
> > >>  PORT CLKIN = dcm_clk_s
> > >>  PORT LOCKED = Dcm_all_locked
> > >>  PORT RST = net_gnd
> > >> END
> > >>
> > >> BEGIN proc_sys_reset
> > >>  PARAMETER INSTANCE = proc_sys_reset_0
> > >>  PARAMETER HW_VER = 2.00.a
> > >>  PARAMETER C_EXT_RESET_HIGH = 0
> > >>  BUS_INTERFACE RESETPPC0 = ppc_reset_bus
> > >>  PORT Slowest_sync_clk = sys_clk_s
> > >>  PORT Dcm_locked = Dcm_all_locked
> > >>  PORT Ext_Reset_In = sys_rst_s
> > >>  PORT Bus_Struct_Reset = sys_bus_reset
> > >>  PORT Peripheral_Reset = sys_periph_reset
> > >> END
> > >>
> > >> BEGIN xps_intc
> > >>  PARAMETER INSTANCE = xps_intc_0
> > >>  PARAMETER HW_VER = 1.00.a
> > >>  PARAMETER C_BASEADDR = 0x81800000
> > >>  PARAMETER C_HIGHADDR = 0x8180ffff
> > >>  BUS_INTERFACE SPLB = plb
> > >>  PORT Irq = EICC405EXTINPUTIRQ
> > >>  PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt &
> > IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ &
> > TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut &
> > DDR_SDRAM_SDMA2_Tx_IntOut
> > >> END
> > >>
> > >>
> > >>
> > >>    #address-cells = <1>;
> > >>    #size-cells = <1>;
> > >>    compatible = "xlnx,virtex";
> > >>    model = "testing";
> > >>    DDR_SDRAM: memory@0 {
> > >>            device_type = "memory";
> > >>            reg = < 0 8000000 >;
> > >>    } ;
> > >>    chosen {
> > >>            bootargs = "console=ttyS0,9600 ip=on
> > nfsroot=172.16.40.76:/v2pclients/jhl26,tcp";
> > >>            linux,stdout-path = "/plb@0/serial@83e00000";
> > >>    } ;
> > >>    cpus {
> > >>            #address-cells = <1>;
> > >>            #cpus = <1>;
> > >>            #size-cells = <0>;
> > >>            ppc405_0: cpu@0 {
> > >>                    clock-frequency = <11e1a300>;
> > >>                    compatible = "PowerPC,405", "ibm,ppc405";
> > >>                    d-cache-line-size = <20>;
> > >>                    d-cache-size = <4000>;
> > >>                    device_type = "cpu";
> > >>                    i-cache-line-size = <20>;
> > >>                    i-cache-size = <4000>;
> > >>                    model = "PowerPC,405";
> > >>                    reg = <0>;
> > >>                    timebase-frequency = <11e1a300>;
> > >>                    xlnx,apu-control = <de00>;
> > >>                    xlnx,apu-udi-1 = <a18983>;
> > >>                    xlnx,apu-udi-2 = <a38983>;
> > >>                    xlnx,apu-udi-3 = <a589c3>;
> > >>                    xlnx,apu-udi-4 = <a789c3>;
> > >>                    xlnx,apu-udi-5 = <a98c03>;
> > >>                    xlnx,apu-udi-6 = <ab8c03>;
> > >>                    xlnx,apu-udi-7 = <ad8c43>;
> > >>                    xlnx,apu-udi-8 = <af8c43>;
> > >>                    xlnx,deterministic-mult = <0>;
> > >>                    xlnx,disable-operand-forwarding = <1>;
> > >>                    xlnx,fastest-plb-clock = "DPLB0";
> > >>                    xlnx,generate-plb-timespecs = <1>;
> > >>                    xlnx,mmu-enable = <1>;
> > >>                    xlnx,pvr-high = <0>;
> > >>                    xlnx,pvr-low = <0>;
> > >>            } ;
> > >>    } ;
> > >>    plb: plb@0 {
> > >>            #address-cells = <1>;
> > >>            #size-cells = <1>;
> > >>            compatible = "xlnx,plb-v46-1.02.a";
> > >>            ranges ;
> > >>            IIC_EEPROM: i2c@81600000 {
> > >>                    compatible = "xlnx,xps-iic-2.00.a";
> > >>                    interrupt-parent = <&xps_intc_0>;
> > >>                    interrupts = < 4 2 >;
> > >>                    reg = < 81600000 10000 >;
> > >>                    xlnx,clk-freq = <5f5e100>;
> > >>                    xlnx,family = "virtex4";
> > >>                    xlnx,gpo-width = <1>;
> > >>                    xlnx,iic-freq = <186a0>;
> > >>                    xlnx,scl-inertial-delay = <0>;
> > >>                    xlnx,sda-inertial-delay = <0>;
> > >>                    xlnx,ten-bit-adr = <0>;
> > >>            } ;
> > >>            LEDs_4Bit: gpio@81400000 {
> > >>                    compatible = "xlnx,xps-gpio-1.00.a";
> > >>                    interrupt-parent = <&xps_intc_0>;
> > >>                    interrupts = < 5 2 >;
> > >>                    reg = < 81400000 10000 >;
> > >>                    xlnx,all-inputs = <0>;
> > >>                    xlnx,all-inputs-2 = <0>;
> > >>                    xlnx,dout-default = <0>;
> > >>                    xlnx,dout-default-2 = <0>;
> > >>                    xlnx,family = "virtex4";
> > >>                    xlnx,gpio-width = <4>;
> > >>                    xlnx,interrupt-present = <1>;
> > >>                    xlnx,is-bidir = <1>;
> > >>                    xlnx,is-bidir-2 = <1>;
> > >>                    xlnx,is-dual = <0>;
> > >>                    xlnx,tri-default = <ffffffff>;
> > >>                    xlnx,tri-default-2 = <ffffffff>;
> > >>            } ;
> > >>            RS232_Uart: serial@83e00000 {
> > >>                    compatible = "xlnx,xps-uart16550-2.00.a";
> > >> //                 compatible = "ns16550";
> > >>                    device_type = "serial";
> > >>                    interrupt-parent = <&xps_intc_0>;
> > >>                    interrupts = < 6 2 >;
> > >>                    reg = < 83e00000 10000 >;
> > >>                    current-speed = <d#9600>;
> > >>                    clock-frequency = <d#100000000>;  /* added
> > by jhl */
> > >>                    reg-shift = <2>;
> > >>                    xlnx,family = "virtex4";
> > >>                    xlnx,has-external-rclk = <0>;
> > >>                    xlnx,has-external-xin = <0>;
> > >>                    xlnx,is-a-16550 = <1>;
> > >>            } ;
> > >>            SysACE_CompactFlash: sysace@83600000 {
> > >>                    compatible = "xlnx,xps-sysace-1.00.a";
> > >>                    interrupt-parent = <&xps_intc_0>;
> > >>                    interrupts = < 3 2 >;
> > >>                    reg = < 83600000 10000 >;
> > >>                    xlnx,family = "virtex4";
> > >>                    xlnx,mem-width = <10>;
> > >>            } ;
> > >>            TriMode_MAC_GMII: xps-ll-temac@81c00000 {
> > >>                    #address-cells = <1>;
> > >>                    #size-cells = <1>;
> > >>                    compatible = "xlnx,compound";
> > >>                    ethernet@81c00000 {
> > >>                            compatible = "xlnx,xps-ll-temac-
> > 1.01.a";
> > >>                            device_type = "network";
> > >>                            interrupt-parent =
> > <&xps_intc_0>;
> > >>                            interrupts = < 2 2 >;
> > >>                            llink-connected = <&PIM2>;
> > >>                            local-mac-address = [ 02 00 00
> > 00 00 01 ];
> > >>                            reg = < 81c00000 40 >;
> > >>                            xlnx,bus2core-clk-ratio = <1>;
> > >>                            xlnx,phy-type = <1>;
> > >>                            xlnx,phyaddr = <1>;
> > >>                            xlnx,rxcsum = <0>;
> > >>                            xlnx,rxfifo = <1000>;
> > >>                            xlnx,temac-type = <1>;
> > >>                            xlnx,txcsum = <0>;
> > >>                            xlnx,txfifo = <1000>;
> > >>                    } ;
> > >>            } ;
> > >>            mpmc@0 {
> > >>                    #address-cells = <1>;
> > >>                    #size-cells = <1>;
> > >>                    compatible = "xlnx,mpmc-4.00.a";
> > >>                    PIM2: sdma@84600100 {
> > >>                            compatible = "xlnx,ll-dma-
> > 1.00.a";
> > >>                            interrupt-parent =
> > <&xps_intc_0>;
> > >>                            interrupts = < 1 2 0 2 >;
> > >>                            reg = < 84600100 80 >;
> > >>                    } ;
> > >>            } ;
> > >>            xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {
> > >>                    compatible = "xlnx,xps-bram-if-cntlr-
> > 1.00.a";
> > >>                    reg = < ffffe000 2000 >;
> > >>                    xlnx,family = "virtex4";
> > >>            } ;
> > >>            xps_intc_0: interrupt-controller@81800000 {
> > >>                    #interrupt-cells = <2>;
> > >>                    compatible = "xlnx,xps-intc-1.00.a";
> > >>                    interrupt-controller ;
> > >>                    reg = < 81800000 10000 >;
> > >>                    xlnx,num-intr-inputs = <7>;
> > >>            } ;
> > >>    } ;
> > >>    ppc405_0_dplb1: plb@1 {
> > >>            #address-cells = <1>;
> > >>            #size-cells = <1>;
> > >>            compatible = "xlnx,plb-v46-1.02.a";
> > >>            ranges ;
> > >>    } ;
> > >> }  ;
> > >>
> > >>
> > >>
> > >> -----Original Message-----
> > >> From: Magnus Hjorth [mailto:mh@omnisys.se]
> > >> Sent: Saturday, March 29, 2008 6:54 AM
> > >> To: git
> > >> Cc: linuxppc-embedded@ozlabs.org
> > >> Subject: Xilinx LLTEMAC driver issues
> > >>
> > >> Hi,
> > >>
> > >> I'm having some networking troubles with the Xilinx LLTEMAC driver
> from the
> > >> Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
> > >> xps_ll_temac v1.00.b
> > >>
> > >> The weird thing is, that it sort of half works. It successfully makes
> a DHCP
> > >> request and gets its IP address. I tried setting up a tftpd server,
> and I can
> > >> see UDP requests coming in but the response doesn't seem to come out.
> I also
> > >> tried running a TCP server on the board, and it can see and accept
> incoming
> > >> connections but after that no data seems to get through. I can ping
> out and
> > >> get around 40% packet loss.
> > >>
> > >> Looking at /proc/interrupts, I can see both TxDma interrupts and
> RxDma
> > >> interrupts. No eth0 interrupts but that seems to be OK judging by the
> driver
> > >> source comments. Ifconfig shows no collistions, no dropped packets,
> no
> > errors,
> > >> so the system seems to think that everything is OK.
> > >>
> > >> Clues anyone? I'm starting to run out of ideas...
> > >>
> > >> Best regards,
> > >> Magnus
> > >>
> > >>
> > >> --
> > >>
> > >> Magnus Hjorth, M.Sc.
> > >> Omnisys Instruments AB
> > >> Gruvgatan 8
> > >> SE-421 30  Västra Frölunda, SWEDEN
> > >> Phone: +46 31 734 34 09
> > >> Fax: +46 31 734 34 29
> > >> http://www.omnisys.se
> > >>
> > >
> > > _______________________________________________
> > > Linuxppc-embedded mailing list
> > > Linuxppc-embedded@ozlabs.org
> > > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>



-- 
Johann Baudy
johaahn@gmail.com

[-- Attachment #2: Type: text/html, Size: 49288 bytes --]

Re: Xilinx LLTEMAC driver issues

[John Bonesio]

The change with the extra parenthesis (in the patch starting with line 133)=
 seems unecessary. I looked at the XLlDma_mBdWrite macro and it appeared to=
 have the correct use of parethesis in the implementation.
So, assuming there's nothing subtle that I missed, it's not needed. However=
, it does no harm either.

The rest of the patch seems fine.

=2D John

On Wednesday 02 April 2008 00:20, Johann Baudy wrote:
> I've solved this checksum offloading issue with this below patch.
> It may help, if you need performance. It certainly needs review but it wo=
rks
> on my side.
>=20
> --- xilinxgit/drivers/net/xilinx_lltemac/xlltemac_main.c.orig    2008-03-=
21
> 09:11:43.000000000 +0100
> +++ xilinxgit/drivers/net/xilinx_lltemac/xlltemac_main.c    2008-03-21
> 09:24:23.000000000 +0100
> @@ -133,7 +133,7 @@
>          (XLlDma_mBdRead((BdPtr), XLLDMA_BD_STSCTRL_USR0_OFFSET)) &
> 0xFFFFFFFE )
>=20
>  #define BdCsumSetup(BdPtr, Start, Insert) \
> -    XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, (Start) << 16 |
> (Insert))
> +    XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, ((Start) << 16) |
> (Insert))
>=20
>  /* Used for debugging */
>  #define BdCsumInsert(BdPtr) \
> @@ -1540,7 +1541,7 @@ static int xenet_DmaSend_internal(struct
>      /*
>       * if tx checksum offloading is enabled, when the ethernet stack
>       * wants us to perform the checksum in hardware,
> -     * skb->ip_summed is CHECKSUM_COMPLETE. Otherwise skb->ip_summed is
> +     * skb->ip_summed is CHECKSUM_PARTIAL. Otherwise skb->ip_summed is
>       * CHECKSUM_NONE, meaning the checksum is already done, or
>       * CHECKSUM_UNNECESSARY, meaning checksumming is turned off (e.g.
>       * loopback interface)
> @@ -1565,9 +1566,11 @@ static int xenet_DmaSend_internal(struct
>       * skb_transport_header(skb) points to the beginning of the ip header
>       *
>       */
> -    if (skb->ip_summed =3D=3D CHECKSUM_COMPLETE) {
> +    if (skb->ip_summed =3D=3D CHECKSUM_PARTIAL) {
> +
> +        unsigned int csum_start_off =3D skb_transport_offset(skb);
> +        unsigned int csum_index_off =3D csum_start_off + skb->csum_offse=
t;
>=20
> -        unsigned char *raw =3D skb_transport_header(skb);
>  #if 0
>          {
>              unsigned int csum =3D _xenet_tx_csum(skb);
> @@ -1578,9 +1581,8 @@ static int xenet_DmaSend_internal(struct
>          }
>  #else
>          BdCsumEnable(bd_ptr);
> -        BdCsumSetup(bd_ptr, raw - skb->data,
> -                (raw - skb->data) + skb->csum);
> -
> +        BdCsumSetup(bd_ptr, csum_start_off,
> +                csum_index_off);
>  #endif
>          lp->tx_hw_csums++;
>      }
> @@ -3277,7 +3279,7 @@ static int __devinit xtenet_of_probe(str
>      struct resource *r_irq =3D &r_irq_struct;    /* Interrupt resources =
*/
>      struct resource *r_mem =3D &r_mem_struct;    /* IO mem resources */
>      struct xlltemac_platform_data *pdata =3D &pdata_struct;
> -        void *mac_address;
> +        const void *mac_address;
>      int rc =3D 0;
>      const phandle *llink_connected_handle;
>      struct device_node *llink_connected_node;
>=20
>=20
> On Mon, Mar 31, 2008 at 11:10 AM, Magnus Hjorth <mh@omnisys.se> wrote:
>=20
> > Deactivating checksum offloading helped a lot! I still have some packet
> > loss and not the best performance (TFTP transfer about 100 kbyte/s) but=
 at
> > least it works.
> >
> > Thanks!
> >
> > //Magnus
> >
> > > -----Original Message-----
> > > From: rza1 [mailto:rza1@so-logic.net]
> > > Sent: den 31 mars 2008 11:14
> > > To: Magnus Hjorth
> > > Cc: John Linn; git; linuxppc-embedded@ozlabs.org
> > > Subject: Re: Xilinx LLTEMAC driver issues
> > >
> > > Hi Magnus,
> > >
> > > 1.
> > > I am using nearly the same versions then you and got the same problems
> > > too ;-).
> > > I think there are some problems with the checksum offloading.
> > > Try to sniff the some packages (e.g. wireshark)...
> > > For me ICMP (ping) worked but udp and tcp not (because off a wrong
> > > checksum in the transport layer).
> > > A quick solution is to just deactivate checksum offloading.
> > >
> > > 2.
> > > I remember some problems with Virtex-4 presamples too.
> > > There where problems with the hard-temac wrapper. You had to use 1.00=
=2Ea
> > > and not b version.
> > > But I don't have these problems with the EDK 9.2sp2/ISE9.2sp3 anymore.
> > >
> > > all the best,
> > > Robert
> > >
> > > Magnus Hjorth wrote:
> > > > Hi John,
> > > >
> > > > Thanks for the very fast reply! Right now I'm not at work so I don't
> > > > have the board or EDK here to test anything.
> > > >
> > > > I'm using checksum offload, but I don't know if DRE is enabled or n=
ot.
> > I
> > > > can't recall seeing any setting to enable/disable DRE..
> > > >
> > > > A few things that crossed my mind:
> > > >
> > > > Last year I did a design with EDK 8.2, back then there was an issue
> > with
> > > > the ML403 boards having an old revision of the FPGA which wasn't
> > > > compatible with some versions of the IP core. There are no such
> > version
> > > > issues with the xps_ll_temac?
> > > >
> > > > I don't think that I had phy-addr set in the DTS file. Will test th=
at
> > on
> > > > Monday.
> > > >
> > > > Best regards,
> > > > Magnus
> > > >
> > > >
> > > > On Sat, 2008-03-29 at 07:58 -0600, John Linn wrote:
> > > >
> > > >> Hi Magnus,
> > > >>
> > > >> Sorry to hear you're having problems with it.
> > > >>
> > > >> I am doing testing on an ML405 which is the same board but with a
> > bigger
> > > FPGA, but with ppc arch and I don't see this issue. I have done limit=
ed
> > testing
> > > with powerpc arch and the LL TEMAC, but I didn't see this issue there
> > either.
> > > Powerpc arch is definitely less mature in my experience than the ppc
> > arch. I'll
> > > do a quick test with my powerpc arch and make sure again I'm not seei=
ng
> > it.
> > > >>
> > > >> My kernel is from the Xilinx Git tree, but there have been a number
> > of
> > > changes we have pushed out so I don't know how long ago you pulled fr=
om
> > the Git
> > > tree.
> > > >>
> > > >> My EDK project is 10.1 so it's a little newer. I am using LL TEMAC
> > 1.01a so
> > > it's a little newer.  I reviewed the change log for the LL TEMAC and
> > don't see
> > > any big problems that were fixed in the newer versions, more new
> > features.  I'll
> > > check with some others here to see if I missed something there.
> > > >>
> > > >> I am using DMA also, but no DRE or checksum offload.  You didn't s=
ay
> > anything
> > > about those. I'm going to insert my mhs file that describes my system=
 to
> > let you
> > > compare your system configuration. It's not clear to me yet if you ha=
ve
> > a h/w or
> > > s/w problem.
> > > >>
> > > >> I'll also insert some of my device tree with the LL TEMAC so you c=
an
> > compare
> > > (ignore 16550 stuff as we are still working on that).
> > > >>
> > > >> Since you can't ping reliably I would probably focus on that since
> > it's
> > > simpler than the other issues you're seeing.
> > > >>
> > > >> Thanks,
> > > >> John
> > > >>
> > > >>
> > > >>
> > > >> #
> > >
> > #######################################################################=
#######
> > > >> # Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build
> > > EDK_K_SP1.1
> > > >> # Thu Feb 14 14:11:12 2008
> > > >> # Target Board:  Xilinx Virtex 4 ML405 Evaluation Platform Rev 1
> > > >> # Family:    virtex4
> > > >> # Device:    xc4vfx20
> > > >> # Package:   ff672
> > > >> # Speed Grade:  -10
> > > >> # Processor: ppc405_0
> > > >> # Processor clock frequency: 300.00 MHz
> > > >> # Bus clock frequency: 100.00 MHz
> > > >> # On Chip Memory :   8 KB
> > > >> # Total Off Chip Memory : 128 MB
> > > >> # - DDR_SDRAM =3D 128 MB
> > > >> #
> > >
> > #######################################################################=
#######
> > > >>  PARAMETER VERSION =3D 2.1.0
> > > >>
> > > >>
> > > >>  PORT fpga_0_RS232_Uart_sin_pin =3D fpga_0_RS232_Uart_sin, DIR =3D=
 I
> > > >>  PORT fpga_0_RS232_Uart_sout_pin =3D fpga_0_RS232_Uart_sout, DIR =
=3D O
> > > >>  PORT fpga_0_LEDs_4Bit_GPIO_IO_pin =3D fpga_0_LEDs_4Bit_GPIO_IO, D=
IR =3D
> > IO, VEC
> > > =3D [0:3]
> > > >>  PORT fpga_0_IIC_EEPROM_Scl_pin =3D fpga_0_IIC_EEPROM_Scl, DIR =3D=
 IO
> > > >>  PORT fpga_0_IIC_EEPROM_Sda_pin =3D fpga_0_IIC_EEPROM_Sda, DIR =3D=
 IO
> > > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin =3D
> > > fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR =3D I
> > > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin =3D
> > > fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR =3D O, VEC =3D [6:1]
> > > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin =3D
> > > fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR =3D IO, VEC =3D [15:0]
> > > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin =3D
> > > fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR =3D O
> > > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin =3D
> > > fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR =3D O
> > > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin =3D
> > > fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR =3D O
> > > >>  PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin =3D
> > > fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR =3D I
> > > >>  PORT fpga_0_DDR_SDRAM_DDR_Clk_pin =3D fpga_0_DDR_SDRAM_DDR_Clk, D=
IR =3D
> > O
> > > >>  PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin =3D fpga_0_DDR_SDRAM_DDR_Clk_=
n,
> > DIR =3D O
> > > >>  PORT fpga_0_DDR_SDRAM_DDR_Addr_pin =3D fpga_0_DDR_SDRAM_DDR_Addr,=
 DIR
> > =3D O, VEC
> > > =3D [12:0]
> > > >>  PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =3D
> > fpga_0_DDR_SDRAM_DDR_BankAddr, DIR
> > > =3D O, VEC =3D [1:0]
> > > >>  PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin =3D fpga_0_DDR_SDRAM_DDR_CAS_=
n,
> > DIR =3D O
> > > >>  PORT fpga_0_DDR_SDRAM_DDR_CE_pin =3D fpga_0_DDR_SDRAM_DDR_CE, DIR=
 =3D O
> > > >>  PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin =3D fpga_0_DDR_SDRAM_DDR_CS_n,=
 DIR
> > =3D O
> > > >>  PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin =3D fpga_0_DDR_SDRAM_DDR_RAS_=
n,
> > DIR =3D O
> > > >>  PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin =3D fpga_0_DDR_SDRAM_DDR_WE_n,=
 DIR
> > =3D O
> > > >>  PORT fpga_0_DDR_SDRAM_DDR_DM_pin =3D fpga_0_DDR_SDRAM_DDR_DM, DIR=
 =3D O,
> > VEC =3D
> > > [3:0]
> > > >>  PORT fpga_0_DDR_SDRAM_DDR_DQS =3D fpga_0_DDR_SDRAM_DDR_DQS, DIR =
=3D IO,
> > VEC =3D
> > > [3:0]
> > > >>  PORT fpga_0_DDR_SDRAM_DDR_DQ =3D fpga_0_DDR_SDRAM_DDR_DQ, DIR =3D=
 IO,
> > VEC =3D
> > > [31:0]
> > > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin =3D
> > > fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR =3D O, VEC =3D [7:0]
> > > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin =3D
> > > fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR =3D O
> > > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin =3D
> > > fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR =3D O
> > > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin =3D
> > > fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR =3D O
> > > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin =3D
> > > fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR =3D I, VEC =3D [7:0]
> > > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin =3D
> > > fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR =3D I
> > > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin =3D
> > > fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR =3D I
> > > >>  PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin =3D
> > > fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR =3D I
> > > >>  PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin =3D
> > > fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR =3D I
> > > >>  PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin =3D
> > fpga_0_TriMode_MAC_GMII_MDIO_0,
> > > DIR =3D IO
> > > >>  PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin =3D
> > fpga_0_TriMode_MAC_GMII_MDC_0, DIR
> > > =3D O
> > > >>  PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin =3D
> > > fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR =3D O
> > > >>  PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D CLK, CLK_FRE=
Q =3D
> > 100000000
> > > >>  PORT sys_rst_pin =3D sys_rst_s, DIR =3D I, RST_POLARITY =3D 0, SI=
GIS =3D RST
> > > >>
> > > >>
> > > >> BEGIN ppc405_virtex4
> > > >>  PARAMETER INSTANCE =3D ppc405_0
> > > >>  PARAMETER HW_VER =3D 2.01.a
> > > >>  PARAMETER C_FASTEST_PLB_CLOCK =3D DPLB1
> > > >>  PARAMETER C_IDCR_BASEADDR =3D 0b0100000000
> > > >>  PARAMETER C_IDCR_HIGHADDR =3D 0b0111111111
> > > >>  BUS_INTERFACE JTAGPPC =3D jtagppc_0_0
> > > >>  BUS_INTERFACE IPLB0 =3D plb
> > > >>  BUS_INTERFACE DPLB0 =3D plb
> > > >>  BUS_INTERFACE IPLB1 =3D ppc405_0_iplb1
> > > >>  BUS_INTERFACE DPLB1 =3D ppc405_0_dplb1
> > > >>  BUS_INTERFACE RESETPPC =3D ppc_reset_bus
> > > >>  PORT CPMC405CLOCK =3D proc_clk_s
> > > >>  PORT EICC405EXTINPUTIRQ =3D EICC405EXTINPUTIRQ
> > > >> END
> > > >>
> > > >> BEGIN jtagppc_cntlr
> > > >>  PARAMETER INSTANCE =3D jtagppc_0
> > > >>  PARAMETER HW_VER =3D 2.01.a
> > > >>  BUS_INTERFACE JTAGPPC0 =3D jtagppc_0_0
> > > >> END
> > > >>
> > > >> BEGIN plb_v46
> > > >>  PARAMETER INSTANCE =3D plb
> > > >>  PARAMETER C_DCR_INTFCE =3D 0
> > > >>  PARAMETER C_NUM_CLK_PLB2OPB_REARB =3D 100
> > > >>  PARAMETER HW_VER =3D 1.02.a
> > > >>  PORT PLB_Clk =3D sys_clk_s
> > > >>  PORT SYS_Rst =3D sys_bus_reset
> > > >> END
> > > >>
> > > >> BEGIN xps_bram_if_cntlr
> > > >>  PARAMETER INSTANCE =3D xps_bram_if_cntlr_1
> > > >>  PARAMETER HW_VER =3D 1.00.a
> > > >>  PARAMETER C_SPLB_NATIVE_DWIDTH =3D 64
> > > >>  PARAMETER C_BASEADDR =3D 0xffffe000
> > > >>  PARAMETER C_HIGHADDR =3D 0xffffffff
> > > >>  BUS_INTERFACE SPLB =3D plb
> > > >>  BUS_INTERFACE PORTA =3D xps_bram_if_cntlr_1_port
> > > >> END
> > > >>
> > > >> BEGIN bram_block
> > > >>  PARAMETER INSTANCE =3D plb_bram_if_cntlr_1_bram
> > > >>  PARAMETER HW_VER =3D 1.00.a
> > > >>  BUS_INTERFACE PORTA =3D xps_bram_if_cntlr_1_port
> > > >> END
> > > >>
> > > >> BEGIN xps_uart16550
> > > >>  PARAMETER INSTANCE =3D RS232_Uart
> > > >>  PARAMETER HW_VER =3D 2.00.a
> > > >>  PARAMETER C_IS_A_16550 =3D 1
> > > >>  PARAMETER C_BASEADDR =3D 0x83e00000
> > > >>  PARAMETER C_HIGHADDR =3D 0x83e0ffff
> > > >>  BUS_INTERFACE SPLB =3D plb
> > > >>  PORT sin =3D fpga_0_RS232_Uart_sin
> > > >>  PORT sout =3D fpga_0_RS232_Uart_sout
> > > >>  PORT IP2INTC_Irpt =3D RS232_Uart_IP2INTC_Irpt
> > > >> END
> > > >>
> > > >> BEGIN xps_gpio
> > > >>  PARAMETER INSTANCE =3D LEDs_4Bit
> > > >>  PARAMETER HW_VER =3D 1.00.a
> > > >>  PARAMETER C_INTERRUPT_PRESENT =3D 1
> > > >>  PARAMETER C_GPIO_WIDTH =3D 4
> > > >>  PARAMETER C_IS_DUAL =3D 0
> > > >>  PARAMETER C_IS_BIDIR =3D 1
> > > >>  PARAMETER C_ALL_INPUTS =3D 0
> > > >>  PARAMETER C_BASEADDR =3D 0x81400000
> > > >>  PARAMETER C_HIGHADDR =3D 0x8140ffff
> > > >>  BUS_INTERFACE SPLB =3D plb
> > > >>  PORT GPIO_IO =3D fpga_0_LEDs_4Bit_GPIO_IO
> > > >>  PORT IP2INTC_Irpt =3D LEDs_4Bit_IP2INTC_Irpt
> > > >> END
> > > >>
> > > >> BEGIN xps_iic
> > > >>  PARAMETER INSTANCE =3D IIC_EEPROM
> > > >>  PARAMETER HW_VER =3D 2.00.a
> > > >>  PARAMETER C_CLK_FREQ =3D 100000000
> > > >>  PARAMETER C_IIC_FREQ =3D 100000
> > > >>  PARAMETER C_TEN_BIT_ADR =3D 0
> > > >>  PARAMETER C_BASEADDR =3D 0x81600000
> > > >>  PARAMETER C_HIGHADDR =3D 0x8160ffff
> > > >>  BUS_INTERFACE SPLB =3D plb
> > > >>  PORT Scl =3D fpga_0_IIC_EEPROM_Scl
> > > >>  PORT Sda =3D fpga_0_IIC_EEPROM_Sda
> > > >>  PORT IIC2INTC_Irpt =3D IIC_EEPROM_IIC2INTC_Irpt
> > > >> END
> > > >>
> > > >> BEGIN xps_sysace
> > > >>  PARAMETER INSTANCE =3D SysACE_CompactFlash
> > > >>  PARAMETER HW_VER =3D 1.00.a
> > > >>  PARAMETER C_MEM_WIDTH =3D 16
> > > >>  PARAMETER C_BASEADDR =3D 0x83600000
> > > >>  PARAMETER C_HIGHADDR =3D 0x8360ffff
> > > >>  BUS_INTERFACE SPLB =3D plb
> > > >>  PORT SysACE_CLK =3D fpga_0_SysACE_CompactFlash_SysACE_CLK
> > > >>  PORT SysACE_MPA =3D fpga_0_SysACE_CompactFlash_SysACE_MPA_split
> > > >>  PORT SysACE_MPD =3D fpga_0_SysACE_CompactFlash_SysACE_MPD
> > > >>  PORT SysACE_CEN =3D fpga_0_SysACE_CompactFlash_SysACE_CEN
> > > >>  PORT SysACE_OEN =3D fpga_0_SysACE_CompactFlash_SysACE_OEN
> > > >>  PORT SysACE_WEN =3D fpga_0_SysACE_CompactFlash_SysACE_WEN
> > > >>  PORT SysACE_MPIRQ =3D fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
> > > >>  PORT SysACE_IRQ =3D SysACE_CompactFlash_SysACE_IRQ
> > > >> END
> > > >>
> > > >> BEGIN mpmc
> > > >>  PARAMETER INSTANCE =3D DDR_SDRAM
> > > >>  PARAMETER HW_VER =3D 4.00.a
> > > >>  PARAMETER C_NUM_PORTS =3D 3
> > > >>  PARAMETER C_MEM_PARTNO =3D HYB25D512160BE-5
> > > >>  PARAMETER C_MEM_DATA_WIDTH =3D 32
> > > >>  PARAMETER C_MEM_DQS_WIDTH =3D 4
> > > >>  PARAMETER C_MEM_DM_WIDTH =3D 4
> > > >>  PARAMETER C_MEM_TYPE =3D DDR
> > > >>  PARAMETER C_NUM_IDELAYCTRL =3D 2
> > > >>  PARAMETER C_IDELAYCTRL_LOC =3D IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
> > > >>  PARAMETER C_PIM0_BASETYPE =3D 2
> > > >>  PARAMETER C_PIM1_BASETYPE =3D 2
> > > >>  PARAMETER C_PIM2_BASETYPE =3D 3
> > > >>  PARAMETER C_MPMC_CLK0_PERIOD_PS =3D 10000
> > > >>  PARAMETER C_SDMA2_PI2LL_CLK_RATIO =3D 1
> > > >>  PARAMETER C_MPMC_BASEADDR =3D 0x00000000
> > > >>  PARAMETER C_MPMC_HIGHADDR =3D 0x07ffffff
> > > >>  PARAMETER C_SDMA_CTRL_BASEADDR =3D 0x84600000
> > > >>  PARAMETER C_SDMA_CTRL_HIGHADDR =3D 0x8460ffff
> > > >>  BUS_INTERFACE SPLB0 =3D ppc405_0_iplb1
> > > >>  BUS_INTERFACE SPLB1 =3D ppc405_0_dplb1
> > > >>  BUS_INTERFACE SDMA_LL2 =3D TriMode_MAC_GMII_LLINK0
> > > >>  BUS_INTERFACE SDMA_CTRL2 =3D plb
> > > >>  PORT DDR_Addr =3D fpga_0_DDR_SDRAM_DDR_Addr
> > > >>  PORT DDR_BankAddr =3D fpga_0_DDR_SDRAM_DDR_BankAddr
> > > >>  PORT DDR_CAS_n =3D fpga_0_DDR_SDRAM_DDR_CAS_n
> > > >>  PORT DDR_CE =3D fpga_0_DDR_SDRAM_DDR_CE
> > > >>  PORT DDR_CS_n =3D fpga_0_DDR_SDRAM_DDR_CS_n
> > > >>  PORT DDR_RAS_n =3D fpga_0_DDR_SDRAM_DDR_RAS_n
> > > >>  PORT DDR_WE_n =3D fpga_0_DDR_SDRAM_DDR_WE_n
> > > >>  PORT DDR_DM =3D fpga_0_DDR_SDRAM_DDR_DM
> > > >>  PORT DDR_DQS =3D fpga_0_DDR_SDRAM_DDR_DQS
> > > >>  PORT DDR_DQ =3D fpga_0_DDR_SDRAM_DDR_DQ
> > > >>  PORT DDR_Clk =3D fpga_0_DDR_SDRAM_DDR_Clk
> > > >>  PORT DDR_Clk_n =3D fpga_0_DDR_SDRAM_DDR_Clk_n
> > > >>  PORT MPMC_Clk0 =3D sys_clk_s
> > > >>  PORT MPMC_Clk90 =3D DDR_SDRAM_mpmc_clk_90_s
> > > >>  PORT SDMA2_Clk =3D sys_clk_s
> > > >>  PORT MPMC_Clk_200MHz =3D clk_200mhz_s
> > > >>  PORT MPMC_Rst =3D sys_periph_reset
> > > >>  PORT SDMA2_Rx_IntOut =3D DDR_SDRAM_SDMA2_Rx_IntOut
> > > >>  PORT SDMA2_Tx_IntOut =3D DDR_SDRAM_SDMA2_Tx_IntOut
> > > >> END
> > > >>
> > > >> BEGIN xps_ll_temac
> > > >>  PARAMETER INSTANCE =3D TriMode_MAC_GMII
> > > >>  PARAMETER HW_VER =3D 1.01.a
> > > >>  PARAMETER C_SPLB_CLK_PERIOD_PS =3D 10000
> > > >>  PARAMETER C_PHY_TYPE =3D 1
> > > >>  PARAMETER C_NUM_IDELAYCTRL =3D 4
> > > >>  PARAMETER C_IDELAYCTRL_LOC =3D IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-
> > > IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3
> > > >>  PARAMETER C_TEMAC_TYPE =3D 1
> > > >>  PARAMETER C_BUS2CORE_CLK_RATIO =3D 1
> > > >>  PARAMETER C_BASEADDR =3D 0x81c00000
> > > >>  PARAMETER C_HIGHADDR =3D 0x81c0ffff
> > > >>  BUS_INTERFACE SPLB =3D plb
> > > >>  BUS_INTERFACE LLINK0 =3D TriMode_MAC_GMII_LLINK0
> > > >>  PORT GMII_TXD_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TXD_0
> > > >>  PORT GMII_TX_EN_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0
> > > >>  PORT GMII_TX_ER_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0
> > > >>  PORT GMII_TX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0
> > > >>  PORT GMII_RXD_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RXD_0
> > > >>  PORT GMII_RX_DV_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0
> > > >>  PORT GMII_RX_ER_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0
> > > >>  PORT GMII_RX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0
> > > >>  PORT MII_TX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0
> > > >>  PORT MDIO_0 =3D fpga_0_TriMode_MAC_GMII_MDIO_0
> > > >>  PORT MDC_0 =3D fpga_0_TriMode_MAC_GMII_MDC_0
> > > >>  PORT TemacPhy_RST_n =3D fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n
> > > >>  PORT GTX_CLK_0 =3D temac_clk_s
> > > >>  PORT REFCLK =3D clk_200mhz_s
> > > >>  PORT LlinkTemac0_CLK =3D sys_clk_s
> > > >>  PORT TemacIntc0_Irpt =3D TriMode_MAC_GMII_TemacIntc0_Irpt
> > > >> END
> > > >>
> > > >> BEGIN util_bus_split
> > > >>  PARAMETER INSTANCE =3D SysACE_CompactFlash_util_bus_split_0
> > > >>  PARAMETER HW_VER =3D 1.00.a
> > > >>  PARAMETER C_SIZE_IN =3D 7
> > > >>  PARAMETER C_LEFT_POS =3D 0
> > > >>  PARAMETER C_SPLIT =3D 6
> > > >>  PORT Sig =3D fpga_0_SysACE_CompactFlash_SysACE_MPA_split
> > > >>  PORT Out1 =3D fpga_0_SysACE_CompactFlash_SysACE_MPA
> > > >> END
> > > >>
> > > >> BEGIN plb_v46
> > > >>  PARAMETER INSTANCE =3D ppc405_0_iplb1
> > > >>  PARAMETER HW_VER =3D 1.02.a
> > > >>  PORT PLB_Clk =3D sys_clk_s
> > > >>  PORT SYS_Rst =3D sys_bus_reset
> > > >> END
> > > >>
> > > >> BEGIN plb_v46
> > > >>  PARAMETER INSTANCE =3D ppc405_0_dplb1
> > > >>  PARAMETER HW_VER =3D 1.02.a
> > > >>  PORT PLB_Clk =3D sys_clk_s
> > > >>  PORT SYS_Rst =3D sys_bus_reset
> > > >> END
> > > >>
> > > >> BEGIN clock_generator
> > > >>  PARAMETER INSTANCE =3D clock_generator_0
> > > >>  PARAMETER HW_VER =3D 2.00.a
> > > >>  PARAMETER C_EXT_RESET_HIGH =3D 1
> > > >>  PARAMETER C_CLKIN_FREQ =3D 100000000
> > > >>  PARAMETER C_CLKOUT0_FREQ =3D 100000000
> > > >>  PARAMETER C_CLKOUT0_BUF =3D TRUE
> > > >>  PARAMETER C_CLKOUT0_PHASE =3D 0
> > > >>  PARAMETER C_CLKOUT0_GROUP =3D DCM0
> > > >>  PARAMETER C_CLKOUT1_FREQ =3D 100000000
> > > >>  PARAMETER C_CLKOUT1_BUF =3D TRUE
> > > >>  PARAMETER C_CLKOUT1_PHASE =3D 90
> > > >>  PARAMETER C_CLKOUT1_GROUP =3D DCM0
> > > >>  PARAMETER C_CLKOUT2_FREQ =3D 300000000
> > > >>  PARAMETER C_CLKOUT2_BUF =3D TRUE
> > > >>  PARAMETER C_CLKOUT2_PHASE =3D 0
> > > >>  PARAMETER C_CLKOUT2_GROUP =3D DCM0
> > > >>  PARAMETER C_CLKOUT3_FREQ =3D 200000000
> > > >>  PARAMETER C_CLKOUT3_BUF =3D TRUE
> > > >>  PARAMETER C_CLKOUT3_PHASE =3D 0
> > > >>  PARAMETER C_CLKOUT3_GROUP =3D NONE
> > > >>  PARAMETER C_CLKOUT4_FREQ =3D 125000000
> > > >>  PARAMETER C_CLKOUT4_BUF =3D TRUE
> > > >>  PARAMETER C_CLKOUT4_PHASE =3D 0
> > > >>  PARAMETER C_CLKOUT4_GROUP =3D NONE
> > > >>  PORT CLKOUT0 =3D sys_clk_s
> > > >>  PORT CLKOUT1 =3D DDR_SDRAM_mpmc_clk_90_s
> > > >>  PORT CLKOUT2 =3D proc_clk_s
> > > >>  PORT CLKOUT3 =3D clk_200mhz_s
> > > >>  PORT CLKOUT4 =3D temac_clk_s
> > > >>  PORT CLKIN =3D dcm_clk_s
> > > >>  PORT LOCKED =3D Dcm_all_locked
> > > >>  PORT RST =3D net_gnd
> > > >> END
> > > >>
> > > >> BEGIN proc_sys_reset
> > > >>  PARAMETER INSTANCE =3D proc_sys_reset_0
> > > >>  PARAMETER HW_VER =3D 2.00.a
> > > >>  PARAMETER C_EXT_RESET_HIGH =3D 0
> > > >>  BUS_INTERFACE RESETPPC0 =3D ppc_reset_bus
> > > >>  PORT Slowest_sync_clk =3D sys_clk_s
> > > >>  PORT Dcm_locked =3D Dcm_all_locked
> > > >>  PORT Ext_Reset_In =3D sys_rst_s
> > > >>  PORT Bus_Struct_Reset =3D sys_bus_reset
> > > >>  PORT Peripheral_Reset =3D sys_periph_reset
> > > >> END
> > > >>
> > > >> BEGIN xps_intc
> > > >>  PARAMETER INSTANCE =3D xps_intc_0
> > > >>  PARAMETER HW_VER =3D 1.00.a
> > > >>  PARAMETER C_BASEADDR =3D 0x81800000
> > > >>  PARAMETER C_HIGHADDR =3D 0x8180ffff
> > > >>  BUS_INTERFACE SPLB =3D plb
> > > >>  PORT Irq =3D EICC405EXTINPUTIRQ
> > > >>  PORT Intr =3D RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt &
> > > IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ &
> > > TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut &
> > > DDR_SDRAM_SDMA2_Tx_IntOut
> > > >> END
> > > >>
> > > >>
> > > >>
> > > >>    #address-cells =3D <1>;
> > > >>    #size-cells =3D <1>;
> > > >>    compatible =3D "xlnx,virtex";
> > > >>    model =3D "testing";
> > > >>    DDR_SDRAM: memory@0 {
> > > >>            device_type =3D "memory";
> > > >>            reg =3D < 0 8000000 >;
> > > >>    } ;
> > > >>    chosen {
> > > >>            bootargs =3D "console=3DttyS0,9600 ip=3Don
> > > nfsroot=3D172.16.40.76:/v2pclients/jhl26,tcp";
> > > >>            linux,stdout-path =3D "/plb@0/serial@83e00000";
> > > >>    } ;
> > > >>    cpus {
> > > >>            #address-cells =3D <1>;
> > > >>            #cpus =3D <1>;
> > > >>            #size-cells =3D <0>;
> > > >>            ppc405_0: cpu@0 {
> > > >>                    clock-frequency =3D <11e1a300>;
> > > >>                    compatible =3D "PowerPC,405", "ibm,ppc405";
> > > >>                    d-cache-line-size =3D <20>;
> > > >>                    d-cache-size =3D <4000>;
> > > >>                    device_type =3D "cpu";
> > > >>                    i-cache-line-size =3D <20>;
> > > >>                    i-cache-size =3D <4000>;
> > > >>                    model =3D "PowerPC,405";
> > > >>                    reg =3D <0>;
> > > >>                    timebase-frequency =3D <11e1a300>;
> > > >>                    xlnx,apu-control =3D <de00>;
> > > >>                    xlnx,apu-udi-1 =3D <a18983>;
> > > >>                    xlnx,apu-udi-2 =3D <a38983>;
> > > >>                    xlnx,apu-udi-3 =3D <a589c3>;
> > > >>                    xlnx,apu-udi-4 =3D <a789c3>;
> > > >>                    xlnx,apu-udi-5 =3D <a98c03>;
> > > >>                    xlnx,apu-udi-6 =3D <ab8c03>;
> > > >>                    xlnx,apu-udi-7 =3D <ad8c43>;
> > > >>                    xlnx,apu-udi-8 =3D <af8c43>;
> > > >>                    xlnx,deterministic-mult =3D <0>;
> > > >>                    xlnx,disable-operand-forwarding =3D <1>;
> > > >>                    xlnx,fastest-plb-clock =3D "DPLB0";
> > > >>                    xlnx,generate-plb-timespecs =3D <1>;
> > > >>                    xlnx,mmu-enable =3D <1>;
> > > >>                    xlnx,pvr-high =3D <0>;
> > > >>                    xlnx,pvr-low =3D <0>;
> > > >>            } ;
> > > >>    } ;
> > > >>    plb: plb@0 {
> > > >>            #address-cells =3D <1>;
> > > >>            #size-cells =3D <1>;
> > > >>            compatible =3D "xlnx,plb-v46-1.02.a";
> > > >>            ranges ;
> > > >>            IIC_EEPROM: i2c@81600000 {
> > > >>                    compatible =3D "xlnx,xps-iic-2.00.a";
> > > >>                    interrupt-parent =3D <&xps_intc_0>;
> > > >>                    interrupts =3D < 4 2 >;
> > > >>                    reg =3D < 81600000 10000 >;
> > > >>                    xlnx,clk-freq =3D <5f5e100>;
> > > >>                    xlnx,family =3D "virtex4";
> > > >>                    xlnx,gpo-width =3D <1>;
> > > >>                    xlnx,iic-freq =3D <186a0>;
> > > >>                    xlnx,scl-inertial-delay =3D <0>;
> > > >>                    xlnx,sda-inertial-delay =3D <0>;
> > > >>                    xlnx,ten-bit-adr =3D <0>;
> > > >>            } ;
> > > >>            LEDs_4Bit: gpio@81400000 {
> > > >>                    compatible =3D "xlnx,xps-gpio-1.00.a";
> > > >>                    interrupt-parent =3D <&xps_intc_0>;
> > > >>                    interrupts =3D < 5 2 >;
> > > >>                    reg =3D < 81400000 10000 >;
> > > >>                    xlnx,all-inputs =3D <0>;
> > > >>                    xlnx,all-inputs-2 =3D <0>;
> > > >>                    xlnx,dout-default =3D <0>;
> > > >>                    xlnx,dout-default-2 =3D <0>;
> > > >>                    xlnx,family =3D "virtex4";
> > > >>                    xlnx,gpio-width =3D <4>;
> > > >>                    xlnx,interrupt-present =3D <1>;
> > > >>                    xlnx,is-bidir =3D <1>;
> > > >>                    xlnx,is-bidir-2 =3D <1>;
> > > >>                    xlnx,is-dual =3D <0>;
> > > >>                    xlnx,tri-default =3D <ffffffff>;
> > > >>                    xlnx,tri-default-2 =3D <ffffffff>;
> > > >>            } ;
> > > >>            RS232_Uart: serial@83e00000 {
> > > >>                    compatible =3D "xlnx,xps-uart16550-2.00.a";
> > > >> //                 compatible =3D "ns16550";
> > > >>                    device_type =3D "serial";
> > > >>                    interrupt-parent =3D <&xps_intc_0>;
> > > >>                    interrupts =3D < 6 2 >;
> > > >>                    reg =3D < 83e00000 10000 >;
> > > >>                    current-speed =3D <d#9600>;
> > > >>                    clock-frequency =3D <d#100000000>;  /* added
> > > by jhl */
> > > >>                    reg-shift =3D <2>;
> > > >>                    xlnx,family =3D "virtex4";
> > > >>                    xlnx,has-external-rclk =3D <0>;
> > > >>                    xlnx,has-external-xin =3D <0>;
> > > >>                    xlnx,is-a-16550 =3D <1>;
> > > >>            } ;
> > > >>            SysACE_CompactFlash: sysace@83600000 {
> > > >>                    compatible =3D "xlnx,xps-sysace-1.00.a";
> > > >>                    interrupt-parent =3D <&xps_intc_0>;
> > > >>                    interrupts =3D < 3 2 >;
> > > >>                    reg =3D < 83600000 10000 >;
> > > >>                    xlnx,family =3D "virtex4";
> > > >>                    xlnx,mem-width =3D <10>;
> > > >>            } ;
> > > >>            TriMode_MAC_GMII: xps-ll-temac@81c00000 {
> > > >>                    #address-cells =3D <1>;
> > > >>                    #size-cells =3D <1>;
> > > >>                    compatible =3D "xlnx,compound";
> > > >>                    ethernet@81c00000 {
> > > >>                            compatible =3D "xlnx,xps-ll-temac-
> > > 1.01.a";
> > > >>                            device_type =3D "network";
> > > >>                            interrupt-parent =3D
> > > <&xps_intc_0>;
> > > >>                            interrupts =3D < 2 2 >;
> > > >>                            llink-connected =3D <&PIM2>;
> > > >>                            local-mac-address =3D [ 02 00 00
> > > 00 00 01 ];
> > > >>                            reg =3D < 81c00000 40 >;
> > > >>                            xlnx,bus2core-clk-ratio =3D <1>;
> > > >>                            xlnx,phy-type =3D <1>;
> > > >>                            xlnx,phyaddr =3D <1>;
> > > >>                            xlnx,rxcsum =3D <0>;
> > > >>                            xlnx,rxfifo =3D <1000>;
> > > >>                            xlnx,temac-type =3D <1>;
> > > >>                            xlnx,txcsum =3D <0>;
> > > >>                            xlnx,txfifo =3D <1000>;
> > > >>                    } ;
> > > >>            } ;
> > > >>            mpmc@0 {
> > > >>                    #address-cells =3D <1>;
> > > >>                    #size-cells =3D <1>;
> > > >>                    compatible =3D "xlnx,mpmc-4.00.a";
> > > >>                    PIM2: sdma@84600100 {
> > > >>                            compatible =3D "xlnx,ll-dma-
> > > 1.00.a";
> > > >>                            interrupt-parent =3D
> > > <&xps_intc_0>;
> > > >>                            interrupts =3D < 1 2 0 2 >;
> > > >>                            reg =3D < 84600100 80 >;
> > > >>                    } ;
> > > >>            } ;
> > > >>            xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {
> > > >>                    compatible =3D "xlnx,xps-bram-if-cntlr-
> > > 1.00.a";
> > > >>                    reg =3D < ffffe000 2000 >;
> > > >>                    xlnx,family =3D "virtex4";
> > > >>            } ;
> > > >>            xps_intc_0: interrupt-controller@81800000 {
> > > >>                    #interrupt-cells =3D <2>;
> > > >>                    compatible =3D "xlnx,xps-intc-1.00.a";
> > > >>                    interrupt-controller ;
> > > >>                    reg =3D < 81800000 10000 >;
> > > >>                    xlnx,num-intr-inputs =3D <7>;
> > > >>            } ;
> > > >>    } ;
> > > >>    ppc405_0_dplb1: plb@1 {
> > > >>            #address-cells =3D <1>;
> > > >>            #size-cells =3D <1>;
> > > >>            compatible =3D "xlnx,plb-v46-1.02.a";
> > > >>            ranges ;
> > > >>    } ;
> > > >> }  ;
> > > >>
> > > >>
> > > >>
> > > >> -----Original Message-----
> > > >> From: Magnus Hjorth [mailto:mh@omnisys.se]
> > > >> Sent: Saturday, March 29, 2008 6:54 AM
> > > >> To: git
> > > >> Cc: linuxppc-embedded@ozlabs.org
> > > >> Subject: Xilinx LLTEMAC driver issues
> > > >>
> > > >> Hi,
> > > >>
> > > >> I'm having some networking troubles with the Xilinx LLTEMAC driver
> > from the
> > > >> Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
> > > >> xps_ll_temac v1.00.b
> > > >>
> > > >> The weird thing is, that it sort of half works. It successfully ma=
kes
> > a DHCP
> > > >> request and gets its IP address. I tried setting up a tftpd server,
> > and I can
> > > >> see UDP requests coming in but the response doesn't seem to come o=
ut.
> > I also
> > > >> tried running a TCP server on the board, and it can see and accept
> > incoming
> > > >> connections but after that no data seems to get through. I can ping
> > out and
> > > >> get around 40% packet loss.
> > > >>
> > > >> Looking at /proc/interrupts, I can see both TxDma interrupts and
> > RxDma
> > > >> interrupts. No eth0 interrupts but that seems to be OK judging by =
the
> > driver
> > > >> source comments. Ifconfig shows no collistions, no dropped packets,
> > no
> > > errors,
> > > >> so the system seems to think that everything is OK.
> > > >>
> > > >> Clues anyone? I'm starting to run out of ideas...
> > > >>
> > > >> Best regards,
> > > >> Magnus
> > > >>
> > > >>
> > > >> --
> > > >>
> > > >> Magnus Hjorth, M.Sc.
> > > >> Omnisys Instruments AB
> > > >> Gruvgatan 8
> > > >> SE-421 30  V=C3=A4stra Fr=C3=B6lunda, SWEDEN
> > > >> Phone: +46 31 734 34 09
> > > >> Fax: +46 31 734 34 29
> > > >> http://www.omnisys.se
> > > >>
> > > >
> > > > _______________________________________________
> > > > Linuxppc-embedded mailing list
> > > > Linuxppc-embedded@ozlabs.org
> > > > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> >
>=20
>=20
>=20
> --=20
> Johann Baudy
> johaahn@gmail.com
>=20

RE: Xilinx LLTEMAC driver issues

[MingLiu]

[-- Attachment #1: Type: text/plain, Size: 685 bytes --]


Dear all,
> The change with the extra parenthesis (in the patch starting with line 133) seems unecessary. I looked at the XLlDma_mBdWrite macro and it appeared to have the correct use of parethesis in the implementation.> So, assuming there's nothing subtle that I missed, it's not needed. However, it does no harm either.
However it really helps after I tried this patch. So there should be some difference after it is used. 
 
One more question, does this mean that the problem is not on the hardware timing, but the device driver? 
 
BR
Ming
_________________________________________________________________
用手机MSN聊天写邮件看空间，无限沟通，分享精彩！
http://mobile.msn.com.cn/

[-- Attachment #2: Type: text/html, Size: 929 bytes --]

RE: Xilinx LLTEMAC driver issues

[Xiaochang Duan]

[-- Attachment #1: Type: text/plain, Size: 1650 bytes --]

According to C operator precedence ((http://www.difranco.net/cop2220/op-prec.htm), the following patch should not be needed as operator “<<” has higher precedence than operator “|”.

 

-    XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, (Start) << 16 | (Insert))

+    XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, ((Start) << 16) | 

+ (Insert))

 

Also FYI, the XLlDma_mBdWrite currently is defined in xlldma driver as:

 

#define XLlDma_mBdWrite(BaseAddress, Offset, Data)                \

            (*(u32*)((u32)(BaseAddress) + (u32)(Offset)) = (Data))

 

So I don’t understand why the patch could help.

 

Thanks, 

-Xiaochang

________________________________

From: MingLiu [mailto:eemingliu@hotmail.com] 
Sent: Thursday, April 03, 2008 2:29 AM
To: John Bonesio; Johann Baudy
Cc: linuxppc-embedded@ozlabs.org; John Linn; git
Subject: RE: Xilinx LLTEMAC driver issues

 

Dear all,

> The change with the extra parenthesis (in the patch starting with line 133) seems unecessary. I looked at the XLlDma_mBdWrite macro and it appeared to have the correct use of parethesis in the implementation.
> So, assuming there's nothing subtle that I missed, it's not needed. However, it does no harm either.

However it really helps after I tried this patch. So there should be some difference after it is used. 
 
One more question, does this mean that the problem is not on the hardware timing, but the device driver? 
 
BR
Ming

________________________________

Windows Live Writer，支持离线撰写博客内容，随时随地想写就写。 立即使用！ <http://get.live.cn/product/writer.html> 


[-- Attachment #2: Type: text/html, Size: 7774 bytes --]

Re: Xilinx LLTEMAC driver issues

[Johann Baudy]

VGhlIG9ubHkgcGFydCBvZiB0aGUgcGF0Y2ggdGhhdCByZWFsbHkgc29sdmVzIHRoZSBjaGVja3N1
bSBvZmZsb2FkCmNhbGN1bGF0aW9uIGlzIGludG8geGVuZXRfRG1hU2VuZF9pbnRlcm5hbCgpLgpU
aGUgcmVzdCBpcyB3YXJuaW5nIHJlbW92YWwsIGNvbW1lbnQgdXBkYXRlIGFuZCBkZXZlbG9wZXIg
ZnJpZW5kbHkgZGVmaW5lIDopCgpCZXN0IHJlZ2FyZHMsCkpvaGFubgoKCjIwMDgvNC8zIFhpYW9j
aGFuZyBEdWFuIDx4aWFvY2hhbmcuZHVhbkB4aWxpbnguY29tPjoKPgo+Cj4KPgo+IEFjY29yZGlu
ZyB0byBDIG9wZXJhdG9yIHByZWNlZGVuY2UgKChodHRwOi8vd3d3LmRpZnJhbmNvLm5ldC9jb3Ay
MjIwL29wLXByZWMuaHRtKSwgdGhlIGZvbGxvd2luZyBwYXRjaCBzaG91bGQgbm90IGJlIG5lZWRl
ZCBhcyBvcGVyYXRvciAiPDwiIGhhcyBoaWdoZXIgcHJlY2VkZW5jZSB0aGFuIG9wZXJhdG9yICJ8
Ii4KPgo+Cj4KPiAtICAgIFhMbERtYV9tQmRXcml0ZSgoQmRQdHIpLCBYTExETUFfQkRfVVNSMV9P
RkZTRVQsIChTdGFydCkgPDwgMTYgfCAoSW5zZXJ0KSkKPgo+Cj4gKyAgICBYTGxEbWFfbUJkV3Jp
dGUoKEJkUHRyKSwgWExMRE1BX0JEX1VTUjFfT0ZGU0VULCAoKFN0YXJ0KSA8PCAxNikgfAo+Cj4g
KyAoSW5zZXJ0KSkKPgo+Cj4KPiBBbHNvIEZZSSwgdGhlIFhMbERtYV9tQmRXcml0ZSBjdXJyZW50
bHkgaXMgZGVmaW5lZCBpbiB4bGxkbWEgZHJpdmVyIGFzOgo+Cj4KPgo+ICNkZWZpbmUgWExsRG1h
X21CZFdyaXRlKEJhc2VBZGRyZXNzLCBPZmZzZXQsIERhdGEpICAgICAgICAgICAgICAgIFwKPgo+
ICAgICAgICAgICAgICgqKHUzMiopKCh1MzIpKEJhc2VBZGRyZXNzKSArICh1MzIpKE9mZnNldCkp
ID0gKERhdGEpKQo+Cj4KPgo+IFNvIEkgZG9uJ3QgdW5kZXJzdGFuZCB3aHkgdGhlIHBhdGNoIGNv
dWxkIGhlbHAuCj4KPgo+Cj4gVGhhbmtzLAo+Cj4gLVhpYW9jaGFuZwo+Cj4gX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX18KCj4KPiBGcm9tOiBNaW5nTGl1IFttYWlsdG86ZWVtaW5nbGl1
QGhvdG1haWwuY29tXQo+IFNlbnQ6IFRodXJzZGF5LCBBcHJpbCAwMywgMjAwOCAyOjI5IEFNCj4g
VG86IEpvaG4gQm9uZXNpbzsgSm9oYW5uIEJhdWR5Cj4gQ2M6IGxpbnV4cHBjLWVtYmVkZGVkQG96
bGFicy5vcmc7IEpvaG4gTGlubjsgZ2l0Cj4KPiBTdWJqZWN0OiBSRTogWGlsaW54IExMVEVNQUMg
ZHJpdmVyIGlzc3Vlcwo+Cj4KPgo+Cj4KPgo+IERlYXIgYWxsLAo+Cj4gPiBUaGUgY2hhbmdlIHdp
dGggdGhlIGV4dHJhIHBhcmVudGhlc2lzIChpbiB0aGUgcGF0Y2ggc3RhcnRpbmcgd2l0aCBsaW5l
IDEzMykgc2VlbXMgdW5lY2Vzc2FyeS4gSSBsb29rZWQgYXQgdGhlIFhMbERtYV9tQmRXcml0ZSBt
YWNybyBhbmQgaXQgYXBwZWFyZWQgdG8gaGF2ZSB0aGUgY29ycmVjdCB1c2Ugb2YgcGFyZXRoZXNp
cyBpbiB0aGUgaW1wbGVtZW50YXRpb24uCj4gPiBTbywgYXNzdW1pbmcgdGhlcmUncyBub3RoaW5n
IHN1YnRsZSB0aGF0IEkgbWlzc2VkLCBpdCdzIG5vdCBuZWVkZWQuIEhvd2V2ZXIsIGl0IGRvZXMg
bm8gaGFybSBlaXRoZXIuCj4KPiBIb3dldmVyIGl0IHJlYWxseSBoZWxwcyBhZnRlciBJIHRyaWVk
IHRoaXMgcGF0Y2guIFNvIHRoZXJlIHNob3VsZCBiZSBzb21lIGRpZmZlcmVuY2UgYWZ0ZXIgaXQg
aXMgdXNlZC4KPgo+IE9uZSBtb3JlIHF1ZXN0aW9uLCBkb2VzIHRoaXMgbWVhbiB0aGF0IHRoZSBw
cm9ibGVtIGlzIG5vdCBvbiB0aGUgaGFyZHdhcmUgdGltaW5nLCBidXQgdGhlIGRldmljZSBkcml2
ZXI/Cj4KPiBCUgo+IE1pbmcKPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwoKPgo+
IFdpbmRvd3MgTGl2ZSBXcml0ZXKjrNans9bA68/f16vQtLKpv83E2sjdo6zL5sqxy+a12M/r0LS+
zdC0oaMgwaK8tMq508OjoQoKCgotLSAKSm9oYW5uIEJhdWR5CmpvaGFhaG5AZ21haWwuY29tCg==

RE: Xilinx LLTEMAC driver issues

[Xiaochang Duan]

Thanks for the clarification. :)
-Xiaochang

-----Original Message-----
From: Johann Baudy [mailto:johaahn@gmail.com]=20
Sent: Thursday, April 03, 2008 10:39 AM
To: Xiaochang Duan
Cc: MingLiu; John Bonesio; linuxppc-embedded@ozlabs.org; John Linn; git
Subject: Re: Xilinx LLTEMAC driver issues

The only part of the patch that really solves the checksum offload
calculation is into xenet_DmaSend_internal().
The rest is warning removal, comment update and developer friendly =
define :)

Best regards,
Johann


2008/4/3 Xiaochang Duan <xiaochang.duan@xilinx.com>:
>
>
>
>
> According to C operator precedence =
((http://www.difranco.net/cop2220/op-prec.htm), the following patch =
should not be needed as operator "<<" has higher precedence than =
operator "|".
>
>
>
> -    XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, (Start) << 16 | =
(Insert))
>
>
> +    XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, ((Start) << 16) |
>
> + (Insert))
>
>
>
> Also FYI, the XLlDma_mBdWrite currently is defined in xlldma driver =
as:
>
>
>
> #define XLlDma_mBdWrite(BaseAddress, Offset, Data)                \
>
>             (*(u32*)((u32)(BaseAddress) + (u32)(Offset)) =3D (Data))
>
>
>
> So I don't understand why the patch could help.
>
>
>
> Thanks,
>
> -Xiaochang
>
> ________________________________

>
> From: MingLiu [mailto:eemingliu@hotmail.com]
> Sent: Thursday, April 03, 2008 2:29 AM
> To: John Bonesio; Johann Baudy
> Cc: linuxppc-embedded@ozlabs.org; John Linn; git
>
> Subject: RE: Xilinx LLTEMAC driver issues
>
>
>
>
>
>
> Dear all,
>
> > The change with the extra parenthesis (in the patch starting with =
line 133) seems unecessary. I looked at the XLlDma_mBdWrite macro and it =
appeared to have the correct use of parethesis in the implementation.
> > So, assuming there's nothing subtle that I missed, it's not needed. =
However, it does no harm either.
>
> However it really helps after I tried this patch. So there should be =
some difference after it is used.
>
> One more question, does this mean that the problem is not on the =
hardware timing, but the device driver?
>
> BR
> Ming
> ________________________________

>
> Windows Live =
Writer=A3=AC=D6=A7=B3=D6=C0=EB=CF=DF=D7=AB=D0=B4=B2=A9=BF=CD=C4=DA=C8=DD=A3=
=AC=CB=E6=CA=B1=CB=E6=B5=D8=CF=EB=D0=B4=BE=CD=D0=B4=A1=A3 =
=C1=A2=BC=B4=CA=B9=D3=C3=A3=A1



--=20
Johann Baudy
johaahn@gmail.com

Re: Xilinx LLTEMAC driver issues

[Johann Baudy]

SGkgTWluZywKCkkndmUgYWxyZWFkeSB1c2VkIG5ldHBlcmYgKHdpdGhvdXQgTkZTKSBzdWNjZXNz
ZnVsbHkuCkFyZSB5b3UgdXNpbmcgMS4wMC5iIGFuZCA5LjIsIGlmIHllcyBsb29rIGF0ICBBUiAj
Mjk3MDguCgpCZXN0IHJlZ2FyZHMsCkpvaGFubgoKT24gRnJpLCBBcHIgNCwgMjAwOCBhdCA5OjM2
IEFNLCBNaW5nTGl1IDxlZW1pbmdsaXVAaG90bWFpbC5jb20+IHdyb3RlOgo+Cj4gIERlYXIgSm9o
YW5uLAo+ICBQcmV2aW91c2x5IEkgc2FpZCB0aGlzIHBhdGNoIGhlbHBzIGZvciB0aGUgY2hlY2tz
dW0gZXJyb3IgcHJvYmxlbS4gQnV0IG5vdwo+IEkgZm91bmQgc29tZSBuZXcgaXNzdWVzLiBZZXMu
IGF0IGxlYXN0IHdpdGggdGhpcyBwYXRjaCwgc29tZXRoaW5nIGlzIGJldHRlcgo+IGFuZCBhdCBs
ZWFzdCB3ZSBjYW4gdXNlIHRoZSBoYXJkd2FyZSBjaGVja3N1bSBvZmZsb2FkaW5nIHRvIGRvIHNv
bWV0aGluZywKPiBmb3IgZXhhbXBsZSBJIGNhbiBtb3VudCB0aGUgTkZTIHJvb3QgZmlsZSBzeXN0
ZW0uIEhvd2V2ZXIgd2hlbiBJIHRyeSB0bwo+IG1lYXN1cmUgdGhlIGV0aGVybmV0IGJhbmR3aWR0
aCB3aXRoIG5ldHBlcmYsIHNvbWV0aGluZyBnb2VzIHdyb25nIGFuZCB0aGUKPiBORlMgbW91bnQg
d2lsbCBiZSBicm9rZW4uIEkgZ3Vlc3MgdGhpcyBpcyBiZWNhdXNlIG9mIHRoZSBsYXJnZSBidWxr
IGRhdGEKPiB0cmFuc2ZlciBhbmQgbWF5YmUgdGh1cyBpdCB0cmlnZ2VycyB0aGUgY2hlY2tzdW0g
cHJvYmxlbSB0byBoYXBwZW4uCj4KPiAgRG8geW91IGhhdmUgdGhlIHNhbWUgc2l0dWF0aW9uPyBP
ciBzb21lb25lIGVsc2UgaGFzIHRoZSBzYW1lIHByb2JsZW0/IEkKPiB3aWxsIGFwcHJlY2lhdGUg
aWYgeW91IGNhbiBzaGFyZSB5b3VyIGV4cGVyaWVuY2UuIFRoYW5rcyBhIGxvdC4KPgo+ICBCUgo+
ICBNaW5nCj4KPgo+Cj4gIF9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4gIERhdGU6
IFdlZCwgMiBBcHIgMjAwOCAwNzoyMDo0MyArMDAwMAo+IEZyb206IGpvaGFhaG5AZ21haWwuY29t
Cj4gVG86IG1oQG9tbmlzeXMuc2UKPgo+IFN1YmplY3Q6IFJlOiBYaWxpbnggTExURU1BQyBkcml2
ZXIgaXNzdWVzCj4gQ0M6IGxpbnV4cHBjLWVtYmVkZGVkQG96bGFicy5vcmc7IEpvaG4uTGlubkB4
aWxpbnguY29tOyBnaXRAeGlsaW54LmNvbQo+Cj4KPgo+IEkndmUgc29sdmVkIHRoaXMgY2hlY2tz
dW0gb2ZmbG9hZGluZyBpc3N1ZSB3aXRoIHRoaXMgYmVsb3cgcGF0Y2guCj4gSXQgbWF5IGhlbHAs
IGlmIHlvdSBuZWVkIHBlcmZvcm1hbmNlLiBJdCBjZXJ0YWlubHkgbmVlZHMgcmV2aWV3IGJ1dCBp
dCB3b3Jrcwo+IG9uIG15IHNpZGUuCj4KPiAtLS0geGlsaW54Z2l0L2RyaXZlcnMvbmV0L3hpbGlu
eAo+IF9sbHRlbWFjL3hsbHRlbWFjX21haW4uYy5vcmlnICAgIDIwMDgtMDMtMjEgMDk6MTE6NDMu
MDAwMDAwMDAwICswMTAwCj4gKysrIHhpbGlueGdpdC9kcml2ZXJzL25ldC94aWxpbnhfbGx0ZW1h
Yy94bGx0ZW1hY19tYWluLmMgICAgMjAwOC0wMy0yMQo+IDA5OjI0OjIzLjAwMDAwMDAwMCArMDEw
MAo+IEBAIC0xMzMsNyArMTMzLDcgQEAKPiAgICAgICAgICAoWExsRG1hX21CZFJlYWQoKEJkUHRy
KSwgWExMRE1BX0JEX1NUU0NUUkxfVVNSMF9PRkZTRVQpKSAmCj4gMHhGRkZGRkZGRSApCj4KPiAg
I2RlZmluZSBCZENzdW1TZXR1cChCZFB0ciwgU3RhcnQsIEluc2VydCkgXAo+IC0gICAgWExsRG1h
X21CZFdyaXRlKChCZFB0ciksIFhMTERNQV9CRF9VU1IxX09GRlNFVCwgKFN0YXJ0KSA8PCAxNiB8
Cj4gKEluc2VydCkpCj4gKyAgICBYTGxEbWFfbUJkV3JpdGUoKEJkUHRyKSwgWExMRE1BX0JEX1VT
UjFfT0ZGU0VULCAoKFN0YXJ0KSA8PCAxNikgfAo+IChJbnNlcnQpKQo+Cj4gIC8qIFVzZWQgZm9y
IGRlYnVnZ2luZyAqLwo+ICAjZGVmaW5lIEJkQ3N1bUluc2VydChCZFB0cikgXAo+IEBAIC0xNTQw
LDcgKzE1NDEsNyBAQCBzdGF0aWMgaW50IHhlbmV0X0RtYVNlbmRfaW50ZXJuYWwoc3RydWN0Cj4g
ICAgICAvKgo+ICAgICAgICogaWYgdHggY2hlY2tzdW0gb2ZmbG9hZGluZyBpcyBlbmFibGVkLCB3
aGVuIHRoZSBldGhlcm5ldCBzdGFjawo+ICAgICAgICogd2FudHMgdXMgdG8gcGVyZm9ybSB0aGUg
Y2hlY2tzdW0gaW4gaGFyZHdhcmUsCj4gLSAgICAgKiBza2ItPmlwX3N1bW1lZCBpcyBDSEVDS1NV
TV9DT01QTEVURS4gT3RoZXJ3aXNlIHNrYi0+aXBfc3VtbWVkIGlzCj4gKyAgICAgKiBza2ItPmlw
X3N1bW1lZCBpcyBDSEVDS1NVTV9QQVJUSUFMLiBPdGhlcndpc2Ugc2tiLT5pcF9zdW1tZWQgaXMK
PiAgICAgICAqIENIRUNLU1VNX05PTkUsIG1lYW5pbmcgdGhlIGNoZWNrc3VtIGlzIGFscmVhZHkg
ZG9uZSwgb3IKPiAgICAgICAqIENIRUNLU1VNX1VOTkVDRVNTQVJZLCBtZWFuaW5nIGNoZWNrc3Vt
bWluZyBpcyB0dXJuZWQgb2ZmIChlLmcuCj4gICAgICAgKiBsb29wYmFjayBpbnRlcmZhY2UpCj4g
QEAgLTE1NjUsOSArMTU2NiwxMSBAQCBzdGF0aWMgaW50IHhlbmV0X0RtYVNlbmRfaW50ZXJuYWwo
c3RydWN0Cj4gICAgICAgKiBza2JfdHJhbnNwb3J0X2hlYWRlcihza2IpIHBvaW50cyB0byB0aGUg
YmVnaW5uaW5nIG9mIHRoZSBpcCBoZWFkZXIKPiAgICAgICAqCj4gICAgICAgKi8KPiAtICAgIGlm
IChza2ItPmlwX3N1bW1lZCA9PSBDSEVDS1NVTV9DT01QTEVURSkgewo+ICsgICAgaWYgKHNrYi0+
aXBfc3VtbWVkID09IENIRUNLU1VNX1BBUlRJQUwpIHsKPiArCj4gKyAgICAgICAgdW5zaWduZWQg
aW50IGNzdW1fc3RhcnRfb2ZmID0gc2tiX3RyYW5zcG9ydF9vZmZzZXQoc2tiKTsKPiArICAgICAg
ICB1bnNpZ25lZCBpbnQgY3N1bV9pbmRleF9vZmYgPSBjc3VtX3N0YXJ0X29mZiArIHNrYi0+Y3N1
bV9vZmZzZXQ7Cj4KPiAtICAgICAgICB1bnNpZ25lZCBjaGFyICpyYXcgPSBza2JfdHJhbnNwb3J0
X2hlYWRlcihza2IpOwo+ICAjaWYgMAo+ICAgICAgICAgIHsKPiAgICAgICAgICAgICAgdW5zaWdu
ZWQgaW50IGNzdW0gPSBfeGVuZXRfdHhfY3N1bShza2IpOwo+IEBAIC0xNTc4LDkgKzE1ODEsOCBA
QCBzdGF0aWMgaW50IHhlbmV0X0RtYVNlbmRfaW50ZXJuYWwoc3RydWN0Cj4gICAgICAgICAgfQo+
ICAjZWxzZQo+ICAgICAgICAgIEJkQ3N1bUVuYWJsZShiZF9wdHIpOwo+IC0gICAgICAgIEJkQ3N1
bVNldHVwKGJkX3B0ciwgcmF3IC0gc2tiLT5kYXRhLAo+IC0gICAgICAgICAgICAgICAgKHJhdyAt
IHNrYi0+ZGF0YSkgKyBza2ItPmNzdW0pOwo+IC0KPiArICAgICAgICBCZENzdW1TZXR1cChiZF9w
dHIsIGNzdW1fc3RhcnRfb2ZmLAo+ICsgICAgICAgICAgICAgICAgY3N1bV9pbmRleF9vZmYpOwo+
ICAjZW5kaWYKPiAgICAgICAgICBscC0+dHhfaHdfY3N1bXMrKzsKPiAgICAgIH0KPiBAQCAtMzI3
Nyw3ICszMjc5LDcgQEAgc3RhdGljIGludCBfX2RldmluaXQgeHRlbmV0X29mX3Byb2JlKHN0cgo+
ICAgICAgc3RydWN0IHJlc291cmNlICpyX2lycSA9ICZyX2lycV9zdHJ1Y3Q7ICAgIC8qIEludGVy
cnVwdCByZXNvdXJjZXMgKi8KPiAgICAgIHN0cnVjdCByZXNvdXJjZSAqcl9tZW0gPSAmcl9tZW1f
c3RydWN0OyAgICAvKiBJTyBtZW0gcmVzb3VyY2VzICovCj4gICAgICBzdHJ1Y3QgeGxsdGVtYWNf
cGxhdGZvcm1fZGF0YSAqcGRhdGEgPSAmcGRhdGFfc3RydWN0Owo+IC0gICAgICAgIHZvaWQgKm1h
Y19hZGRyZXNzOwo+ICsgICAgICAgIGNvbnN0IHZvaWQgKm1hY19hZGRyZXNzOwo+ICAgICAgaW50
IHJjID0gMDsKPiAgICAgIGNvbnN0IHBoYW5kbGUgKmxsaW5rX2Nvbm5lY3RlZF9oYW5kbGU7Cj4g
ICAgICBzdHJ1Y3QgZGV2aWNlX25vZGUgKmxsaW5rX2Nvbm5lY3RlZF9ub2RlOwo+Cj4KPiBPbiBN
b24sIE1hciAzMSwgMjAwOCBhdCAxMToxMCBBTSwgTWFnbnVzIEhqb3J0aCA8bWhAb21uaXN5cy5z
ZT4gd3JvdGU6Cj4KPiBEZWFjdGl2YXRpbmcgY2hlY2tzdW0gb2ZmbG9hZGluZyBoZWxwZWQgYSBs
b3QhIEkgc3RpbGwgaGF2ZSBzb21lIHBhY2tldCBsb3NzCj4gYW5kIG5vdCB0aGUgYmVzdCBwZXJm
b3JtYW5jZSAoVEZUUCB0cmFuc2ZlciBhYm91dCAxMDAga2J5dGUvcykgYnV0IGF0IGxlYXN0Cj4g
aXQgd29ya3MuCj4KPiBUaGFua3MhCj4KPiAvL01hZ251cwo+Cj4KPgo+Cj4gPiAtLS0tLU9yaWdp
bmFsIE1lc3NhZ2UtLS0tLQo+ID4gRnJvbTogcnphMSBbbWFpbHRvOnJ6YTFAc28tbG9naWMubmV0
XQo+ID4gU2VudDogZGVuIDMxIG1hcnMgMjAwOCAxMToxNAo+ID4gVG86IE1hZ251cyBIam9ydGgK
PiA+IENjOiBKb2huIExpbm47IGdpdDsgbGludXhwcGMtZW1iZWRkZWRAb3psYWJzLm9yZwo+ID4g
U3ViamVjdDogUmU6IFhpbGlueCBMTFRFTUFDIGRyaXZlciBpc3N1ZXMKPiA+Cj4gPiBIaSBNYWdu
dXMsCj4gPgo+ID4gMS4KPiA+IEkgYW0gdXNpbmcgbmVhcmx5IHRoZSBzYW1lIHZlcnNpb25zIHRo
ZW4geW91IGFuZCBnb3QgdGhlIHNhbWUgcHJvYmxlbXMKPiA+IHRvbyA7LSkuCj4gPiBJIHRoaW5r
IHRoZXJlIGFyZSBzb21lIHByb2JsZW1zIHdpdGggdGhlIGNoZWNrc3VtIG9mZmxvYWRpbmcuCj4g
PiBUcnkgdG8gc25pZmYgdGhlIHNvbWUgcGFja2FnZXMgKGUuZy4gd2lyZXNoYXJrKS4uLgo+ID4g
Rm9yIG1lIElDTVAgKHBpbmcpIHdvcmtlZCBidXQgdWRwIGFuZCB0Y3Agbm90IChiZWNhdXNlIG9m
ZiBhIHdyb25nCj4gPiBjaGVja3N1bSBpbiB0aGUgdHJhbnNwb3J0IGxheWVyKS4KPiA+IEEgcXVp
Y2sgc29sdXRpb24gaXMgdG8ganVzdCBkZWFjdGl2YXRlIGNoZWNrc3VtIG9mZmxvYWRpbmcuCj4g
Pgo+ID4gMi4KPiA+IEkgcmVtZW1iZXIgc29tZSBwcm9ibGVtcyB3aXRoIFZpcnRleC00IHByZXNh
bXBsZXMgdG9vLgo+ID4gVGhlcmUgd2hlcmUgcHJvYmxlbXMgd2l0aCB0aGUgaGFyZC10ZW1hYyB3
cmFwcGVyLiBZb3UgaGFkIHRvIHVzZSAxLjAwLmEKPiA+IGFuZCBub3QgYiB2ZXJzaW9uLgo+ID4g
QnV0IEkgZG9uJ3QgaGF2ZSB0aGVzZSBwcm9ibGVtcyB3aXRoIHRoZSBFREsgOS4yc3AyL0lTRTku
MnNwMyBhbnltb3JlLgo+ID4KPiA+IGFsbCB0aGUgYmVzdCwKPiA+IFJvYmVydAo+ID4KPiA+IE1h
Z251cyBIam9ydGggd3JvdGU6Cj4gPiA+IEhpIEpvaG4sCj4gPiA+Cj4gPiA+IFRoYW5rcyBmb3Ig
dGhlIHZlcnkgZmFzdCByZXBseSEgUmlnaHQgbm93IEknbSBub3QgYXQgd29yayBzbyBJIGRvbid0
Cj4gPiA+IGhhdmUgdGhlIGJvYXJkIG9yIEVESyBoZXJlIHRvIHRlc3QgYW55dGhpbmcuCj4gPiA+
Cj4gPiA+IEknbSB1c2luZyBjaGVja3N1bSBvZmZsb2FkLCBidXQgSSBkb24ndCBrbm93IGlmIERS
RSBpcyBlbmFibGVkIG9yIG5vdC4gSQo+ID4gPiBjYW4ndCByZWNhbGwgc2VlaW5nIGFueSBzZXR0
aW5nIHRvIGVuYWJsZS9kaXNhYmxlIERSRS4uCj4gPiA+Cj4gPiA+IEEgZmV3IHRoaW5ncyB0aGF0
IGNyb3NzZWQgbXkgbWluZDoKPiA+ID4KPiA+ID4gTGFzdCB5ZWFyIEkgZGlkIGEgZGVzaWduIHdp
dGggRURLIDguMiwgYmFjayB0aGVuIHRoZXJlIHdhcyBhbiBpc3N1ZSB3aXRoCj4gPiA+IHRoZSBN
TDQwMyBib2FyZHMgaGF2aW5nIGFuIG9sZCByZXZpc2lvbiBvZiB0aGUgRlBHQSB3aGljaCB3YXNu
J3QKPiA+ID4gY29tcGF0aWJsZSB3aXRoIHNvbWUgdmVyc2lvbnMgb2YgdGhlIElQIGNvcmUuIFRo
ZXJlIGFyZSBubyBzdWNoIHZlcnNpb24KPiA+ID4gaXNzdWVzIHdpdGggdGhlIHhwc19sbF90ZW1h
Yz8KPiA+ID4KPiA+ID4gSSBkb24ndCB0aGluayB0aGF0IEkgaGFkIHBoeS1hZGRyIHNldCBpbiB0
aGUgRFRTIGZpbGUuIFdpbGwgdGVzdCB0aGF0IG9uCj4gPiA+IE1vbmRheS4KPiA+ID4KPiA+ID4g
QmVzdCByZWdhcmRzLAo+ID4gPiBNYWdudXMKPiA+ID4KPiA+ID4KPiA+ID4gT24gU2F0LCAyMDA4
LTAzLTI5IGF0IDA3OjU4IC0wNjAwLCBKb2huIExpbm4gd3JvdGU6Cj4gPiA+Cj4gPiA+PiBIaSBN
YWdudXMsCj4gPiA+Pgo+ID4gPj4gU29ycnkgdG8gaGVhciB5b3UncmUgaGF2aW5nIHByb2JsZW1z
IHdpdGggaXQuCj4gPiA+Pgo+ID4gPj4gSSBhbSBkb2luZyB0ZXN0aW5nIG9uIGFuIE1MNDA1IHdo
aWNoIGlzIHRoZSBzYW1lIGJvYXJkIGJ1dCB3aXRoIGEKPiBiaWdnZXIKPiA+IEZQR0EsIGJ1dCB3
aXRoIHBwYyBhcmNoIGFuZCBJIGRvbid0IHNlZSB0aGlzIGlzc3VlLiBJIGhhdmUgZG9uZSBsaW1p
dGVkCj4gdGVzdGluZwo+ID4gd2l0aCBwb3dlcnBjIGFyY2ggYW5kIHRoZSBMTCBURU1BQywgYnV0
IEkgZGlkbid0IHNlZSB0aGlzIGlzc3VlIHRoZXJlCj4gZWl0aGVyLgo+ID4gUG93ZXJwYyBhcmNo
IGlzIGRlZmluaXRlbHkgbGVzcyBtYXR1cmUgaW4gbXkgZXhwZXJpZW5jZSB0aGFuIHRoZSBwcGMg
YXJjaC4KPiBJJ2xsCj4gPiBkbyBhIHF1aWNrIHRlc3Qgd2l0aCBteSBwb3dlcnBjIGFyY2ggYW5k
IG1ha2Ugc3VyZSBhZ2FpbiBJJ20gbm90IHNlZWluZwo+IGl0Lgo+ID4gPj4KPiA+ID4+IE15IGtl
cm5lbCBpcyBmcm9tIHRoZSBYaWxpbnggR2l0IHRyZWUsIGJ1dCB0aGVyZSBoYXZlIGJlZW4gYSBu
dW1iZXIgb2YKPiA+IGNoYW5nZXMgd2UgaGF2ZSBwdXNoZWQgb3V0IHNvIEkgZG9uJ3Qga25vdyBo
b3cgbG9uZyBhZ28geW91IHB1bGxlZCBmcm9tCj4gdGhlIEdpdAo+ID4gdHJlZS4KPiA+ID4+Cj4g
PiA+PiBNeSBFREsgcHJvamVjdCBpcyAxMC4xIHNvIGl0J3MgYSBsaXR0bGUgbmV3ZXIuIEkgYW0g
dXNpbmcgTEwgVEVNQUMKPiAxLjAxYSBzbwo+ID4gaXQncyBhIGxpdHRsZSBuZXdlci4gIEkgcmV2
aWV3ZWQgdGhlIGNoYW5nZSBsb2cgZm9yIHRoZSBMTCBURU1BQyBhbmQgZG9uJ3QKPiBzZWUKPiA+
IGFueSBiaWcgcHJvYmxlbXMgdGhhdCB3ZXJlIGZpeGVkIGluIHRoZSBuZXdlciB2ZXJzaW9ucywg
bW9yZSBuZXcgZmVhdHVyZXMuCj4gSSdsbAo+ID4gY2hlY2sgd2l0aCBzb21lIG90aGVycyBoZXJl
IHRvIHNlZSBpZiBJIG1pc3NlZCBzb21ldGhpbmcgdGhlcmUuCj4gPiA+Pgo+ID4gPj4gSSBhbSB1
c2luZyBETUEgYWxzbywgYnV0IG5vIERSRSBvciBjaGVja3N1bSBvZmZsb2FkLiAgWW91IGRpZG4n
dCBzYXkKPiBhbnl0aGluZwo+ID4gYWJvdXQgdGhvc2UuIEknbSBnb2luZyB0byBpbnNlcnQgbXkg
bWhzIGZpbGUgdGhhdCBkZXNjcmliZXMgbXkgc3lzdGVtIHRvCj4gbGV0IHlvdQo+ID4gY29tcGFy
ZSB5b3VyIHN5c3RlbSBjb25maWd1cmF0aW9uLiBJdCdzIG5vdCBjbGVhciB0byBtZSB5ZXQgaWYg
eW91IGhhdmUgYQo+IGgvdyBvcgo+ID4gcy93IHByb2JsZW0uCj4gPiA+Pgo+ID4gPj4gSSdsbCBh
bHNvIGluc2VydCBzb21lIG9mIG15IGRldmljZSB0cmVlIHdpdGggdGhlIExMIFRFTUFDIHNvIHlv
dSBjYW4KPiBjb21wYXJlCj4gPiAoaWdub3JlIDE2NTUwIHN0dWZmIGFzIHdlIGFyZSBzdGlsbCB3
b3JraW5nIG9uIHRoYXQpLgo+ID4gPj4KPiA+ID4+IFNpbmNlIHlvdSBjYW4ndCBwaW5nIHJlbGlh
Ymx5IEkgd291bGQgcHJvYmFibHkgZm9jdXMgb24gdGhhdCBzaW5jZSBpdCdzCj4gPiBzaW1wbGVy
IHRoYW4gdGhlIG90aGVyIGlzc3VlcyB5b3UncmUgc2VlaW5nLgo+ID4gPj4KPiA+ID4+IFRoYW5r
cywKPiA+ID4+IEpvaG4KPiA+ID4+Cj4gPiA+Pgo+ID4gPj4KPiA+ID4+ICMKPiA+Cj4gIyMjIyMj
IyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMj
IyMjIyMjIyMjIyMjIyMjCj4gPiA+PiAjIENyZWF0ZWQgYnkgQmFzZSBTeXN0ZW0gQnVpbGRlciBX
aXphcmQgZm9yIFhpbGlueCBFREsgMTAuMS4xIEJ1aWxkCj4gPiBFREtfS19TUDEuMQo+ID4gPj4g
IyBUaHUgRmViIDE0IDE0OjExOjEyIDIwMDgKPiA+ID4+ICMgVGFyZ2V0IEJvYXJkOiAgWGlsaW54
IFZpcnRleCA0IE1MNDA1IEV2YWx1YXRpb24gUGxhdGZvcm0gUmV2IDEKPiA+ID4+ICMgRmFtaWx5
OiAgICB2aXJ0ZXg0Cj4gPiA+PiAjIERldmljZTogICAgeGM0dmZ4MjAKPiA+ID4+ICMgUGFja2Fn
ZTogICBmZjY3Mgo+ID4gPj4gIyBTcGVlZCBHcmFkZTogIC0xMAo+ID4gPj4gIyBQcm9jZXNzb3I6
IHBwYzQwNV8wCj4gPiA+PiAjIFByb2Nlc3NvciBjbG9jayBmcmVxdWVuY3k6IDMwMC4wMCBNSHoK
PiA+ID4+ICMgQnVzIGNsb2NrIGZyZXF1ZW5jeTogMTAwLjAwIE1Iego+ID4gPj4gIyBPbiBDaGlw
IE1lbW9yeSA6ICAgOCBLQgo+ID4gPj4gIyBUb3RhbCBPZmYgQ2hpcCBNZW1vcnkgOiAxMjggTUIK
PiA+ID4+ICMgLSBERFJfU0RSQU0gPSAxMjggTUIKPiA+ID4+ICMKPiA+Cj4gIyMjIyMjIyMjIyMj
IyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMj
IyMjIyMjIyMjCj4gPiA+PiAgUEFSQU1FVEVSIFZFUlNJT04gPSAyLjEuMAo+ID4gPj4KPiA+ID4+
Cj4gPiA+PiAgUE9SVCBmcGdhXzBfUlMyMzJfVWFydF9zaW5fcGluID0gZnBnYV8wX1JTMjMyX1Vh
cnRfc2luLCBESVIgPSBJCj4gPiA+PiAgUE9SVCBmcGdhXzBfUlMyMzJfVWFydF9zb3V0X3BpbiA9
IGZwZ2FfMF9SUzIzMl9VYXJ0X3NvdXQsIERJUiA9IE8KPiA+ID4+ICBQT1JUIGZwZ2FfMF9MRURz
XzRCaXRfR1BJT19JT19waW4gPSBmcGdhXzBfTEVEc180Qml0X0dQSU9fSU8sIERJUiA9Cj4gSU8s
IFZFQwo+ID4gPSBbMDozXQo+ID4gPj4gIFBPUlQgZnBnYV8wX0lJQ19FRVBST01fU2NsX3BpbiA9
IGZwZ2FfMF9JSUNfRUVQUk9NX1NjbCwgRElSID0gSU8KPiA+ID4+ICBQT1JUIGZwZ2FfMF9JSUNf
RUVQUk9NX1NkYV9waW4gPSBmcGdhXzBfSUlDX0VFUFJPTV9TZGEsIERJUiA9IElPCj4gPiA+PiAg
UE9SVCBmcGdhXzBfU3lzQUNFX0NvbXBhY3RGbGFzaF9TeXNBQ0VfQ0xLX3BpbiA9Cj4gPiBmcGdh
XzBfU3lzQUNFX0NvbXBhY3RGbGFzaF9TeXNBQ0VfQ0xLLCBESVIgPSBJCj4gPiA+PiAgUE9SVCBm
cGdhXzBfU3lzQUNFX0NvbXBhY3RGbGFzaF9TeXNBQ0VfTVBBX3BpbiA9Cj4gPiBmcGdhXzBfU3lz
QUNFX0NvbXBhY3RGbGFzaF9TeXNBQ0VfTVBBLCBESVIgPSBPLCBWRUMgPSBbNjoxXQo+ID4gPj4g
IFBPUlQgZnBnYV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX01QRF9waW4gPQo+ID4gZnBn
YV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX01QRCwgRElSID0gSU8sIFZFQyA9IFsxNTow
XQo+ID4gPj4gIFBPUlQgZnBnYV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX0NFTl9waW4g
PQo+ID4gZnBnYV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX0NFTiwgRElSID0gTwo+ID4g
Pj4gIFBPUlQgZnBnYV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX09FTl9waW4gPQo+ID4g
ZnBnYV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX09FTiwgRElSID0gTwo+ID4gPj4gIFBP
UlQgZnBnYV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX1dFTl9waW4gPQo+ID4gZnBnYV8w
X1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX1dFTiwgRElSID0gTwo+ID4gPj4gIFBPUlQgZnBn
YV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX01QSVJRX3BpbiA9Cj4gPiBmcGdhXzBfU3lz
QUNFX0NvbXBhY3RGbGFzaF9TeXNBQ0VfTVBJUlEsIERJUiA9IEkKPiA+ID4+ICBQT1JUIGZwZ2Ff
MF9ERFJfU0RSQU1fRERSX0Nsa19waW4gPSBmcGdhXzBfRERSX1NEUkFNX0REUl9DbGssIERJUiA9
IE8KPiA+ID4+ICBQT1JUIGZwZ2FfMF9ERFJfU0RSQU1fRERSX0Nsa19uX3BpbiA9IGZwZ2FfMF9E
RFJfU0RSQU1fRERSX0Nsa19uLCBESVIKPiA9IE8KPiA+ID4+ICBQT1JUIGZwZ2FfMF9ERFJfU0RS
QU1fRERSX0FkZHJfcGluID0gZnBnYV8wX0REUl9TRFJBTV9ERFJfQWRkciwgRElSID0KPiBPLCBW
RUMKPiA+ID0gWzEyOjBdCj4gPiA+PiAgUE9SVCBmcGdhXzBfRERSX1NEUkFNX0REUl9CYW5rQWRk
cl9waW4gPQo+IGZwZ2FfMF9ERFJfU0RSQU1fRERSX0JhbmtBZGRyLCBESVIKPiA+ID0gTywgVkVD
ID0gWzE6MF0KPiA+ID4+ICBQT1JUIGZwZ2FfMF9ERFJfU0RSQU1fRERSX0NBU19uX3BpbiA9IGZw
Z2FfMF9ERFJfU0RSQU1fRERSX0NBU19uLCBESVIKPiA9IE8KPiA+ID4+ICBQT1JUIGZwZ2FfMF9E
RFJfU0RSQU1fRERSX0NFX3BpbiA9IGZwZ2FfMF9ERFJfU0RSQU1fRERSX0NFLCBESVIgPSBPCj4g
PiA+PiAgUE9SVCBmcGdhXzBfRERSX1NEUkFNX0REUl9DU19uX3BpbiA9IGZwZ2FfMF9ERFJfU0RS
QU1fRERSX0NTX24sIERJUiA9Cj4gTwo+ID4gPj4gIFBPUlQgZnBnYV8wX0REUl9TRFJBTV9ERFJf
UkFTX25fcGluID0gZnBnYV8wX0REUl9TRFJBTV9ERFJfUkFTX24sIERJUgo+ID0gTwo+ID4gPj4g
IFBPUlQgZnBnYV8wX0REUl9TRFJBTV9ERFJfV0Vfbl9waW4gPSBmcGdhXzBfRERSX1NEUkFNX0RE
Ul9XRV9uLCBESVIgPQo+IE8KPiA+ID4+ICBQT1JUIGZwZ2FfMF9ERFJfU0RSQU1fRERSX0RNX3Bp
biA9IGZwZ2FfMF9ERFJfU0RSQU1fRERSX0RNLCBESVIgPSBPLAo+IFZFQyA9Cj4gPiBbMzowXQo+
ID4gPj4gIFBPUlQgZnBnYV8wX0REUl9TRFJBTV9ERFJfRFFTID0gZnBnYV8wX0REUl9TRFJBTV9E
RFJfRFFTLCBESVIgPSBJTywKPiBWRUMgPQo+ID4gWzM6MF0KPiA+ID4+ICBQT1JUIGZwZ2FfMF9E
RFJfU0RSQU1fRERSX0RRID0gZnBnYV8wX0REUl9TRFJBTV9ERFJfRFEsIERJUiA9IElPLCBWRUMK
PiA9Cj4gPiBbMzE6MF0KPiA+ID4+ICBQT1JUIGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX0dNSUlf
VFhEXzBfcGluID0KPiA+IGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX0dNSUlfVFhEXzAsIERJUiA9
IE8sIFZFQyA9IFs3OjBdCj4gPiA+PiAgUE9SVCBmcGdhXzBfVHJpTW9kZV9NQUNfR01JSV9HTUlJ
X1RYX0VOXzBfcGluID0KPiA+IGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX0dNSUlfVFhfRU5fMCwg
RElSID0gTwo+ID4gPj4gIFBPUlQgZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlfR01JSV9UWF9FUl8w
X3BpbiA9Cj4gPiBmcGdhXzBfVHJpTW9kZV9NQUNfR01JSV9HTUlJX1RYX0VSXzAsIERJUiA9IE8K
PiA+ID4+ICBQT1JUIGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX0dNSUlfVFhfQ0xLXzBfcGluID0K
PiA+IGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX0dNSUlfVFhfQ0xLXzAsIERJUiA9IE8KPiA+ID4+
ICBQT1JUIGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX0dNSUlfUlhEXzBfcGluID0KPiA+IGZwZ2Ff
MF9UcmlNb2RlX01BQ19HTUlJX0dNSUlfUlhEXzAsIERJUiA9IEksIFZFQyA9IFs3OjBdCj4gPiA+
PiAgUE9SVCBmcGdhXzBfVHJpTW9kZV9NQUNfR01JSV9HTUlJX1JYX0RWXzBfcGluID0KPiA+IGZw
Z2FfMF9UcmlNb2RlX01BQ19HTUlJX0dNSUlfUlhfRFZfMCwgRElSID0gSQo+ID4gPj4gIFBPUlQg
ZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlfR01JSV9SWF9FUl8wX3BpbiA9Cj4gPiBmcGdhXzBfVHJp
TW9kZV9NQUNfR01JSV9HTUlJX1JYX0VSXzAsIERJUiA9IEkKPiA+ID4+ICBQT1JUIGZwZ2FfMF9U
cmlNb2RlX01BQ19HTUlJX0dNSUlfUlhfQ0xLXzBfcGluID0KPiA+IGZwZ2FfMF9UcmlNb2RlX01B
Q19HTUlJX0dNSUlfUlhfQ0xLXzAsIERJUiA9IEkKPiA+ID4+ICBQT1JUIGZwZ2FfMF9UcmlNb2Rl
X01BQ19HTUlJX01JSV9UWF9DTEtfMF9waW4gPQo+ID4gZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlf
TUlJX1RYX0NMS18wLCBESVIgPSBJCj4gPiA+PiAgUE9SVCBmcGdhXzBfVHJpTW9kZV9NQUNfR01J
SV9NRElPXzBfcGluID0KPiBmcGdhXzBfVHJpTW9kZV9NQUNfR01JSV9NRElPXzAsCj4gPiBESVIg
PSBJTwo+ID4gPj4gIFBPUlQgZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlfTURDXzBfcGluID0KPiBm
cGdhXzBfVHJpTW9kZV9NQUNfR01JSV9NRENfMCwgRElSCj4gPiA9IE8KPiA+ID4+ICBQT1JUIGZw
Z2FfMF9UcmlNb2RlX01BQ19HTUlJX1RlbWFjUGh5X1JTVF9uX3BpbiA9Cj4gPiBmcGdhXzBfVHJp
TW9kZV9NQUNfR01JSV9UZW1hY1BoeV9SU1RfbiwgRElSID0gTwo+ID4gPj4gIFBPUlQgc3lzX2Ns
a19waW4gPSBkY21fY2xrX3MsIERJUiA9IEksIFNJR0lTID0gQ0xLLCBDTEtfRlJFUSA9Cj4gMTAw
MDAwMDAwCj4gPiA+PiAgUE9SVCBzeXNfcnN0X3BpbiA9IHN5c19yc3RfcywgRElSID0gSSwgUlNU
X1BPTEFSSVRZID0gMCwgU0lHSVMgPSBSU1QKPiA+ID4+Cj4gPiA+Pgo+ID4gPj4gQkVHSU4gcHBj
NDA1X3ZpcnRleDQKPiA+ID4+ICBQQVJBTUVURVIgSU5TVEFOQ0UgPSBwcGM0MDVfMAo+ID4gPj4g
IFBBUkFNRVRFUiBIV19WRVIgPSAyLjAxLmEKPiA+ID4+ICBQQVJBTUVURVIgQ19GQVNURVNUX1BM
Ql9DTE9DSyA9IERQTEIxCj4gPiA+PiAgUEFSQU1FVEVSIENfSURDUl9CQVNFQUREUiA9IDBiMDEw
MDAwMDAwMAo+ID4gPj4gIFBBUkFNRVRFUiBDX0lEQ1JfSElHSEFERFIgPSAwYjAxMTExMTExMTEK
PiA+ID4+ICBCVVNfSU5URVJGQUNFIEpUQUdQUEMgPSBqdGFncHBjXzBfMAo+ID4gPj4gIEJVU19J
TlRFUkZBQ0UgSVBMQjAgPSBwbGIKPiA+ID4+ICBCVVNfSU5URVJGQUNFIERQTEIwID0gcGxiCj4g
PiA+PiAgQlVTX0lOVEVSRkFDRSBJUExCMSA9IHBwYzQwNV8wX2lwbGIxCj4gPiA+PiAgQlVTX0lO
VEVSRkFDRSBEUExCMSA9IHBwYzQwNV8wX2RwbGIxCj4gPiA+PiAgQlVTX0lOVEVSRkFDRSBSRVNF
VFBQQyA9IHBwY19yZXNldF9idXMKPiA+ID4+ICBQT1JUIENQTUM0MDVDTE9DSyA9IHByb2NfY2xr
X3MKPiA+ID4+ICBQT1JUIEVJQ0M0MDVFWFRJTlBVVElSUSA9IEVJQ0M0MDVFWFRJTlBVVElSUQo+
ID4gPj4gRU5ECj4gPiA+Pgo+ID4gPj4gQkVHSU4ganRhZ3BwY19jbnRscgo+ID4gPj4gIFBBUkFN
RVRFUiBJTlNUQU5DRSA9IGp0YWdwcGNfMAo+ID4gPj4gIFBBUkFNRVRFUiBIV19WRVIgPSAyLjAx
LmEKPiA+ID4+ICBCVVNfSU5URVJGQUNFIEpUQUdQUEMwID0ganRhZ3BwY18wXzAKPiA+ID4+IEVO
RAo+ID4gPj4KPiA+ID4+IEJFR0lOIHBsYl92NDYKPiA+ID4+ICBQQVJBTUVURVIgSU5TVEFOQ0Ug
PSBwbGIKPiA+ID4+ICBQQVJBTUVURVIgQ19EQ1JfSU5URkNFID0gMAo+ID4gPj4gIFBBUkFNRVRF
UiBDX05VTV9DTEtfUExCMk9QQl9SRUFSQiA9IDEwMAo+ID4gPj4gIFBBUkFNRVRFUiBIV19WRVIg
PSAxLjAyLmEKPiA+ID4+ICBQT1JUIFBMQl9DbGsgPSBzeXNfY2xrX3MKPiA+ID4+ICBQT1JUIFNZ
U19Sc3QgPSBzeXNfYnVzX3Jlc2V0Cj4gPiA+PiBFTkQKPiA+ID4+Cj4gPiA+PiBCRUdJTiB4cHNf
YnJhbV9pZl9jbnRscgo+ID4gPj4gIFBBUkFNRVRFUiBJTlNUQU5DRSA9IHhwc19icmFtX2lmX2Nu
dGxyXzEKPiA+ID4+ICBQQVJBTUVURVIgSFdfVkVSID0gMS4wMC5hCj4gPiA+PiAgUEFSQU1FVEVS
IENfU1BMQl9OQVRJVkVfRFdJRFRIID0gNjQKPiA+ID4+ICBQQVJBTUVURVIgQ19CQVNFQUREUiA9
IDB4ZmZmZmUwMDAKPiA+ID4+ICBQQVJBTUVURVIgQ19ISUdIQUREUiA9IDB4ZmZmZmZmZmYKPiA+
ID4+ICBCVVNfSU5URVJGQUNFIFNQTEIgPSBwbGIKPiA+ID4+ICBCVVNfSU5URVJGQUNFIFBPUlRB
ID0geHBzX2JyYW1faWZfY250bHJfMV9wb3J0Cj4gPiA+PiBFTkQKPiA+ID4+Cj4gPiA+PiBCRUdJ
TiBicmFtX2Jsb2NrCj4gPiA+PiAgUEFSQU1FVEVSIElOU1RBTkNFID0gcGxiX2JyYW1faWZfY250
bHJfMV9icmFtCj4gPiA+PiAgUEFSQU1FVEVSIEhXX1ZFUiA9IDEuMDAuYQo+ID4gPj4gIEJVU19J
TlRFUkZBQ0UgUE9SVEEgPSB4cHNfYnJhbV9pZl9jbnRscl8xX3BvcnQKPiA+ID4+IEVORAo+ID4g
Pj4KPiA+ID4+IEJFR0lOIHhwc191YXJ0MTY1NTAKPiA+ID4+ICBQQVJBTUVURVIgSU5TVEFOQ0Ug
PSBSUzIzMl9VYXJ0Cj4gPiA+PiAgUEFSQU1FVEVSIEhXX1ZFUiA9IDIuMDAuYQo+ID4gPj4gIFBB
UkFNRVRFUiBDX0lTX0FfMTY1NTAgPSAxCj4gPiA+PiAgUEFSQU1FVEVSIENfQkFTRUFERFIgPSAw
eDgzZTAwMDAwCj4gPiA+PiAgUEFSQU1FVEVSIENfSElHSEFERFIgPSAweDgzZTBmZmZmCj4gPiA+
PiAgQlVTX0lOVEVSRkFDRSBTUExCID0gcGxiCj4gPiA+PiAgUE9SVCBzaW4gPSBmcGdhXzBfUlMy
MzJfVWFydF9zaW4KPiA+ID4+ICBQT1JUIHNvdXQgPSBmcGdhXzBfUlMyMzJfVWFydF9zb3V0Cj4g
PiA+PiAgUE9SVCBJUDJJTlRDX0lycHQgPSBSUzIzMl9VYXJ0X0lQMklOVENfSXJwdAo+ID4gPj4g
RU5ECj4gPiA+Pgo+ID4gPj4gQkVHSU4geHBzX2dwaW8KPiA+ID4+ICBQQVJBTUVURVIgSU5TVEFO
Q0UgPSBMRURzXzRCaXQKPiA+ID4+ICBQQVJBTUVURVIgSFdfVkVSID0gMS4wMC5hCj4gPiA+PiAg
UEFSQU1FVEVSIENfSU5URVJSVVBUX1BSRVNFTlQgPSAxCj4gPiA+PiAgUEFSQU1FVEVSIENfR1BJ
T19XSURUSCA9IDQKPiA+ID4+ICBQQVJBTUVURVIgQ19JU19EVUFMID0gMAo+ID4gPj4gIFBBUkFN
RVRFUiBDX0lTX0JJRElSID0gMQo+ID4gPj4gIFBBUkFNRVRFUiBDX0FMTF9JTlBVVFMgPSAwCj4g
PiA+PiAgUEFSQU1FVEVSIENfQkFTRUFERFIgPSAweDgxNDAwMDAwCj4gPiA+PiAgUEFSQU1FVEVS
IENfSElHSEFERFIgPSAweDgxNDBmZmZmCj4gPiA+PiAgQlVTX0lOVEVSRkFDRSBTUExCID0gcGxi
Cj4gPiA+PiAgUE9SVCBHUElPX0lPID0gZnBnYV8wX0xFRHNfNEJpdF9HUElPX0lPCj4gPiA+PiAg
UE9SVCBJUDJJTlRDX0lycHQgPSBMRURzXzRCaXRfSVAySU5UQ19JcnB0Cj4gPiA+PiBFTkQKPiA+
ID4+Cj4gPiA+PiBCRUdJTiB4cHNfaWljCj4gPiA+PiAgUEFSQU1FVEVSIElOU1RBTkNFID0gSUlD
X0VFUFJPTQo+ID4gPj4gIFBBUkFNRVRFUiBIV19WRVIgPSAyLjAwLmEKPiA+ID4+ICBQQVJBTUVU
RVIgQ19DTEtfRlJFUSA9IDEwMDAwMDAwMAo+ID4gPj4gIFBBUkFNRVRFUiBDX0lJQ19GUkVRID0g
MTAwMDAwCj4gPiA+PiAgUEFSQU1FVEVSIENfVEVOX0JJVF9BRFIgPSAwCj4gPiA+PiAgUEFSQU1F
VEVSIENfQkFTRUFERFIgPSAweDgxNjAwMDAwCj4gPiA+PiAgUEFSQU1FVEVSIENfSElHSEFERFIg
PSAweDgxNjBmZmZmCj4gPiA+PiAgQlVTX0lOVEVSRkFDRSBTUExCID0gcGxiCj4gPiA+PiAgUE9S
VCBTY2wgPSBmcGdhXzBfSUlDX0VFUFJPTV9TY2wKPiA+ID4+ICBQT1JUIFNkYSA9IGZwZ2FfMF9J
SUNfRUVQUk9NX1NkYQo+ID4gPj4gIFBPUlQgSUlDMklOVENfSXJwdCA9IElJQ19FRVBST01fSUlD
MklOVENfSXJwdAo+ID4gPj4gRU5ECj4gPiA+Pgo+ID4gPj4gQkVHSU4geHBzX3N5c2FjZQo+ID4g
Pj4gIFBBUkFNRVRFUiBJTlNUQU5DRSA9IFN5c0FDRV9Db21wYWN0Rmxhc2gKPiA+ID4+ICBQQVJB
TUVURVIgSFdfVkVSID0gMS4wMC5hCj4gPiA+PiAgUEFSQU1FVEVSIENfTUVNX1dJRFRIID0gMTYK
PiA+ID4+ICBQQVJBTUVURVIgQ19CQVNFQUREUiA9IDB4ODM2MDAwMDAKPiA+ID4+ICBQQVJBTUVU
RVIgQ19ISUdIQUREUiA9IDB4ODM2MGZmZmYKPiA+ID4+ICBCVVNfSU5URVJGQUNFIFNQTEIgPSBw
bGIKPiA+ID4+ICBQT1JUIFN5c0FDRV9DTEsgPSBmcGdhXzBfU3lzQUNFX0NvbXBhY3RGbGFzaF9T
eXNBQ0VfQ0xLCj4gPiA+PiAgUE9SVCBTeXNBQ0VfTVBBID0gZnBnYV8wX1N5c0FDRV9Db21wYWN0
Rmxhc2hfU3lzQUNFX01QQV9zcGxpdAo+ID4gPj4gIFBPUlQgU3lzQUNFX01QRCA9IGZwZ2FfMF9T
eXNBQ0VfQ29tcGFjdEZsYXNoX1N5c0FDRV9NUEQKPiA+ID4+ICBQT1JUIFN5c0FDRV9DRU4gPSBm
cGdhXzBfU3lzQUNFX0NvbXBhY3RGbGFzaF9TeXNBQ0VfQ0VOCj4gPiA+PiAgUE9SVCBTeXNBQ0Vf
T0VOID0gZnBnYV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX09FTgo+ID4gPj4gIFBPUlQg
U3lzQUNFX1dFTiA9IGZwZ2FfMF9TeXNBQ0VfQ29tcGFjdEZsYXNoX1N5c0FDRV9XRU4KPiA+ID4+
ICBQT1JUIFN5c0FDRV9NUElSUSA9IGZwZ2FfMF9TeXNBQ0VfQ29tcGFjdEZsYXNoX1N5c0FDRV9N
UElSUQo+ID4gPj4gIFBPUlQgU3lzQUNFX0lSUSA9IFN5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNF
X0lSUQo+ID4gPj4gRU5ECj4gPiA+Pgo+ID4gPj4gQkVHSU4gbXBtYwo+ID4gPj4gIFBBUkFNRVRF
UiBJTlNUQU5DRSA9IEREUl9TRFJBTQo+ID4gPj4gIFBBUkFNRVRFUiBIV19WRVIgPSA0LjAwLmEK
PiA+ID4+ICBQQVJBTUVURVIgQ19OVU1fUE9SVFMgPSAzCj4gPiA+PiAgUEFSQU1FVEVSIENfTUVN
X1BBUlROTyA9IEhZQjI1RDUxMjE2MEJFLTUKPiA+ID4+ICBQQVJBTUVURVIgQ19NRU1fREFUQV9X
SURUSCA9IDMyCj4gPiA+PiAgUEFSQU1FVEVSIENfTUVNX0RRU19XSURUSCA9IDQKPiA+ID4+ICBQ
QVJBTUVURVIgQ19NRU1fRE1fV0lEVEggPSA0Cj4gPiA+PiAgUEFSQU1FVEVSIENfTUVNX1RZUEUg
PSBERFIKPiA+ID4+ICBQQVJBTUVURVIgQ19OVU1fSURFTEFZQ1RSTCA9IDIKPiA+ID4+ICBQQVJB
TUVURVIgQ19JREVMQVlDVFJMX0xPQyA9IElERUxBWUNUUkxfWDBZMy1JREVMQVlDVFJMX1gwWTIK
PiA+ID4+ICBQQVJBTUVURVIgQ19QSU0wX0JBU0VUWVBFID0gMgo+ID4gPj4gIFBBUkFNRVRFUiBD
X1BJTTFfQkFTRVRZUEUgPSAyCj4gPiA+PiAgUEFSQU1FVEVSIENfUElNMl9CQVNFVFlQRSA9IDMK
PiA+ID4+ICBQQVJBTUVURVIgQ19NUE1DX0NMSzBfUEVSSU9EX1BTID0gMTAwMDAKPiA+ID4+ICBQ
QVJBTUVURVIgQ19TRE1BMl9QSTJMTF9DTEtfUkFUSU8gPSAxCj4gPiA+PiAgUEFSQU1FVEVSIENf
TVBNQ19CQVNFQUREUiA9IDB4MDAwMDAwMDAKPiA+ID4+ICBQQVJBTUVURVIgQ19NUE1DX0hJR0hB
RERSID0gMHgwN2ZmZmZmZgo+ID4gPj4gIFBBUkFNRVRFUiBDX1NETUFfQ1RSTF9CQVNFQUREUiA9
IDB4ODQ2MDAwMDAKPiA+ID4+ICBQQVJBTUVURVIgQ19TRE1BX0NUUkxfSElHSEFERFIgPSAweDg0
NjBmZmZmCj4gPiA+PiAgQlVTX0lOVEVSRkFDRSBTUExCMCA9IHBwYzQwNV8wX2lwbGIxCj4gPiA+
PiAgQlVTX0lOVEVSRkFDRSBTUExCMSA9IHBwYzQwNV8wX2RwbGIxCj4gPiA+PiAgQlVTX0lOVEVS
RkFDRSBTRE1BX0xMMiA9IFRyaU1vZGVfTUFDX0dNSUlfTExJTkswCj4gPiA+PiAgQlVTX0lOVEVS
RkFDRSBTRE1BX0NUUkwyID0gcGxiCj4gPiA+PiAgUE9SVCBERFJfQWRkciA9IGZwZ2FfMF9ERFJf
U0RSQU1fRERSX0FkZHIKPiA+ID4+ICBQT1JUIEREUl9CYW5rQWRkciA9IGZwZ2FfMF9ERFJfU0RS
QU1fRERSX0JhbmtBZGRyCj4gPiA+PiAgUE9SVCBERFJfQ0FTX24gPSBmcGdhXzBfRERSX1NEUkFN
X0REUl9DQVNfbgo+ID4gPj4gIFBPUlQgRERSX0NFID0gZnBnYV8wX0REUl9TRFJBTV9ERFJfQ0UK
PiA+ID4+ICBQT1JUIEREUl9DU19uID0gZnBnYV8wX0REUl9TRFJBTV9ERFJfQ1Nfbgo+ID4gPj4g
IFBPUlQgRERSX1JBU19uID0gZnBnYV8wX0REUl9TRFJBTV9ERFJfUkFTX24KPiA+ID4+ICBQT1JU
IEREUl9XRV9uID0gZnBnYV8wX0REUl9TRFJBTV9ERFJfV0Vfbgo+ID4gPj4gIFBPUlQgRERSX0RN
ID0gZnBnYV8wX0REUl9TRFJBTV9ERFJfRE0KPiA+ID4+ICBQT1JUIEREUl9EUVMgPSBmcGdhXzBf
RERSX1NEUkFNX0REUl9EUVMKPiA+ID4+ICBQT1JUIEREUl9EUSA9IGZwZ2FfMF9ERFJfU0RSQU1f
RERSX0RRCj4gPiA+PiAgUE9SVCBERFJfQ2xrID0gZnBnYV8wX0REUl9TRFJBTV9ERFJfQ2xrCj4g
PiA+PiAgUE9SVCBERFJfQ2xrX24gPSBmcGdhXzBfRERSX1NEUkFNX0REUl9DbGtfbgo+ID4gPj4g
IFBPUlQgTVBNQ19DbGswID0gc3lzX2Nsa19zCj4gPiA+PiAgUE9SVCBNUE1DX0NsazkwID0gRERS
X1NEUkFNX21wbWNfY2xrXzkwX3MKPiA+ID4+ICBQT1JUIFNETUEyX0NsayA9IHN5c19jbGtfcwo+
ID4gPj4gIFBPUlQgTVBNQ19DbGtfMjAwTUh6ID0gY2xrXzIwMG1oel9zCj4gPiA+PiAgUE9SVCBN
UE1DX1JzdCA9IHN5c19wZXJpcGhfcmVzZXQKPiA+ID4+ICBQT1JUIFNETUEyX1J4X0ludE91dCA9
IEREUl9TRFJBTV9TRE1BMl9SeF9JbnRPdXQKPiA+ID4+ICBQT1JUIFNETUEyX1R4X0ludE91dCA9
IEREUl9TRFJBTV9TRE1BMl9UeF9JbnRPdXQKPiA+ID4+IEVORAo+ID4gPj4KPiA+ID4+IEJFR0lO
IHhwc19sbF90ZW1hYwo+ID4gPj4gIFBBUkFNRVRFUiBJTlNUQU5DRSA9IFRyaU1vZGVfTUFDX0dN
SUkKPiA+ID4+ICBQQVJBTUVURVIgSFdfVkVSID0gMS4wMS5hCj4gPiA+PiAgUEFSQU1FVEVSIENf
U1BMQl9DTEtfUEVSSU9EX1BTID0gMTAwMDAKPiA+ID4+ICBQQVJBTUVURVIgQ19QSFlfVFlQRSA9
IDEKPiA+ID4+ICBQQVJBTUVURVIgQ19OVU1fSURFTEFZQ1RSTCA9IDQKPiA+ID4+ICBQQVJBTUVU
RVIgQ19JREVMQVlDVFJMX0xPQyA9IElERUxBWUNUUkxfWDFZMS1JREVMQVlDVFJMX1gxWTMtCj4g
PiBJREVMQVlDVFJMX1gyWTItSURFTEFZQ1RSTF9YMlkzCj4gPiA+PiAgUEFSQU1FVEVSIENfVEVN
QUNfVFlQRSA9IDEKPiA+ID4+ICBQQVJBTUVURVIgQ19CVVMyQ09SRV9DTEtfUkFUSU8gPSAxCj4g
PiA+PiAgUEFSQU1FVEVSIENfQkFTRUFERFIgPSAweDgxYzAwMDAwCj4gPiA+PiAgUEFSQU1FVEVS
IENfSElHSEFERFIgPSAweDgxYzBmZmZmCj4gPiA+PiAgQlVTX0lOVEVSRkFDRSBTUExCID0gcGxi
Cj4gPiA+PiAgQlVTX0lOVEVSRkFDRSBMTElOSzAgPSBUcmlNb2RlX01BQ19HTUlJX0xMSU5LMAo+
ID4gPj4gIFBPUlQgR01JSV9UWERfMCA9IGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX0dNSUlfVFhE
XzAKPiA+ID4+ICBQT1JUIEdNSUlfVFhfRU5fMCA9IGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX0dN
SUlfVFhfRU5fMAo+ID4gPj4gIFBPUlQgR01JSV9UWF9FUl8wID0gZnBnYV8wX1RyaU1vZGVfTUFD
X0dNSUlfR01JSV9UWF9FUl8wCj4gPiA+PiAgUE9SVCBHTUlJX1RYX0NMS18wID0gZnBnYV8wX1Ry
aU1vZGVfTUFDX0dNSUlfR01JSV9UWF9DTEtfMAo+ID4gPj4gIFBPUlQgR01JSV9SWERfMCA9IGZw
Z2FfMF9UcmlNb2RlX01BQ19HTUlJX0dNSUlfUlhEXzAKPiA+ID4+ICBQT1JUIEdNSUlfUlhfRFZf
MCA9IGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX0dNSUlfUlhfRFZfMAo+ID4gPj4gIFBPUlQgR01J
SV9SWF9FUl8wID0gZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlfR01JSV9SWF9FUl8wCj4gPiA+PiAg
UE9SVCBHTUlJX1JYX0NMS18wID0gZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlfR01JSV9SWF9DTEtf
MAo+ID4gPj4gIFBPUlQgTUlJX1RYX0NMS18wID0gZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlfTUlJ
X1RYX0NMS18wCj4gPiA+PiAgUE9SVCBNRElPXzAgPSBmcGdhXzBfVHJpTW9kZV9NQUNfR01JSV9N
RElPXzAKPiA+ID4+ICBQT1JUIE1EQ18wID0gZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlfTURDXzAK
PiA+ID4+ICBQT1JUIFRlbWFjUGh5X1JTVF9uID0gZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlfVGVt
YWNQaHlfUlNUX24KPiA+ID4+ICBQT1JUIEdUWF9DTEtfMCA9IHRlbWFjX2Nsa19zCj4gPiA+PiAg
UE9SVCBSRUZDTEsgPSBjbGtfMjAwbWh6X3MKPiA+ID4+ICBQT1JUIExsaW5rVGVtYWMwX0NMSyA9
IHN5c19jbGtfcwo+ID4gPj4gIFBPUlQgVGVtYWNJbnRjMF9JcnB0ID0gVHJpTW9kZV9NQUNfR01J
SV9UZW1hY0ludGMwX0lycHQKPiA+ID4+IEVORAo+ID4gPj4KPiA+ID4+IEJFR0lOIHV0aWxfYnVz
X3NwbGl0Cj4gPiA+PiAgUEFSQU1FVEVSIElOU1RBTkNFID0gU3lzQUNFX0NvbXBhY3RGbGFzaF91
dGlsX2J1c19zcGxpdF8wCj4gPiA+PiAgUEFSQU1FVEVSIEhXX1ZFUiA9IDEuMDAuYQo+ID4gPj4g
IFBBUkFNRVRFUiBDX1NJWkVfSU4gPSA3Cj4gPiA+PiAgUEFSQU1FVEVSIENfTEVGVF9QT1MgPSAw
Cj4gPiA+PiAgUEFSQU1FVEVSIENfU1BMSVQgPSA2Cj4gPiA+PiAgUE9SVCBTaWcgPSBmcGdhXzBf
U3lzQUNFX0NvbXBhY3RGbGFzaF9TeXNBQ0VfTVBBX3NwbGl0Cj4gPiA+PiAgUE9SVCBPdXQxID0g
ZnBnYV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX01QQQo+ID4gPj4gRU5ECj4gPiA+Pgo+
ID4gPj4gQkVHSU4gcGxiX3Y0Ngo+ID4gPj4gIFBBUkFNRVRFUiBJTlNUQU5DRSA9IHBwYzQwNV8w
X2lwbGIxCj4gPiA+PiAgUEFSQU1FVEVSIEhXX1ZFUiA9IDEuMDIuYQo+ID4gPj4gIFBPUlQgUExC
X0NsayA9IHN5c19jbGtfcwo+ID4gPj4gIFBPUlQgU1lTX1JzdCA9IHN5c19idXNfcmVzZXQKPiA+
ID4+IEVORAo+ID4gPj4KPiA+ID4+IEJFR0lOIHBsYl92NDYKPiA+ID4+ICBQQVJBTUVURVIgSU5T
VEFOQ0UgPSBwcGM0MDVfMF9kcGxiMQo+ID4gPj4gIFBBUkFNRVRFUiBIV19WRVIgPSAxLjAyLmEK
PiA+ID4+ICBQT1JUIFBMQl9DbGsgPSBzeXNfY2xrX3MKPiA+ID4+ICBQT1JUIFNZU19Sc3QgPSBz
eXNfYnVzX3Jlc2V0Cj4gPiA+PiBFTkQKPiA+ID4+Cj4gPiA+PiBCRUdJTiBjbG9ja19nZW5lcmF0
b3IKPiA+ID4+ICBQQVJBTUVURVIgSU5TVEFOQ0UgPSBjbG9ja19nZW5lcmF0b3JfMAo+ID4gPj4g
IFBBUkFNRVRFUiBIV19WRVIgPSAyLjAwLmEKPiA+ID4+ICBQQVJBTUVURVIgQ19FWFRfUkVTRVRf
SElHSCA9IDEKPiA+ID4+ICBQQVJBTUVURVIgQ19DTEtJTl9GUkVRID0gMTAwMDAwMDAwCj4gPiA+
PiAgUEFSQU1FVEVSIENfQ0xLT1VUMF9GUkVRID0gMTAwMDAwMDAwCj4gPiA+PiAgUEFSQU1FVEVS
IENfQ0xLT1VUMF9CVUYgPSBUUlVFCj4gPiA+PiAgUEFSQU1FVEVSIENfQ0xLT1VUMF9QSEFTRSA9
IDAKPiA+ID4+ICBQQVJBTUVURVIgQ19DTEtPVVQwX0dST1VQID0gRENNMAo+ID4gPj4gIFBBUkFN
RVRFUiBDX0NMS09VVDFfRlJFUSA9IDEwMDAwMDAwMAo+ID4gPj4gIFBBUkFNRVRFUiBDX0NMS09V
VDFfQlVGID0gVFJVRQo+ID4gPj4gIFBBUkFNRVRFUiBDX0NMS09VVDFfUEhBU0UgPSA5MAo+ID4g
Pj4gIFBBUkFNRVRFUiBDX0NMS09VVDFfR1JPVVAgPSBEQ00wCj4gPiA+PiAgUEFSQU1FVEVSIENf
Q0xLT1VUMl9GUkVRID0gMzAwMDAwMDAwCj4gPiA+PiAgUEFSQU1FVEVSIENfQ0xLT1VUMl9CVUYg
PSBUUlVFCj4gPiA+PiAgUEFSQU1FVEVSIENfQ0xLT1VUMl9QSEFTRSA9IDAKPiA+ID4+ICBQQVJB
TUVURVIgQ19DTEtPVVQyX0dST1VQID0gRENNMAo+ID4gPj4gIFBBUkFNRVRFUiBDX0NMS09VVDNf
RlJFUSA9IDIwMDAwMDAwMAo+ID4gPj4gIFBBUkFNRVRFUiBDX0NMS09VVDNfQlVGID0gVFJVRQo+
ID4gPj4gIFBBUkFNRVRFUiBDX0NMS09VVDNfUEhBU0UgPSAwCj4gPiA+PiAgUEFSQU1FVEVSIENf
Q0xLT1VUM19HUk9VUCA9IE5PTkUKPiA+ID4+ICBQQVJBTUVURVIgQ19DTEtPVVQ0X0ZSRVEgPSAx
MjUwMDAwMDAKPiA+ID4+ICBQQVJBTUVURVIgQ19DTEtPVVQ0X0JVRiA9IFRSVUUKPiA+ID4+ICBQ
QVJBTUVURVIgQ19DTEtPVVQ0X1BIQVNFID0gMAo+ID4gPj4gIFBBUkFNRVRFUiBDX0NMS09VVDRf
R1JPVVAgPSBOT05FCj4gPiA+PiAgUE9SVCBDTEtPVVQwID0gc3lzX2Nsa19zCj4gPiA+PiAgUE9S
VCBDTEtPVVQxID0gRERSX1NEUkFNX21wbWNfY2xrXzkwX3MKPiA+ID4+ICBQT1JUIENMS09VVDIg
PSBwcm9jX2Nsa19zCj4gPiA+PiAgUE9SVCBDTEtPVVQzID0gY2xrXzIwMG1oel9zCj4gPiA+PiAg
UE9SVCBDTEtPVVQ0ID0gdGVtYWNfY2xrX3MKPiA+ID4+ICBQT1JUIENMS0lOID0gZGNtX2Nsa19z
Cj4gPiA+PiAgUE9SVCBMT0NLRUQgPSBEY21fYWxsX2xvY2tlZAo+ID4gPj4gIFBPUlQgUlNUID0g
bmV0X2duZAo+ID4gPj4gRU5ECj4gPiA+Pgo+ID4gPj4gQkVHSU4gcHJvY19zeXNfcmVzZXQKPiA+
ID4+ICBQQVJBTUVURVIgSU5TVEFOQ0UgPSBwcm9jX3N5c19yZXNldF8wCj4gPiA+PiAgUEFSQU1F
VEVSIEhXX1ZFUiA9IDIuMDAuYQo+ID4gPj4gIFBBUkFNRVRFUiBDX0VYVF9SRVNFVF9ISUdIID0g
MAo+ID4gPj4gIEJVU19JTlRFUkZBQ0UgUkVTRVRQUEMwID0gcHBjX3Jlc2V0X2J1cwo+ID4gPj4g
IFBPUlQgU2xvd2VzdF9zeW5jX2NsayA9IHN5c19jbGtfcwo+ID4gPj4gIFBPUlQgRGNtX2xvY2tl
ZCA9IERjbV9hbGxfbG9ja2VkCj4gPiA+PiAgUE9SVCBFeHRfUmVzZXRfSW4gPSBzeXNfcnN0X3MK
PiA+ID4+ICBQT1JUIEJ1c19TdHJ1Y3RfUmVzZXQgPSBzeXNfYnVzX3Jlc2V0Cj4gPiA+PiAgUE9S
VCBQZXJpcGhlcmFsX1Jlc2V0ID0gc3lzX3BlcmlwaF9yZXNldAo+ID4gPj4gRU5ECj4gPiA+Pgo+
ID4gPj4gQkVHSU4geHBzX2ludGMKPiA+ID4+ICBQQVJBTUVURVIgSU5TVEFOQ0UgPSB4cHNfaW50
Y18wCj4gPiA+PiAgUEFSQU1FVEVSIEhXX1ZFUiA9IDEuMDAuYQo+ID4gPj4gIFBBUkFNRVRFUiBD
X0JBU0VBRERSID0gMHg4MTgwMDAwMAo+ID4gPj4gIFBBUkFNRVRFUiBDX0hJR0hBRERSID0gMHg4
MTgwZmZmZgo+ID4gPj4gIEJVU19JTlRFUkZBQ0UgU1BMQiA9IHBsYgo+ID4gPj4gIFBPUlQgSXJx
ID0gRUlDQzQwNUVYVElOUFVUSVJRCj4gPiA+PiAgUE9SVCBJbnRyID0gUlMyMzJfVWFydF9JUDJJ
TlRDX0lycHQgJiBMRURzXzRCaXRfSVAySU5UQ19JcnB0ICYKPiA+IElJQ19FRVBST01fSUlDMklO
VENfSXJwdCAmIFN5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX0lSUSAmCj4gPiBUcmlNb2RlX01B
Q19HTUlJX1RlbWFjSW50YzBfSXJwdCAmIEREUl9TRFJBTV9TRE1BMl9SeF9JbnRPdXQgJgo+ID4g
RERSX1NEUkFNX1NETUEyX1R4X0ludE91dAo+ID4gPj4gRU5ECj4gPiA+Pgo+ID4gPj4KPiA+ID4+
Cj4gPiA+PiAgICAjYWRkcmVzcy1jZWxscyA9IDwxPjsKPiA+ID4+ICAgICNzaXplLWNlbGxzID0g
PDE+Owo+ID4gPj4gICAgY29tcGF0aWJsZSA9ICJ4bG54LHZpcnRleCI7Cj4gPiA+PiAgICBtb2Rl
bCA9ICJ0ZXN0aW5nIjsKPiA+ID4+ICAgIEREUl9TRFJBTTogbWVtb3J5QDAgewo+ID4gPj4gICAg
ICAgICAgICBkZXZpY2VfdHlwZSA9ICJtZW1vcnkiOwo+ID4gPj4gICAgICAgICAgICByZWcgPSA8
IDAgODAwMDAwMCA+Owo+ID4gPj4gICAgfSA7Cj4gPiA+PiAgICBjaG9zZW4gewo+ID4gPj4gICAg
ICAgICAgICBib290YXJncyA9ICJjb25zb2xlPXR0eVMwLDk2MDAgaXA9b24KPiA+IG5mc3Jvb3Q9
MTcyLjE2LjQwLjc2Oi92MnBjbGllbnRzL2pobDI2LHRjcCI7Cj4gPiA+PiAgICAgICAgICAgIGxp
bnV4LHN0ZG91dC1wYXRoID0gIi9wbGJAMC9zZXJpYWxAODNlMDAwMDAiOwo+ID4gPj4gICAgfSA7
Cj4gPiA+PiAgICBjcHVzIHsKPiA+ID4+ICAgICAgICAgICAgI2FkZHJlc3MtY2VsbHMgPSA8MT47
Cj4gPiA+PiAgICAgICAgICAgICNjcHVzID0gPDE+Owo+ID4gPj4gICAgICAgICAgICAjc2l6ZS1j
ZWxscyA9IDwwPjsKPiA+ID4+ICAgICAgICAgICAgcHBjNDA1XzA6IGNwdUAwIHsKPiA+ID4+ICAg
ICAgICAgICAgICAgICAgICBjbG9jay1mcmVxdWVuY3kgPSA8MTFlMWEzMDA+Owo+ID4gPj4gICAg
ICAgICAgICAgICAgICAgIGNvbXBhdGlibGUgPSAiUG93ZXJQQyw0MDUiLCAiaWJtLHBwYzQwNSI7
Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgZC1jYWNoZS1saW5lLXNpemUgPSA8MjA+Owo+ID4g
Pj4gICAgICAgICAgICAgICAgICAgIGQtY2FjaGUtc2l6ZSA9IDw0MDAwPjsKPiA+ID4+ICAgICAg
ICAgICAgICAgICAgICBkZXZpY2VfdHlwZSA9ICJjcHUiOwo+ID4gPj4gICAgICAgICAgICAgICAg
ICAgIGktY2FjaGUtbGluZS1zaXplID0gPDIwPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICBp
LWNhY2hlLXNpemUgPSA8NDAwMD47Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgbW9kZWwgPSAi
UG93ZXJQQyw0MDUiOwo+ID4gPj4gICAgICAgICAgICAgICAgICAgIHJlZyA9IDwwPjsKPiA+ID4+
ICAgICAgICAgICAgICAgICAgICB0aW1lYmFzZS1mcmVxdWVuY3kgPSA8MTFlMWEzMDA+Owo+ID4g
Pj4gICAgICAgICAgICAgICAgICAgIHhsbngsYXB1LWNvbnRyb2wgPSA8ZGUwMD47Cj4gPiA+PiAg
ICAgICAgICAgICAgICAgICAgeGxueCxhcHUtdWRpLTEgPSA8YTE4OTgzPjsKPiA+ID4+ICAgICAg
ICAgICAgICAgICAgICB4bG54LGFwdS11ZGktMiA9IDxhMzg5ODM+Owo+ID4gPj4gICAgICAgICAg
ICAgICAgICAgIHhsbngsYXB1LXVkaS0zID0gPGE1ODljMz47Cj4gPiA+PiAgICAgICAgICAgICAg
ICAgICAgeGxueCxhcHUtdWRpLTQgPSA8YTc4OWMzPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAg
ICB4bG54LGFwdS11ZGktNSA9IDxhOThjMDM+Owo+ID4gPj4gICAgICAgICAgICAgICAgICAgIHhs
bngsYXB1LXVkaS02ID0gPGFiOGMwMz47Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgeGxueCxh
cHUtdWRpLTcgPSA8YWQ4YzQzPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICB4bG54LGFwdS11
ZGktOCA9IDxhZjhjNDM+Owo+ID4gPj4gICAgICAgICAgICAgICAgICAgIHhsbngsZGV0ZXJtaW5p
c3RpYy1tdWx0ID0gPDA+Owo+ID4gPj4gICAgICAgICAgICAgICAgICAgIHhsbngsZGlzYWJsZS1v
cGVyYW5kLWZvcndhcmRpbmcgPSA8MT47Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgeGxueCxm
YXN0ZXN0LXBsYi1jbG9jayA9ICJEUExCMCI7Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgeGxu
eCxnZW5lcmF0ZS1wbGItdGltZXNwZWNzID0gPDE+Owo+ID4gPj4gICAgICAgICAgICAgICAgICAg
IHhsbngsbW11LWVuYWJsZSA9IDwxPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICB4bG54LHB2
ci1oaWdoID0gPDA+Owo+ID4gPj4gICAgICAgICAgICAgICAgICAgIHhsbngscHZyLWxvdyA9IDww
PjsKPiA+ID4+ICAgICAgICAgICAgfSA7Cj4gPiA+PiAgICB9IDsKPiA+ID4+ICAgIHBsYjogcGxi
QDAgewo+ID4gPj4gICAgICAgICAgICAjYWRkcmVzcy1jZWxscyA9IDwxPjsKPiA+ID4+ICAgICAg
ICAgICAgI3NpemUtY2VsbHMgPSA8MT47Cj4gPiA+PiAgICAgICAgICAgIGNvbXBhdGlibGUgPSAi
eGxueCxwbGItdjQ2LTEuMDIuYSI7Cj4gPiA+PiAgICAgICAgICAgIHJhbmdlcyA7Cj4gPiA+PiAg
ICAgICAgICAgIElJQ19FRVBST006IGkyY0A4MTYwMDAwMCB7Cj4gPiA+PiAgICAgICAgICAgICAg
ICAgICAgY29tcGF0aWJsZSA9ICJ4bG54LHhwcy1paWMtMi4wMC5hIjsKPiA+ID4+ICAgICAgICAg
ICAgICAgICAgICBpbnRlcnJ1cHQtcGFyZW50ID0gPCZ4cHNfaW50Y18wPjsKPiA+ID4+ICAgICAg
ICAgICAgICAgICAgICBpbnRlcnJ1cHRzID0gPCA0IDIgPjsKPiA+ID4+ICAgICAgICAgICAgICAg
ICAgICByZWcgPSA8IDgxNjAwMDAwIDEwMDAwID47Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAg
eGxueCxjbGstZnJlcSA9IDw1ZjVlMTAwPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICB4bG54
LGZhbWlseSA9ICJ2aXJ0ZXg0IjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICB4bG54LGdwby13
aWR0aCA9IDwxPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICB4bG54LGlpYy1mcmVxID0gPDE4
NmEwPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICB4bG54LHNjbC1pbmVydGlhbC1kZWxheSA9
IDwwPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICB4bG54LHNkYS1pbmVydGlhbC1kZWxheSA9
IDwwPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICB4bG54LHRlbi1iaXQtYWRyID0gPDA+Owo+
ID4gPj4gICAgICAgICAgICB9IDsKPiA+ID4+ICAgICAgICAgICAgTEVEc180Qml0OiBncGlvQDgx
NDAwMDAwIHsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICBjb21wYXRpYmxlID0gInhsbngseHBz
LWdwaW8tMS4wMC5hIjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICBpbnRlcnJ1cHQtcGFyZW50
ID0gPCZ4cHNfaW50Y18wPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICBpbnRlcnJ1cHRzID0g
PCA1IDIgPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICByZWcgPSA8IDgxNDAwMDAwIDEwMDAw
ID47Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgeGxueCxhbGwtaW5wdXRzID0gPDA+Owo+ID4g
Pj4gICAgICAgICAgICAgICAgICAgIHhsbngsYWxsLWlucHV0cy0yID0gPDA+Owo+ID4gPj4gICAg
ICAgICAgICAgICAgICAgIHhsbngsZG91dC1kZWZhdWx0ID0gPDA+Owo+ID4gPj4gICAgICAgICAg
ICAgICAgICAgIHhsbngsZG91dC1kZWZhdWx0LTIgPSA8MD47Cj4gPiA+PiAgICAgICAgICAgICAg
ICAgICAgeGxueCxmYW1pbHkgPSAidmlydGV4NCI7Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAg
eGxueCxncGlvLXdpZHRoID0gPDQ+Owo+ID4gPj4gICAgICAgICAgICAgICAgICAgIHhsbngsaW50
ZXJydXB0LXByZXNlbnQgPSA8MT47Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgeGxueCxpcy1i
aWRpciA9IDwxPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICB4bG54LGlzLWJpZGlyLTIgPSA8
MT47Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgeGxueCxpcy1kdWFsID0gPDA+Owo+ID4gPj4g
ICAgICAgICAgICAgICAgICAgIHhsbngsdHJpLWRlZmF1bHQgPSA8ZmZmZmZmZmY+Owo+ID4gPj4g
ICAgICAgICAgICAgICAgICAgIHhsbngsdHJpLWRlZmF1bHQtMiA9IDxmZmZmZmZmZj47Cj4gPiA+
PiAgICAgICAgICAgIH0gOwo+ID4gPj4gICAgICAgICAgICBSUzIzMl9VYXJ0OiBzZXJpYWxAODNl
MDAwMDAgewo+ID4gPj4gICAgICAgICAgICAgICAgICAgIGNvbXBhdGlibGUgPSAieGxueCx4cHMt
dWFydDE2NTUwLTIuMDAuYSI7Cj4gPiA+PiAvLyAgICAgICAgICAgICAgICAgY29tcGF0aWJsZSA9
ICJuczE2NTUwIjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICBkZXZpY2VfdHlwZSA9ICJzZXJp
YWwiOwo+ID4gPj4gICAgICAgICAgICAgICAgICAgIGludGVycnVwdC1wYXJlbnQgPSA8Jnhwc19p
bnRjXzA+Owo+ID4gPj4gICAgICAgICAgICAgICAgICAgIGludGVycnVwdHMgPSA8IDYgMiA+Owo+
ID4gPj4gICAgICAgICAgICAgICAgICAgIHJlZyA9IDwgODNlMDAwMDAgMTAwMDAgPjsKPiA+ID4+
ICAgICAgICAgICAgICAgICAgICBjdXJyZW50LXNwZWVkID0gPGQjOTYwMD47Cj4gPiA+PiAgICAg
ICAgICAgICAgICAgICAgY2xvY2stZnJlcXVlbmN5ID0gPGQjMTAwMDAwMDAwPjsgIC8qIGFkZGVk
Cj4gPiBieSBqaGwgKi8KPiA+ID4+ICAgICAgICAgICAgICAgICAgICByZWctc2hpZnQgPSA8Mj47
Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgeGxueCxmYW1pbHkgPSAidmlydGV4NCI7Cj4gPiA+
PiAgICAgICAgICAgICAgICAgICAgeGxueCxoYXMtZXh0ZXJuYWwtcmNsayA9IDwwPjsKPiA+ID4+
ICAgICAgICAgICAgICAgICAgICB4bG54LGhhcy1leHRlcm5hbC14aW4gPSA8MD47Cj4gPiA+PiAg
ICAgICAgICAgICAgICAgICAgeGxueCxpcy1hLTE2NTUwID0gPDE+Owo+ID4gPj4gICAgICAgICAg
ICB9IDsKPiA+ID4+ICAgICAgICAgICAgU3lzQUNFX0NvbXBhY3RGbGFzaDogc3lzYWNlQDgzNjAw
MDAwIHsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICBjb21wYXRpYmxlID0gInhsbngseHBzLXN5
c2FjZS0xLjAwLmEiOwo+ID4gPj4gICAgICAgICAgICAgICAgICAgIGludGVycnVwdC1wYXJlbnQg
PSA8Jnhwc19pbnRjXzA+Owo+ID4gPj4gICAgICAgICAgICAgICAgICAgIGludGVycnVwdHMgPSA8
IDMgMiA+Owo+ID4gPj4gICAgICAgICAgICAgICAgICAgIHJlZyA9IDwgODM2MDAwMDAgMTAwMDAg
PjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICB4bG54LGZhbWlseSA9ICJ2aXJ0ZXg0IjsKPiA+
ID4+ICAgICAgICAgICAgICAgICAgICB4bG54LG1lbS13aWR0aCA9IDwxMD47Cj4gPiA+PiAgICAg
ICAgICAgIH0gOwo+ID4gPj4gICAgICAgICAgICBUcmlNb2RlX01BQ19HTUlJOiB4cHMtbGwtdGVt
YWNAODFjMDAwMDAgewo+ID4gPj4gICAgICAgICAgICAgICAgICAgICNhZGRyZXNzLWNlbGxzID0g
PDE+Owo+ID4gPj4gICAgICAgICAgICAgICAgICAgICNzaXplLWNlbGxzID0gPDE+Owo+ID4gPj4g
ICAgICAgICAgICAgICAgICAgIGNvbXBhdGlibGUgPSAieGxueCxjb21wb3VuZCI7Cj4gPiA+PiAg
ICAgICAgICAgICAgICAgICAgZXRoZXJuZXRAODFjMDAwMDAgewo+ID4gPj4gICAgICAgICAgICAg
ICAgICAgICAgICAgICAgY29tcGF0aWJsZSA9ICJ4bG54LHhwcy1sbC10ZW1hYy0KPiA+IDEuMDEu
YSI7Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgICAgICAgICBkZXZpY2VfdHlwZSA9ICJuZXR3
b3JrIjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICAgICAgICAgIGludGVycnVwdC1wYXJlbnQg
PQo+ID4gPCZ4cHNfaW50Y18wPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICAgICAgICAgIGlu
dGVycnVwdHMgPSA8IDIgMiA+Owo+ID4gPj4gICAgICAgICAgICAgICAgICAgICAgICAgICAgbGxp
bmstY29ubmVjdGVkID0gPCZQSU0yPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICAgICAgICAg
IGxvY2FsLW1hYy1hZGRyZXNzID0gWyAwMiAwMCAwMAo+ID4gMDAgMDAgMDEgXTsKPiA+ID4+ICAg
ICAgICAgICAgICAgICAgICAgICAgICAgIHJlZyA9IDwgODFjMDAwMDAgNDAgPjsKPiA+ID4+ICAg
ICAgICAgICAgICAgICAgICAgICAgICAgIHhsbngsYnVzMmNvcmUtY2xrLXJhdGlvID0gPDE+Owo+
ID4gPj4gICAgICAgICAgICAgICAgICAgICAgICAgICAgeGxueCxwaHktdHlwZSA9IDwxPjsKPiA+
ID4+ICAgICAgICAgICAgICAgICAgICAgICAgICAgIHhsbngscGh5YWRkciA9IDwxPjsKPiA+ID4+
ICAgICAgICAgICAgICAgICAgICAgICAgICAgIHhsbngscnhjc3VtID0gPDA+Owo+ID4gPj4gICAg
ICAgICAgICAgICAgICAgICAgICAgICAgeGxueCxyeGZpZm8gPSA8MTAwMD47Cj4gPiA+PiAgICAg
ICAgICAgICAgICAgICAgICAgICAgICB4bG54LHRlbWFjLXR5cGUgPSA8MT47Cj4gPiA+PiAgICAg
ICAgICAgICAgICAgICAgICAgICAgICB4bG54LHR4Y3N1bSA9IDwwPjsKPiA+ID4+ICAgICAgICAg
ICAgICAgICAgICAgICAgICAgIHhsbngsdHhmaWZvID0gPDEwMDA+Owo+ID4gPj4gICAgICAgICAg
ICAgICAgICAgIH0gOwo+ID4gPj4gICAgICAgICAgICB9IDsKPiA+ID4+ICAgICAgICAgICAgbXBt
Y0AwIHsKPiA+ID4+ICAgICAgICAgICAgICAgICAgICAjYWRkcmVzcy1jZWxscyA9IDwxPjsKPiA+
ID4+ICAgICAgICAgICAgICAgICAgICAjc2l6ZS1jZWxscyA9IDwxPjsKPiA+ID4+ICAgICAgICAg
ICAgICAgICAgICBjb21wYXRpYmxlID0gInhsbngsbXBtYy00LjAwLmEiOwo+ID4gPj4gICAgICAg
ICAgICAgICAgICAgIFBJTTI6IHNkbWFAODQ2MDAxMDAgewo+ID4gPj4gICAgICAgICAgICAgICAg
ICAgICAgICAgICAgY29tcGF0aWJsZSA9ICJ4bG54LGxsLWRtYS0KPiA+IDEuMDAuYSI7Cj4gPiA+
PiAgICAgICAgICAgICAgICAgICAgICAgICAgICBpbnRlcnJ1cHQtcGFyZW50ID0KPiA+IDwmeHBz
X2ludGNfMD47Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgICAgICAgICBpbnRlcnJ1cHRzID0g
PCAxIDIgMCAyID47Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgICAgICAgICByZWcgPSA8IDg0
NjAwMTAwIDgwID47Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgfSA7Cj4gPiA+PiAgICAgICAg
ICAgIH0gOwo+ID4gPj4gICAgICAgICAgICB4cHNfYnJhbV9pZl9jbnRscl8xOiB4cHMtYnJhbS1p
Zi1jbnRsckBmZmZmZTAwMCB7Cj4gPiA+PiAgICAgICAgICAgICAgICAgICAgY29tcGF0aWJsZSA9
ICJ4bG54LHhwcy1icmFtLWlmLWNudGxyLQo+ID4gMS4wMC5hIjsKPiA+ID4+ICAgICAgICAgICAg
ICAgICAgICByZWcgPSA8IGZmZmZlMDAwIDIwMDAgPjsKPiA+ID4+ICAgICAgICAgICAgICAgICAg
ICB4bG54LGZhbWlseSA9ICJ2aXJ0ZXg0IjsKPiA+ID4+ICAgICAgICAgICAgfSA7Cj4gPiA+PiAg
ICAgICAgICAgIHhwc19pbnRjXzA6IGludGVycnVwdC1jb250cm9sbGVyQDgxODAwMDAwIHsKPiA+
ID4+ICAgICAgICAgICAgICAgICAgICAjaW50ZXJydXB0LWNlbGxzID0gPDI+Owo+ID4gPj4gICAg
ICAgICAgICAgICAgICAgIGNvbXBhdGlibGUgPSAieGxueCx4cHMtaW50Yy0xLjAwLmEiOwo+ID4g
Pj4gICAgICAgICAgICAgICAgICAgIGludGVycnVwdC1jb250cm9sbGVyIDsKPiA+ID4+ICAgICAg
ICAgICAgICAgICAgICByZWcgPSA8IDgxODAwMDAwIDEwMDAwID47Cj4gPiA+PiAgICAgICAgICAg
ICAgICAgICAgeGxueCxudW0taW50ci1pbnB1dHMgPSA8Nz47Cj4gPiA+PiAgICAgICAgICAgIH0g
Owo+ID4gPj4gICAgfSA7Cj4gPiA+PiAgICBwcGM0MDVfMF9kcGxiMTogcGxiQDEgewo+ID4gPj4g
ICAgICAgICAgICAjYWRkcmVzcy1jZWxscyA9IDwxPjsKPiA+ID4+ICAgICAgICAgICAgI3NpemUt
Y2VsbHMgPSA8MT47Cj4gPiA+PiAgICAgICAgICAgIGNvbXBhdGlibGUgPSAieGxueCxwbGItdjQ2
LTEuMDIuYSI7Cj4gPiA+PiAgICAgICAgICAgIHJhbmdlcyA7Cj4gPiA+PiAgICB9IDsKPiA+ID4+
IH0gIDsKPiA+ID4+Cj4gPiA+Pgo+ID4gPj4KPiA+ID4+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0t
LS0tCj4gPiA+PiBGcm9tOiBNYWdudXMgSGpvcnRoIFttYWlsdG86bWhAb21uaXN5cy5zZV0KPiA+
ID4+IFNlbnQ6IFNhdHVyZGF5LCBNYXJjaCAyOSwgMjAwOCA2OjU0IEFNCj4gPiA+PiBUbzogZ2l0
Cj4gPiA+PiBDYzogbGludXhwcGMtZW1iZWRkZWRAb3psYWJzLm9yZwo+ID4gPj4gU3ViamVjdDog
WGlsaW54IExMVEVNQUMgZHJpdmVyIGlzc3Vlcwo+ID4gPj4KPiA+ID4+IEhpLAo+ID4gPj4KPiA+
ID4+IEknbSBoYXZpbmcgc29tZSBuZXR3b3JraW5nIHRyb3VibGVzIHdpdGggdGhlIFhpbGlueCBM
TFRFTUFDIGRyaXZlciBmcm9tCj4gdGhlCj4gPiA+PiBYaWxpbnggTGludXggZ2l0IHRyZWUgKHBv
d2VycGMgYXJjaCkgb24gYW4gTUw0MDMgYm9hcmQuIEVESzkuMlNQMiwKPiA+ID4+IHhwc19sbF90
ZW1hYyB2MS4wMC5iCj4gPiA+Pgo+ID4gPj4gVGhlIHdlaXJkIHRoaW5nIGlzLCB0aGF0IGl0IHNv
cnQgb2YgaGFsZiB3b3Jrcy4gSXQgc3VjY2Vzc2Z1bGx5IG1ha2VzIGEKPiBESENQCj4gPiA+PiBy
ZXF1ZXN0IGFuZCBnZXRzIGl0cyBJUCBhZGRyZXNzLiBJIHRyaWVkIHNldHRpbmcgdXAgYSB0ZnRw
ZCBzZXJ2ZXIsIGFuZAo+IEkgY2FuCj4gPiA+PiBzZWUgVURQIHJlcXVlc3RzIGNvbWluZyBpbiBi
dXQgdGhlIHJlc3BvbnNlIGRvZXNuJ3Qgc2VlbSB0byBjb21lIG91dC4gSQo+IGFsc28KPiA+ID4+
IHRyaWVkIHJ1bm5pbmcgYSBUQ1Agc2VydmVyIG9uIHRoZSBib2FyZCwgYW5kIGl0IGNhbiBzZWUg
YW5kIGFjY2VwdAo+IGluY29taW5nCj4gPiA+PiBjb25uZWN0aW9ucyBidXQgYWZ0ZXIgdGhhdCBu
byBkYXRhIHNlZW1zIHRvIGdldCB0aHJvdWdoLiBJIGNhbiBwaW5nIG91dAo+IGFuZAo+ID4gPj4g
Z2V0IGFyb3VuZCA0MCUgcGFja2V0IGxvc3MuCj4gPiA+Pgo+ID4gPj4gTG9va2luZyBhdCAvcHJv
Yy9pbnRlcnJ1cHRzLCBJIGNhbiBzZWUgYm90aCBUeERtYSBpbnRlcnJ1cHRzIGFuZCBSeERtYQo+
ID4gPj4gaW50ZXJydXB0cy4gTm8gZXRoMCBpbnRlcnJ1cHRzIGJ1dCB0aGF0IHNlZW1zIHRvIGJl
IE9LIGp1ZGdpbmcgYnkgdGhlCj4gZHJpdmVyCj4gPiA+PiBzb3VyY2UgY29tbWVudHMuIElmY29u
ZmlnIHNob3dzIG5vIGNvbGxpc3Rpb25zLCBubyBkcm9wcGVkIHBhY2tldHMsIG5vCj4gPiBlcnJv
cnMsCj4gPiA+PiBzbyB0aGUgc3lzdGVtIHNlZW1zIHRvIHRoaW5rIHRoYXQgZXZlcnl0aGluZyBp
cyBPSy4KPiA+ID4+Cj4gPiA+PiBDbHVlcyBhbnlvbmU/IEknbSBzdGFydGluZyB0byBydW4gb3V0
IG9mIGlkZWFzLi4uCj4gPiA+Pgo+ID4gPj4gQmVzdCByZWdhcmRzLAo+ID4gPj4gTWFnbnVzCj4g
PiA+Pgo+ID4gPj4KPiA+ID4+IC0tCj4gPiA+Pgo+ID4gPj4gTWFnbnVzIEhqb3J0aCwgTS5TYy4K
PiA+ID4+IE9tbmlzeXMgSW5zdHJ1bWVudHMgQUIKPiA+ID4+IEdydXZnYXRhbiA4Cj4gPiA+PiBT
RS00MjEgMzAgIFbDpHN0cmEgRnLDtmx1bmRhLCBTV0VERU4KPiA+ID4+IFBob25lOiArNDYgMzEg
NzM0IDM0IDA5Cj4gPiA+PiBGYXg6ICs0NiAzMSA3MzQgMzQgMjkKPiA+ID4+IGh0dHA6Ly93d3cu
b21uaXN5cy5zZQo+ID4gPj4KPiA+ID4KPiA+ID4gX19fX19fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX18KPiA+ID4gTGludXhwcGMtZW1iZWRkZWQgbWFpbGluZyBsaXN0
Cj4gPiA+IExpbnV4cHBjLWVtYmVkZGVkQG96bGFicy5vcmcKPiA+ID4gaHR0cHM6Ly9vemxhYnMu
b3JnL21haWxtYW4vbGlzdGluZm8vbGludXhwcGMtZW1iZWRkZWQKPiBfX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwo+IExpbnV4cHBjLWVtYmVkZGVkIG1haWxp
bmcgbGlzdAo+IExpbnV4cHBjLWVtYmVkZGVkQG96bGFicy5vcmcKPiBodHRwczovL296bGFicy5v
cmcvbWFpbG1hbi9saXN0aW5mby9saW51eHBwYy1lbWJlZGRlZAo+Cj4KPiAtLQo+IEpvaGFubiBC
YXVkeQo+IGpvaGFhaG5AZ21haWwuY29tCj4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f
X18KPiDnlKggV2luZG93cyBMaXZlIFNwYWNlcyDlsZXnpLrkuKrmgKfoh6rmiJHvvIzkuI7lpb3l
j4vliIbkuqvnlJ/mtLvvvIEg5LqG6Kej5pu05aSa5L+h5oGv77yBCgoKCi0tIApKb2hhbm4gQmF1
ZHkKam9oYWFobkBnbWFpbC5jb20K

RE: Xilinx LLTEMAC driver issues

[MingLiu]

[-- Attachment #1: Type: text/plain, Size: 30378 bytes --]


Dear Johann,
Thanks for the prompt reply. 
 
Actually I am using EDK 10.1 evaluation version. According to Xilinx's answer, they said the problem will be fixed in 10.1 already. Unfortunately I still met it in my design. 
 
Do you happen to still have the file tx_ii_if.zip? I cannot download it from Xilinx any more. Thank you so much if you can give me a copy.
 
BR
Ming
 
> Date: Fri, 4 Apr 2008 09:53:07 +0000> From: johaahn@gmail.com> To: eemingliu@hotmail.com> Subject: Re: Xilinx LLTEMAC driver issues> CC: mh@omnisys.se; linuxppc-embedded@ozlabs.org; john.linn@xilinx.com; git@xilinx.com> > Hi Ming,> > I've already used netperf (without NFS) successfully.> Are you using 1.00.b and 9.2, if yes look at AR #29708.> > Best regards,> Johann> > On Fri, Apr 4, 2008 at 9:36 AM, MingLiu <eemingliu@hotmail.com> wrote:> >> > Dear Johann,> > Previously I said this patch helps for the checksum error problem. But now> > I found some new issues. Yes. at least with this patch, something is better> > and at least we can use the hardware checksum offloading to do something,> > for example I can mount the NFS root file system. However when I try to> > measure the ethernet bandwidth with netperf, something goes wrong and the> > NFS mount will be broken. I guess this is because of the large bulk data> > transfer and maybe thus it triggers the checksum problem to happen.> >> > Do you have the same situation? Or someone else has the same problem? I> > will appreciate if you can share your experience. Thanks a lot.> >> > BR> > Ming> >> >> >> > ________________________________> > Date: Wed, 2 Apr 2008 07:20:43 +0000> > From: johaahn@gmail.com> > To: mh@omnisys.se> >> > Subject: Re: Xilinx LLTEMAC driver issues> > CC: linuxppc-embedded@ozlabs.org; John.Linn@xilinx.com; git@xilinx.com> >> >> >> > I've solved this checksum offloading issue with this below patch.> > It may help, if you need performance. It certainly needs review but it works> > on my side.> >> > --- xilinxgit/drivers/net/xilinx> > _lltemac/xlltemac_main.c.orig 2008-03-21 09:11:43.000000000 +0100> > +++ xilinxgit/drivers/net/xilinx_lltemac/xlltemac_main.c 2008-03-21> > 09:24:23.000000000 +0100> > @@ -133,7 +133,7 @@> > (XLlDma_mBdRead((BdPtr), XLLDMA_BD_STSCTRL_USR0_OFFSET)) &> > 0xFFFFFFFE )> >> > #define BdCsumSetup(BdPtr, Start, Insert) \> > - XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, (Start) << 16 |> > (Insert))> > + XLlDma_mBdWrite((BdPtr), XLLDMA_BD_USR1_OFFSET, ((Start) << 16) |> > (Insert))> >> > /* Used for debugging */> > #define BdCsumInsert(BdPtr) \> > @@ -1540,7 +1541,7 @@ static int xenet_DmaSend_internal(struct> > /*> > * if tx checksum offloading is enabled, when the ethernet stack> > * wants us to perform the checksum in hardware,> > - * skb->ip_summed is CHECKSUM_COMPLETE. Otherwise skb->ip_summed is> > + * skb->ip_summed is CHECKSUM_PARTIAL. Otherwise skb->ip_summed is> > * CHECKSUM_NONE, meaning the checksum is already done, or> > * CHECKSUM_UNNECESSARY, meaning checksumming is turned off (e.g.> > * loopback interface)> > @@ -1565,9 +1566,11 @@ static int xenet_DmaSend_internal(struct> > * skb_transport_header(skb) points to the beginning of the ip header> > *> > */> > - if (skb->ip_summed == CHECKSUM_COMPLETE) {> > + if (skb->ip_summed == CHECKSUM_PARTIAL) {> > +> > + unsigned int csum_start_off = skb_transport_offset(skb);> > + unsigned int csum_index_off = csum_start_off + skb->csum_offset;> >> > - unsigned char *raw = skb_transport_header(skb);> > #if 0> > {> > unsigned int csum = _xenet_tx_csum(skb);> > @@ -1578,9 +1581,8 @@ static int xenet_DmaSend_internal(struct> > }> > #else> > BdCsumEnable(bd_ptr);> > - BdCsumSetup(bd_ptr, raw - skb->data,> > - (raw - skb->data) + skb->csum);> > -> > + BdCsumSetup(bd_ptr, csum_start_off,> > + csum_index_off);> > #endif> > lp->tx_hw_csums++;> > }> > @@ -3277,7 +3279,7 @@ static int __devinit xtenet_of_probe(str> > struct resource *r_irq = &r_irq_struct; /* Interrupt resources */> > struct resource *r_mem = &r_mem_struct; /* IO mem resources */> > struct xlltemac_platform_data *pdata = &pdata_struct;> > - void *mac_address;> > + const void *mac_address;> > int rc = 0;> > const phandle *llink_connected_handle;> > struct device_node *llink_connected_node;> >> >> > On Mon, Mar 31, 2008 at 11:10 AM, Magnus Hjorth <mh@omnisys.se> wrote:> >> > Deactivating checksum offloading helped a lot! I still have some packet loss> > and not the best performance (TFTP transfer about 100 kbyte/s) but at least> > it works.> >> > Thanks!> >> > //Magnus> >> >> >> >> > > -----Original Message-----> > > From: rza1 [mailto:rza1@so-logic.net]> > > Sent: den 31 mars 2008 11:14> > > To: Magnus Hjorth> > > Cc: John Linn; git; linuxppc-embedded@ozlabs.org> > > Subject: Re: Xilinx LLTEMAC driver issues> > >> > > Hi Magnus,> > >> > > 1.> > > I am using nearly the same versions then you and got the same problems> > > too ;-).> > > I think there are some problems with the checksum offloading.> > > Try to sniff the some packages (e.g. wireshark)...> > > For me ICMP (ping) worked but udp and tcp not (because off a wrong> > > checksum in the transport layer).> > > A quick solution is to just deactivate checksum offloading.> > >> > > 2.> > > I remember some problems with Virtex-4 presamples too.> > > There where problems with the hard-temac wrapper. You had to use 1.00.a> > > and not b version.> > > But I don't have these problems with the EDK 9.2sp2/ISE9.2sp3 anymore.> > >> > > all the best,> > > Robert> > >> > > Magnus Hjorth wrote:> > > > Hi John,> > > >> > > > Thanks for the very fast reply! Right now I'm not at work so I don't> > > > have the board or EDK here to test anything.> > > >> > > > I'm using checksum offload, but I don't know if DRE is enabled or not. I> > > > can't recall seeing any setting to enable/disable DRE..> > > >> > > > A few things that crossed my mind:> > > >> > > > Last year I did a design with EDK 8.2, back then there was an issue with> > > > the ML403 boards having an old revision of the FPGA which wasn't> > > > compatible with some versions of the IP core. There are no such version> > > > issues with the xps_ll_temac?> > > >> > > > I don't think that I had phy-addr set in the DTS file. Will test that on> > > > Monday.> > > >> > > > Best regards,> > > > Magnus> > > >> > > >> > > > On Sat, 2008-03-29 at 07:58 -0600, John Linn wrote:> > > >> > > >> Hi Magnus,> > > >>> > > >> Sorry to hear you're having problems with it.> > > >>> > > >> I am doing testing on an ML405 which is the same board but with a> > bigger> > > FPGA, but with ppc arch and I don't see this issue. I have done limited> > testing> > > with powerpc arch and the LL TEMAC, but I didn't see this issue there> > either.> > > Powerpc arch is definitely less mature in my experience than the ppc arch.> > I'll> > > do a quick test with my powerpc arch and make sure again I'm not seeing> > it.> > > >>> > > >> My kernel is from the Xilinx Git tree, but there have been a number of> > > changes we have pushed out so I don't know how long ago you pulled from> > the Git> > > tree.> > > >>> > > >> My EDK project is 10.1 so it's a little newer. I am using LL TEMAC> > 1.01a so> > > it's a little newer. I reviewed the change log for the LL TEMAC and don't> > see> > > any big problems that were fixed in the newer versions, more new features.> > I'll> > > check with some others here to see if I missed something there.> > > >>> > > >> I am using DMA also, but no DRE or checksum offload. You didn't say> > anything> > > about those. I'm going to insert my mhs file that describes my system to> > let you> > > compare your system configuration. It's not clear to me yet if you have a> > h/w or> > > s/w problem.> > > >>> > > >> I'll also insert some of my device tree with the LL TEMAC so you can> > compare> > > (ignore 16550 stuff as we are still working on that).> > > >>> > > >> Since you can't ping reliably I would probably focus on that since it's> > > simpler than the other issues you're seeing.> > > >>> > > >> Thanks,> > > >> John> > > >>> > > >>> > > >>> > > >> #> > >> > ##############################################################################> > > >> # Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build> > > EDK_K_SP1.1> > > >> # Thu Feb 14 14:11:12 2008> > > >> # Target Board: Xilinx Virtex 4 ML405 Evaluation Platform Rev 1> > > >> # Family: virtex4> > > >> # Device: xc4vfx20> > > >> # Package: ff672> > > >> # Speed Grade: -10> > > >> # Processor: ppc405_0> > > >> # Processor clock frequency: 300.00 MHz> > > >> # Bus clock frequency: 100.00 MHz> > > >> # On Chip Memory : 8 KB> > > >> # Total Off Chip Memory : 128 MB> > > >> # - DDR_SDRAM = 128 MB> > > >> #> > >> > ##############################################################################> > > >> PARAMETER VERSION = 2.1.0> > > >>> > > >>> > > >> PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I> > > >> PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O> > > >> PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR => > IO, VEC> > > = [0:3]> > > >> PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO> > > >> PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin => > > fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin => > > fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin => > > fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin => > > fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin => > > fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin => > > fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O> > > >> PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin => > > fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I> > > >> PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O> > > >> PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR> > = O> > > >> PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR => > O, VEC> > > = [12:0]> > > >> PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin => > fpga_0_DDR_SDRAM_DDR_BankAddr, DIR> > > = O, VEC = [1:0]> > > >> PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR> > = O> > > >> PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O> > > >> PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR => > O> > > >> PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR> > = O> > > >> PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR => > O> > > >> PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O,> > VEC => > > [3:0]> > > >> PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO,> > VEC => > > [3:0]> > > >> PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC> > => > > [31:0]> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin => > > fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR = O, VEC = [7:0]> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin => > > fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR = O> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin => > > fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR = O> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin => > > fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR = O> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin => > > fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR = I, VEC = [7:0]> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin => > > fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR = I> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin => > > fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR = I> > > >> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin => > > fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR = I> > > >> PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin => > > fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR = I> > > >> PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin => > fpga_0_TriMode_MAC_GMII_MDIO_0,> > > DIR = IO> > > >> PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin => > fpga_0_TriMode_MAC_GMII_MDC_0, DIR> > > = O> > > >> PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin => > > fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR = O> > > >> PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ => > 100000000> > > >> PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST> > > >>> > > >>> > > >> BEGIN ppc405_virtex4> > > >> PARAMETER INSTANCE = ppc405_0> > > >> PARAMETER HW_VER = 2.01.a> > > >> PARAMETER C_FASTEST_PLB_CLOCK = DPLB1> > > >> PARAMETER C_IDCR_BASEADDR = 0b0100000000> > > >> PARAMETER C_IDCR_HIGHADDR = 0b0111111111> > > >> BUS_INTERFACE JTAGPPC = jtagppc_0_0> > > >> BUS_INTERFACE IPLB0 = plb> > > >> BUS_INTERFACE DPLB0 = plb> > > >> BUS_INTERFACE IPLB1 = ppc405_0_iplb1> > > >> BUS_INTERFACE DPLB1 = ppc405_0_dplb1> > > >> BUS_INTERFACE RESETPPC = ppc_reset_bus> > > >> PORT CPMC405CLOCK = proc_clk_s> > > >> PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ> > > >> END> > > >>> > > >> BEGIN jtagppc_cntlr> > > >> PARAMETER INSTANCE = jtagppc_0> > > >> PARAMETER HW_VER = 2.01.a> > > >> BUS_INTERFACE JTAGPPC0 = jtagppc_0_0> > > >> END> > > >>> > > >> BEGIN plb_v46> > > >> PARAMETER INSTANCE = plb> > > >> PARAMETER C_DCR_INTFCE = 0> > > >> PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100> > > >> PARAMETER HW_VER = 1.02.a> > > >> PORT PLB_Clk = sys_clk_s> > > >> PORT SYS_Rst = sys_bus_reset> > > >> END> > > >>> > > >> BEGIN xps_bram_if_cntlr> > > >> PARAMETER INSTANCE = xps_bram_if_cntlr_1> > > >> PARAMETER HW_VER = 1.00.a> > > >> PARAMETER C_SPLB_NATIVE_DWIDTH = 64> > > >> PARAMETER C_BASEADDR = 0xffffe000> > > >> PARAMETER C_HIGHADDR = 0xffffffff> > > >> BUS_INTERFACE SPLB = plb> > > >> BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port> > > >> END> > > >>> > > >> BEGIN bram_block> > > >> PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram> > > >> PARAMETER HW_VER = 1.00.a> > > >> BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port> > > >> END> > > >>> > > >> BEGIN xps_uart16550> > > >> PARAMETER INSTANCE = RS232_Uart> > > >> PARAMETER HW_VER = 2.00.a> > > >> PARAMETER C_IS_A_16550 = 1> > > >> PARAMETER C_BASEADDR = 0x83e00000> > > >> PARAMETER C_HIGHADDR = 0x83e0ffff> > > >> BUS_INTERFACE SPLB = plb> > > >> PORT sin = fpga_0_RS232_Uart_sin> > > >> PORT sout = fpga_0_RS232_Uart_sout> > > >> PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt> > > >> END> > > >>> > > >> BEGIN xps_gpio> > > >> PARAMETER INSTANCE = LEDs_4Bit> > > >> PARAMETER HW_VER = 1.00.a> > > >> PARAMETER C_INTERRUPT_PRESENT = 1> > > >> PARAMETER C_GPIO_WIDTH = 4> > > >> PARAMETER C_IS_DUAL = 0> > > >> PARAMETER C_IS_BIDIR = 1> > > >> PARAMETER C_ALL_INPUTS = 0> > > >> PARAMETER C_BASEADDR = 0x81400000> > > >> PARAMETER C_HIGHADDR = 0x8140ffff> > > >> BUS_INTERFACE SPLB = plb> > > >> PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO> > > >> PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt> > > >> END> > > >>> > > >> BEGIN xps_iic> > > >> PARAMETER INSTANCE = IIC_EEPROM> > > >> PARAMETER HW_VER = 2.00.a> > > >> PARAMETER C_CLK_FREQ = 100000000> > > >> PARAMETER C_IIC_FREQ = 100000> > > >> PARAMETER C_TEN_BIT_ADR = 0> > > >> PARAMETER C_BASEADDR = 0x81600000> > > >> PARAMETER C_HIGHADDR = 0x8160ffff> > > >> BUS_INTERFACE SPLB = plb> > > >> PORT Scl = fpga_0_IIC_EEPROM_Scl> > > >> PORT Sda = fpga_0_IIC_EEPROM_Sda> > > >> PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt> > > >> END> > > >>> > > >> BEGIN xps_sysace> > > >> PARAMETER INSTANCE = SysACE_CompactFlash> > > >> PARAMETER HW_VER = 1.00.a> > > >> PARAMETER C_MEM_WIDTH = 16> > > >> PARAMETER C_BASEADDR = 0x83600000> > > >> PARAMETER C_HIGHADDR = 0x8360ffff> > > >> BUS_INTERFACE SPLB = plb> > > >> PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK> > > >> PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_split> > > >> PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD> > > >> PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN> > > >> PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN> > > >> PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN> > > >> PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ> > > >> PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ> > > >> END> > > >>> > > >> BEGIN mpmc> > > >> PARAMETER INSTANCE = DDR_SDRAM> > > >> PARAMETER HW_VER = 4.00.a> > > >> PARAMETER C_NUM_PORTS = 3> > > >> PARAMETER C_MEM_PARTNO = HYB25D512160BE-5> > > >> PARAMETER C_MEM_DATA_WIDTH = 32> > > >> PARAMETER C_MEM_DQS_WIDTH = 4> > > >> PARAMETER C_MEM_DM_WIDTH = 4> > > >> PARAMETER C_MEM_TYPE = DDR> > > >> PARAMETER C_NUM_IDELAYCTRL = 2> > > >> PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2> > > >> PARAMETER C_PIM0_BASETYPE = 2> > > >> PARAMETER C_PIM1_BASETYPE = 2> > > >> PARAMETER C_PIM2_BASETYPE = 3> > > >> PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000> > > >> PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 1> > > >> PARAMETER C_MPMC_BASEADDR = 0x00000000> > > >> PARAMETER C_MPMC_HIGHADDR = 0x07ffffff> > > >> PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000> > > >> PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460ffff> > > >> BUS_INTERFACE SPLB0 = ppc405_0_iplb1> > > >> BUS_INTERFACE SPLB1 = ppc405_0_dplb1> > > >> BUS_INTERFACE SDMA_LL2 = TriMode_MAC_GMII_LLINK0> > > >> BUS_INTERFACE SDMA_CTRL2 = plb> > > >> PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr> > > >> PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr> > > >> PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n> > > >> PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE> > > >> PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n> > > >> PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n> > > >> PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n> > > >> PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM> > > >> PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS> > > >> PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ> > > >> PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk> > > >> PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n> > > >> PORT MPMC_Clk0 = sys_clk_s> > > >> PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s> > > >> PORT SDMA2_Clk = sys_clk_s> > > >> PORT MPMC_Clk_200MHz = clk_200mhz_s> > > >> PORT MPMC_Rst = sys_periph_reset> > > >> PORT SDMA2_Rx_IntOut = DDR_SDRAM_SDMA2_Rx_IntOut> > > >> PORT SDMA2_Tx_IntOut = DDR_SDRAM_SDMA2_Tx_IntOut> > > >> END> > > >>> > > >> BEGIN xps_ll_temac> > > >> PARAMETER INSTANCE = TriMode_MAC_GMII> > > >> PARAMETER HW_VER = 1.01.a> > > >> PARAMETER C_SPLB_CLK_PERIOD_PS = 10000> > > >> PARAMETER C_PHY_TYPE = 1> > > >> PARAMETER C_NUM_IDELAYCTRL = 4> > > >> PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-> > > IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3> > > >> PARAMETER C_TEMAC_TYPE = 1> > > >> PARAMETER C_BUS2CORE_CLK_RATIO = 1> > > >> PARAMETER C_BASEADDR = 0x81c00000> > > >> PARAMETER C_HIGHADDR = 0x81c0ffff> > > >> BUS_INTERFACE SPLB = plb> > > >> BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_LLINK0> > > >> PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0> > > >> PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0> > > >> PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0> > > >> PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0> > > >> PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0> > > >> PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0> > > >> PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0> > > >> PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0> > > >> PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0> > > >> PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0> > > >> PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0> > > >> PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n> > > >> PORT GTX_CLK_0 = temac_clk_s> > > >> PORT REFCLK = clk_200mhz_s> > > >> PORT LlinkTemac0_CLK = sys_clk_s> > > >> PORT TemacIntc0_Irpt = TriMode_MAC_GMII_TemacIntc0_Irpt> > > >> END> > > >>> > > >> BEGIN util_bus_split> > > >> PARAMETER INSTANCE = SysACE_CompactFlash_util_bus_split_0> > > >> PARAMETER HW_VER = 1.00.a> > > >> PARAMETER C_SIZE_IN = 7> > > >> PARAMETER C_LEFT_POS = 0> > > >> PARAMETER C_SPLIT = 6> > > >> PORT Sig = fpga_0_SysACE_CompactFlash_SysACE_MPA_split> > > >> PORT Out1 = fpga_0_SysACE_CompactFlash_SysACE_MPA> > > >> END> > > >>> > > >> BEGIN plb_v46> > > >> PARAMETER INSTANCE = ppc405_0_iplb1> > > >> PARAMETER HW_VER = 1.02.a> > > >> PORT PLB_Clk = sys_clk_s> > > >> PORT SYS_Rst = sys_bus_reset> > > >> END> > > >>> > > >> BEGIN plb_v46> > > >> PARAMETER INSTANCE = ppc405_0_dplb1> > > >> PARAMETER HW_VER = 1.02.a> > > >> PORT PLB_Clk = sys_clk_s> > > >> PORT SYS_Rst = sys_bus_reset> > > >> END> > > >>> > > >> BEGIN clock_generator> > > >> PARAMETER INSTANCE = clock_generator_0> > > >> PARAMETER HW_VER = 2.00.a> > > >> PARAMETER C_EXT_RESET_HIGH = 1> > > >> PARAMETER C_CLKIN_FREQ = 100000000> > > >> PARAMETER C_CLKOUT0_FREQ = 100000000> > > >> PARAMETER C_CLKOUT0_BUF = TRUE> > > >> PARAMETER C_CLKOUT0_PHASE = 0> > > >> PARAMETER C_CLKOUT0_GROUP = DCM0> > > >> PARAMETER C_CLKOUT1_FREQ = 100000000> > > >> PARAMETER C_CLKOUT1_BUF = TRUE> > > >> PARAMETER C_CLKOUT1_PHASE = 90> > > >> PARAMETER C_CLKOUT1_GROUP = DCM0> > > >> PARAMETER C_CLKOUT2_FREQ = 300000000> > > >> PARAMETER C_CLKOUT2_BUF = TRUE> > > >> PARAMETER C_CLKOUT2_PHASE = 0> > > >> PARAMETER C_CLKOUT2_GROUP = DCM0> > > >> PARAMETER C_CLKOUT3_FREQ = 200000000> > > >> PARAMETER C_CLKOUT3_BUF = TRUE> > > >> PARAMETER C_CLKOUT3_PHASE = 0> > > >> PARAMETER C_CLKOUT3_GROUP = NONE> > > >> PARAMETER C_CLKOUT4_FREQ = 125000000> > > >> PARAMETER C_CLKOUT4_BUF = TRUE> > > >> PARAMETER C_CLKOUT4_PHASE = 0> > > >> PARAMETER C_CLKOUT4_GROUP = NONE> > > >> PORT CLKOUT0 = sys_clk_s> > > >> PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_90_s> > > >> PORT CLKOUT2 = proc_clk_s> > > >> PORT CLKOUT3 = clk_200mhz_s> > > >> PORT CLKOUT4 = temac_clk_s> > > >> PORT CLKIN = dcm_clk_s> > > >> PORT LOCKED = Dcm_all_locked> > > >> PORT RST = net_gnd> > > >> END> > > >>> > > >> BEGIN proc_sys_reset> > > >> PARAMETER INSTANCE = proc_sys_reset_0> > > >> PARAMETER HW_VER = 2.00.a> > > >> PARAMETER C_EXT_RESET_HIGH = 0> > > >> BUS_INTERFACE RESETPPC0 = ppc_reset_bus> > > >> PORT Slowest_sync_clk = sys_clk_s> > > >> PORT Dcm_locked = Dcm_all_locked> > > >> PORT Ext_Reset_In = sys_rst_s> > > >> PORT Bus_Struct_Reset = sys_bus_reset> > > >> PORT Peripheral_Reset = sys_periph_reset> > > >> END> > > >>> > > >> BEGIN xps_intc> > > >> PARAMETER INSTANCE = xps_intc_0> > > >> PARAMETER HW_VER = 1.00.a> > > >> PARAMETER C_BASEADDR = 0x81800000> > > >> PARAMETER C_HIGHADDR = 0x8180ffff> > > >> BUS_INTERFACE SPLB = plb> > > >> PORT Irq = EICC405EXTINPUTIRQ> > > >> PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt &> > > IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ &> > > TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut &> > > DDR_SDRAM_SDMA2_Tx_IntOut> > > >> END> > > >>> > > >>> > > >>> > > >> #address-cells = <1>;> > > >> #size-cells = <1>;> > > >> compatible = "xlnx,virtex";> > > >> model = "testing";> > > >> DDR_SDRAM: memory@0 {> > > >> device_type = "memory";> > > >> reg = < 0 8000000 >;> > > >> } ;> > > >> chosen {> > > >> bootargs = "console=ttyS0,9600 ip=on> > > nfsroot=172.16.40.76:/v2pclients/jhl26,tcp";> > > >> linux,stdout-path = "/plb@0/serial@83e00000";> > > >> } ;> > > >> cpus {> > > >> #address-cells = <1>;> > > >> #cpus = <1>;> > > >> #size-cells = <0>;> > > >> ppc405_0: cpu@0 {> > > >> clock-frequency = <11e1a300>;> > > >> compatible = "PowerPC,405", "ibm,ppc405";> > > >> d-cache-line-size = <20>;> > > >> d-cache-size = <4000>;> > > >> device_type = "cpu";> > > >> i-cache-line-size = <20>;> > > >> i-cache-size = <4000>;> > > >> model = "PowerPC,405";> > > >> reg = <0>;> > > >> timebase-frequency = <11e1a300>;> > > >> xlnx,apu-control = <de00>;> > > >> xlnx,apu-udi-1 = <a18983>;> > > >> xlnx,apu-udi-2 = <a38983>;> > > >> xlnx,apu-udi-3 = <a589c3>;> > > >> xlnx,apu-udi-4 = <a789c3>;> > > >> xlnx,apu-udi-5 = <a98c03>;> > > >> xlnx,apu-udi-6 = <ab8c03>;> > > >> xlnx,apu-udi-7 = <ad8c43>;> > > >> xlnx,apu-udi-8 = <af8c43>;> > > >> xlnx,deterministic-mult = <0>;> > > >> xlnx,disable-operand-forwarding = <1>;> > > >> xlnx,fastest-plb-clock = "DPLB0";> > > >> xlnx,generate-plb-timespecs = <1>;> > > >> xlnx,mmu-enable = <1>;> > > >> xlnx,pvr-high = <0>;> > > >> xlnx,pvr-low = <0>;> > > >> } ;> > > >> } ;> > > >> plb: plb@0 {> > > >> #address-cells = <1>;> > > >> #size-cells = <1>;> > > >> compatible = "xlnx,plb-v46-1.02.a";> > > >> ranges ;> > > >> IIC_EEPROM: i2c@81600000 {> > > >> compatible = "xlnx,xps-iic-2.00.a";> > > >> interrupt-parent = <&xps_intc_0>;> > > >> interrupts = < 4 2 >;> > > >> reg = < 81600000 10000 >;> > > >> xlnx,clk-freq = <5f5e100>;> > > >> xlnx,family = "virtex4";> > > >> xlnx,gpo-width = <1>;> > > >> xlnx,iic-freq = <186a0>;> > > >> xlnx,scl-inertial-delay = <0>;> > > >> xlnx,sda-inertial-delay = <0>;> > > >> xlnx,ten-bit-adr = <0>;> > > >> } ;> > > >> LEDs_4Bit: gpio@81400000 {> > > >> compatible = "xlnx,xps-gpio-1.00.a";> > > >> interrupt-parent = <&xps_intc_0>;> > > >> interrupts = < 5 2 >;> > > >> reg = < 81400000 10000 >;> > > >> xlnx,all-inputs = <0>;> > > >> xlnx,all-inputs-2 = <0>;> > > >> xlnx,dout-default = <0>;> > > >> xlnx,dout-default-2 = <0>;> > > >> xlnx,family = "virtex4";> > > >> xlnx,gpio-width = <4>;> > > >> xlnx,interrupt-present = <1>;> > > >> xlnx,is-bidir = <1>;> > > >> xlnx,is-bidir-2 = <1>;> > > >> xlnx,is-dual = <0>;> > > >> xlnx,tri-default = <ffffffff>;> > > >> xlnx,tri-default-2 = <ffffffff>;> > > >> } ;> > > >> RS232_Uart: serial@83e00000 {> > > >> compatible = "xlnx,xps-uart16550-2.00.a";> > > >> // compatible = "ns16550";> > > >> device_type = "serial";> > > >> interrupt-parent = <&xps_intc_0>;> > > >> interrupts = < 6 2 >;> > > >> reg = < 83e00000 10000 >;> > > >> current-speed = <d#9600>;> > > >> clock-frequency = <d#100000000>; /* added> > > by jhl */> > > >> reg-shift = <2>;> > > >> xlnx,family = "virtex4";> > > >> xlnx,has-external-rclk = <0>;> > > >> xlnx,has-external-xin = <0>;> > > >> xlnx,is-a-16550 = <1>;> > > >> } ;> > > >> SysACE_CompactFlash: sysace@83600000 {> > > >> compatible = "xlnx,xps-sysace-1.00.a";> > > >> interrupt-parent = <&xps_intc_0>;> > > >> interrupts = < 3 2 >;> > > >> reg = < 83600000 10000 >;> > > >> xlnx,family = "virtex4";> > > >> xlnx,mem-width = <10>;> > > >> } ;> > > >> TriMode_MAC_GMII: xps-ll-temac@81c00000 {> > > >> #address-cells = <1>;> > > >> #size-cells = <1>;> > > >> compatible = "xlnx,compound";> > > >> ethernet@81c00000 {> > > >> compatible = "xlnx,xps-ll-temac-> > > 1.01.a";> > > >> device_type = "network";> > > >> interrupt-parent => > > <&xps_intc_0>;> > > >> interrupts = < 2 2 >;> > > >> llink-connected = <&PIM2>;> > > >> local-mac-address = [ 02 00 00> > > 00 00 01 ];> > > >> reg = < 81c00000 40 >;> > > >> xlnx,bus2core-clk-ratio = <1>;> > > >> xlnx,phy-type = <1>;> > > >> xlnx,phyaddr = <1>;> > > >> xlnx,rxcsum = <0>;> > > >> xlnx,rxfifo = <1000>;> > > >> xlnx,temac-type = <1>;> > > >> xlnx,txcsum = <0>;> > > >> xlnx,txfifo = <1000>;> > > >> } ;> > > >> } ;> > > >> mpmc@0 {> > > >> #address-cells = <1>;> > > >> #size-cells = <1>;> > > >> compatible = "xlnx,mpmc-4.00.a";> > > >> PIM2: sdma@84600100 {> > > >> compatible = "xlnx,ll-dma-> > > 1.00.a";> > > >> interrupt-parent => > > <&xps_intc_0>;> > > >> interrupts = < 1 2 0 2 >;> > > >> reg = < 84600100 80 >;> > > >> } ;> > > >> } ;> > > >> xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {> > > >> compatible = "xlnx,xps-bram-if-cntlr-> > > 1.00.a";> > > >> reg = < ffffe000 2000 >;> > > >> xlnx,family = "virtex4";> > > >> } ;> > > >> xps_intc_0: interrupt-controller@81800000 {> > > >> #interrupt-cells = <2>;> > > >> compatible = "xlnx,xps-intc-1.00.a";> > > >> interrupt-controller ;> > > >> reg = < 81800000 10000 >;> > > >> xlnx,num-intr-inputs = <7>;> > > >> } ;> > > >> } ;> > > >> ppc405_0_dplb1: plb@1 {> > > >> #address-cells = <1>;> > > >> #size-cells = <1>;> > > >> compatible = "xlnx,plb-v46-1.02.a";> > > >> ranges ;> > > >> } ;> > > >> } ;> > > >>> > > >>> > > >>> > > >> -----Original Message-----> > > >> From: Magnus Hjorth [mailto:mh@omnisys.se]> > > >> Sent: Saturday, March 29, 2008 6:54 AM> > > >> To: git> > > >> Cc: linuxppc-embedded@ozlabs.org> > > >> Subject: Xilinx LLTEMAC driver issues> > > >>> > > >> Hi,> > > >>> > > >> I'm having some networking troubles with the Xilinx LLTEMAC driver from> > the> > > >> Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,> > > >> xps_ll_temac v1.00.b> > > >>> > > >> The weird thing is, that it sort of half works. It successfully makes a> > DHCP> > > >> request and gets its IP address. I tried setting up a tftpd server, and> > I can> > > >> see UDP requests coming in but the response doesn't seem to come out. I> > also> > > >> tried running a TCP server on the board, and it can see and accept> > incoming> > > >> connections but after that no data seems to get through. I can ping out> > and> > > >> get around 40% packet loss.> > > >>> > > >> Looking at /proc/interrupts, I can see both TxDma interrupts and RxDma> > > >> interrupts. No eth0 interrupts but that seems to be OK judging by the> > driver> > > >> source comments. Ifconfig shows no collistions, no dropped packets, no> > > errors,> > > >> so the system seems to think that everything is OK.> > > >>> > > >> Clues anyone? I'm starting to run out of ideas...> > > >>> > > >> Best regards,> > > >> Magnus> > > >>> > > >>> > > >> --> > > >>> > > >> Magnus Hjorth, M.Sc.> > > >> Omnisys Instruments AB> > > >> Gruvgatan 8> > > >> SE-421 30 Västra Frölunda, SWEDEN> > > >> Phone: +46 31 734 34 09> > > >> Fax: +46 31 734 34 29> > > >> http://www.omnisys.se> > > >>> > > >> > > > _______________________________________________> > > > Linuxppc-embedded mailing list> > > > Linuxppc-embedded@ozlabs.org> > > > https://ozlabs.org/mailman/listinfo/linuxppc-embedded> > _______________________________________________> > Linuxppc-embedded mailing list> > Linuxppc-embedded@ozlabs.org> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded> >> >> > --> > Johann Baudy> > johaahn@gmail.com> > ________________________________> > 用 Windows Live Spaces 展示个性自我，与好友分享生活！ 了解更多信息！> > > > -- > Johann Baudy> johaahn@gmail.com
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Re: Xilinx LLTEMAC driver issues

[Johann Baudy]

RGVhciBNaW5nLAoKSSd2ZSBtYWRlIHRoaXMgdGVzdCBvbiBFREsgOS4yICsgbGxfdGVtYWMgMS4w
MC5iICsgbGx0ZW1hYyBodyBwYXRjaAooZnRwOi8vZnRwLnhpbGlueC5jb20vcHViL2FwcGxpY2F0
aW9ucy9taXNjL3R4X2xsX2lmX2VkazEwXzEuemlwCihzdGlsbCB1cCkpKyBsbF90ZW1hYyBkcml2
ZXIgcGF0Y2guCkknbSBjdXJyZW50bHkgd29ya2luZyBvbiBhIDEwLjEgcmViYXNlLiAob25nb2lu
Zy4uLikKCkJlc3QgcmVnYXJkcywKSm9oYW5uCgoKT24gRnJpLCBBcHIgNCwgMjAwOCBhdCAxMDox
MSBBTSwgTWluZ0xpdSA8ZWVtaW5nbGl1QGhvdG1haWwuY29tPiB3cm90ZToKPgo+ICBEZWFyIEpv
aGFubiwKPiAgVGhhbmtzIGZvciB0aGUgcHJvbXB0IHJlcGx5Lgo+Cj4gIEFjdHVhbGx5IEkgYW0g
dXNpbmcgRURLIDEwLjEgZXZhbHVhdGlvbiB2ZXJzaW9uLiBBY2NvcmRpbmcgdG8gWGlsaW54J3MK
PiBhbnN3ZXIsIHRoZXkgc2FpZCB0aGUgcHJvYmxlbSB3aWxsIGJlIGZpeGVkIGluIDEwLjEgYWxy
ZWFkeS4gVW5mb3J0dW5hdGVseSBJCj4gc3RpbGwgbWV0IGl0IGluIG15IGRlc2lnbi4KPgo+ICBE
byB5b3UgaGFwcGVuIHRvIHN0aWxsIGhhdmUgdGhlIGZpbGUgdHhfaWlfaWYuemlwPyBJIGNhbm5v
dCBkb3dubG9hZCBpdAo+IGZyb20gWGlsaW54IGFueSBtb3JlLiBUaGFuayB5b3Ugc28gbXVjaCBp
ZiB5b3UgY2FuIGdpdmUgbWUgYSBjb3B5Lgo+Cj4gIEJSCj4gIE1pbmcKPgo+Cj4gPiBEYXRlOiBG
cmksIDQgQXByIDIwMDggMDk6NTM6MDcgKzAwMDAKPiA+IEZyb206IGpvaGFhaG5AZ21haWwuY29t
Cj4gPiBUbzogZWVtaW5nbGl1QGhvdG1haWwuY29tCj4KPiA+IFN1YmplY3Q6IFJlOiBYaWxpbngg
TExURU1BQyBkcml2ZXIgaXNzdWVzCj4gPiBDQzogbWhAb21uaXN5cy5zZTsgbGludXhwcGMtZW1i
ZWRkZWRAb3psYWJzLm9yZzsgam9obi5saW5uQHhpbGlueC5jb207Cj4gZ2l0QHhpbGlueC5jb20K
Pgo+Cj4gPgo+ID4gSGkgTWluZywKPiA+Cj4gPiBJJ3ZlIGFscmVhZHkgdXNlZCBuZXRwZXJmICh3
aXRob3V0IE5GUykgc3VjY2Vzc2Z1bGx5Lgo+ID4gQXJlIHlvdSB1c2luZyAxLjAwLmIgYW5kIDku
MiwgaWYgeWVzIGxvb2sgYXQgQVIgIzI5NzA4Lgo+ID4KPiA+IEJlc3QgcmVnYXJkcywKPiA+IEpv
aGFubgo+ID4KPiA+IE9uIEZyaSwgQXByIDQsIDIwMDggYXQgOTozNiBBTSwgTWluZ0xpdSA8ZWVt
aW5nbGl1QGhvdG1haWwuY29tPiB3cm90ZToKPiA+ID4KPiA+ID4gRGVhciBKb2hhbm4sCj4gPiA+
IFByZXZpb3VzbHkgSSBzYWlkIHRoaXMgcGF0Y2ggaGVscHMgZm9yIHRoZSBjaGVja3N1bSBlcnJv
ciBwcm9ibGVtLiBCdXQKPiBub3cKPiA+ID4gSSBmb3VuZCBzb21lIG5ldyBpc3N1ZXMuIFllcy4g
YXQgbGVhc3Qgd2l0aCB0aGlzIHBhdGNoLCBzb21ldGhpbmcgaXMKPiBiZXR0ZXIKPiA+ID4gYW5k
IGF0IGxlYXN0IHdlIGNhbiB1c2UgdGhlIGhhcmR3YXJlIGNoZWNrc3VtIG9mZmxvYWRpbmcgdG8g
ZG8KPiBzb21ldGhpbmcsCj4gPiA+IGZvciBleGFtcGxlIEkgY2FuIG1vdW50IHRoZSBORlMgcm9v
dCBmaWxlIHN5c3RlbS4gSG93ZXZlciB3aGVuIEkgdHJ5IHRvCj4gPiA+IG1lYXN1cmUgdGhlIGV0
aGVybmV0IGJhbmR3aWR0aCB3aXRoIG5ldHBlcmYsIHNvbWV0aGluZyBnb2VzIHdyb25nIGFuZAo+
IHRoZQo+ID4gPiBORlMgbW91bnQgd2lsbCBiZSBicm9rZW4uIEkgZ3Vlc3MgdGhpcyBpcyBiZWNh
dXNlIG9mIHRoZSBsYXJnZSBidWxrIGRhdGEKPiA+ID4gdHJhbnNmZXIgYW5kIG1heWJlIHRodXMg
aXQgdHJpZ2dlcnMgdGhlIGNoZWNrc3VtIHByb2JsZW0gdG8gaGFwcGVuLgo+ID4gPgo+ID4gPiBE
byB5b3UgaGF2ZSB0aGUgc2FtZSBzaXR1YXRpb24/IE9yIHNvbWVvbmUgZWxzZSBoYXMgdGhlIHNh
bWUgcHJvYmxlbT8gSQo+ID4gPiB3aWxsIGFwcHJlY2lhdGUgaWYgeW91IGNhbiBzaGFyZSB5b3Vy
IGV4cGVyaWVuY2UuIFRoYW5rcyBhIGxvdC4KPiA+ID4KPiA+ID4gQlIKPiA+ID4gTWluZwo+ID4g
Pgo+ID4gPgo+ID4gPgo+ID4gPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwo+ID4g
PiBEYXRlOiBXZWQsIDIgQXByIDIwMDggMDc6MjA6NDMgKzAwMDAKPiA+ID4gRnJvbTogam9oYWFo
bkBnbWFpbC5jb20KPiA+ID4gVG86IG1oQG9tbmlzeXMuc2UKPiA+ID4KPiA+ID4gU3ViamVjdDog
UmU6IFhpbGlueCBMTFRFTUFDIGRyaXZlciBpc3N1ZXMKPiA+ID4gQ0M6IGxpbnV4cHBjLWVtYmVk
ZGVkQG96bGFicy5vcmc7IEpvaG4uTGlubkB4aWxpbnguY29tOyBnaXRAeGlsaW54LmNvbQo+ID4g
Pgo+ID4gPgo+ID4gPgo+ID4gPiBJJ3ZlIHNvbHZlZCB0aGlzIGNoZWNrc3VtIG9mZmxvYWRpbmcg
aXNzdWUgd2l0aCB0aGlzIGJlbG93IHBhdGNoLgo+ID4gPiBJdCBtYXkgaGVscCwgaWYgeW91IG5l
ZWQgcGVyZm9ybWFuY2UuIEl0IGNlcnRhaW5seSBuZWVkcyByZXZpZXcgYnV0IGl0Cj4gd29ya3MK
PiA+ID4gb24gbXkgc2lkZS4KPiA+ID4KPiA+ID4gLS0tIHhpbGlueGdpdC9kcml2ZXJzL25ldC94
aWxpbngKPiA+ID4gX2xsdGVtYWMveGxsdGVtYWNfbWFpbi5jLm9yaWcgMjAwOC0wMy0yMSAwOTox
MTo0My4wMDAwMDAwMDAgKzAxMDAKPiA+ID4gKysrIHhpbGlueGdpdC9kcml2ZXJzL25ldC94aWxp
bnhfbGx0ZW1hYy94bGx0ZW1hY19tYWluLmMgMjAwOC0wMy0yMQo+ID4gPiAwOToyNDoyMy4wMDAw
MDAwMDAgKzAxMDAKPiA+ID4gQEAgLTEzMyw3ICsxMzMsNyBAQAo+ID4gPiAoWExsRG1hX21CZFJl
YWQoKEJkUHRyKSwgWExMRE1BX0JEX1NUU0NUUkxfVVNSMF9PRkZTRVQpKSAmCj4gPiA+IDB4RkZG
RkZGRkUgKQo+ID4gPgo+ID4gPiAjZGVmaW5lIEJkQ3N1bVNldHVwKEJkUHRyLCBTdGFydCwgSW5z
ZXJ0KSBcCj4gPiA+IC0gWExsRG1hX21CZFdyaXRlKChCZFB0ciksIFhMTERNQV9CRF9VU1IxX09G
RlNFVCwgKFN0YXJ0KSA8PCAxNiB8Cj4gPiA+IChJbnNlcnQpKQo+ID4gPiArIFhMbERtYV9tQmRX
cml0ZSgoQmRQdHIpLCBYTExETUFfQkRfVVNSMV9PRkZTRVQsICgoU3RhcnQpIDw8IDE2KSB8Cj4g
PiA+IChJbnNlcnQpKQo+ID4gPgo+ID4gPiAvKiBVc2VkIGZvciBkZWJ1Z2dpbmcgKi8KPiA+ID4g
I2RlZmluZSBCZENzdW1JbnNlcnQoQmRQdHIpIFwKPiA+ID4gQEAgLTE1NDAsNyArMTU0MSw3IEBA
IHN0YXRpYyBpbnQgeGVuZXRfRG1hU2VuZF9pbnRlcm5hbChzdHJ1Y3QKPiA+ID4gLyoKPiA+ID4g
KiBpZiB0eCBjaGVja3N1bSBvZmZsb2FkaW5nIGlzIGVuYWJsZWQsIHdoZW4gdGhlIGV0aGVybmV0
IHN0YWNrCj4gPiA+ICogd2FudHMgdXMgdG8gcGVyZm9ybSB0aGUgY2hlY2tzdW0gaW4gaGFyZHdh
cmUsCj4gPiA+IC0gKiBza2ItPmlwX3N1bW1lZCBpcyBDSEVDS1NVTV9DT01QTEVURS4gT3RoZXJ3
aXNlIHNrYi0+aXBfc3VtbWVkIGlzCj4gPiA+ICsgKiBza2ItPmlwX3N1bW1lZCBpcyBDSEVDS1NV
TV9QQVJUSUFMLiBPdGhlcndpc2Ugc2tiLT5pcF9zdW1tZWQgaXMKPiA+ID4gKiBDSEVDS1NVTV9O
T05FLCBtZWFuaW5nIHRoZSBjaGVja3N1bSBpcyBhbHJlYWR5IGRvbmUsIG9yCj4gPiA+ICogQ0hF
Q0tTVU1fVU5ORUNFU1NBUlksIG1lYW5pbmcgY2hlY2tzdW1taW5nIGlzIHR1cm5lZCBvZmYgKGUu
Zy4KPiA+ID4gKiBsb29wYmFjayBpbnRlcmZhY2UpCj4gPiA+IEBAIC0xNTY1LDkgKzE1NjYsMTEg
QEAgc3RhdGljIGludCB4ZW5ldF9EbWFTZW5kX2ludGVybmFsKHN0cnVjdAo+ID4gPiAqIHNrYl90
cmFuc3BvcnRfaGVhZGVyKHNrYikgcG9pbnRzIHRvIHRoZSBiZWdpbm5pbmcgb2YgdGhlIGlwIGhl
YWRlcgo+ID4gPiAqCj4gPiA+ICovCj4gPiA+IC0gaWYgKHNrYi0+aXBfc3VtbWVkID09IENIRUNL
U1VNX0NPTVBMRVRFKSB7Cj4gPiA+ICsgaWYgKHNrYi0+aXBfc3VtbWVkID09IENIRUNLU1VNX1BB
UlRJQUwpIHsKPiA+ID4gKwo+ID4gPiArIHVuc2lnbmVkIGludCBjc3VtX3N0YXJ0X29mZiA9IHNr
Yl90cmFuc3BvcnRfb2Zmc2V0KHNrYik7Cj4gPiA+ICsgdW5zaWduZWQgaW50IGNzdW1faW5kZXhf
b2ZmID0gY3N1bV9zdGFydF9vZmYgKyBza2ItPmNzdW1fb2Zmc2V0Owo+ID4gPgo+ID4gPiAtIHVu
c2lnbmVkIGNoYXIgKnJhdyA9IHNrYl90cmFuc3BvcnRfaGVhZGVyKHNrYik7Cj4gPiA+ICNpZiAw
Cj4gPiA+IHsKPiA+ID4gdW5zaWduZWQgaW50IGNzdW0gPSBfeGVuZXRfdHhfY3N1bShza2IpOwo+
ID4gPiBAQCAtMTU3OCw5ICsxNTgxLDggQEAgc3RhdGljIGludCB4ZW5ldF9EbWFTZW5kX2ludGVy
bmFsKHN0cnVjdAo+ID4gPiB9Cj4gPiA+ICNlbHNlCj4gPiA+IEJkQ3N1bUVuYWJsZShiZF9wdHIp
Owo+ID4gPiAtIEJkQ3N1bVNldHVwKGJkX3B0ciwgcmF3IC0gc2tiLT5kYXRhLAo+ID4gPiAtIChy
YXcgLSBza2ItPmRhdGEpICsgc2tiLT5jc3VtKTsKPiA+ID4gLQo+ID4gPiArIEJkQ3N1bVNldHVw
KGJkX3B0ciwgY3N1bV9zdGFydF9vZmYsCj4gPiA+ICsgY3N1bV9pbmRleF9vZmYpOwo+ID4gPiAj
ZW5kaWYKPiA+ID4gbHAtPnR4X2h3X2NzdW1zKys7Cj4gPiA+IH0KPiA+ID4gQEAgLTMyNzcsNyAr
MzI3OSw3IEBAIHN0YXRpYyBpbnQgX19kZXZpbml0IHh0ZW5ldF9vZl9wcm9iZShzdHIKPiA+ID4g
c3RydWN0IHJlc291cmNlICpyX2lycSA9ICZyX2lycV9zdHJ1Y3Q7IC8qIEludGVycnVwdCByZXNv
dXJjZXMgKi8KPiA+ID4gc3RydWN0IHJlc291cmNlICpyX21lbSA9ICZyX21lbV9zdHJ1Y3Q7IC8q
IElPIG1lbSByZXNvdXJjZXMgKi8KPiA+ID4gc3RydWN0IHhsbHRlbWFjX3BsYXRmb3JtX2RhdGEg
KnBkYXRhID0gJnBkYXRhX3N0cnVjdDsKPiA+ID4gLSB2b2lkICptYWNfYWRkcmVzczsKPiA+ID4g
KyBjb25zdCB2b2lkICptYWNfYWRkcmVzczsKPiA+ID4gaW50IHJjID0gMDsKPiA+ID4gY29uc3Qg
cGhhbmRsZSAqbGxpbmtfY29ubmVjdGVkX2hhbmRsZTsKPiA+ID4gc3RydWN0IGRldmljZV9ub2Rl
ICpsbGlua19jb25uZWN0ZWRfbm9kZTsKPiA+ID4KPiA+ID4KPiA+ID4gT24gTW9uLCBNYXIgMzEs
IDIwMDggYXQgMTE6MTAgQU0sIE1hZ251cyBIam9ydGggPG1oQG9tbmlzeXMuc2U+IHdyb3RlOgo+
ID4gPgo+ID4gPiBEZWFjdGl2YXRpbmcgY2hlY2tzdW0gb2ZmbG9hZGluZyBoZWxwZWQgYSBsb3Qh
IEkgc3RpbGwgaGF2ZSBzb21lIHBhY2tldAo+IGxvc3MKPiA+ID4gYW5kIG5vdCB0aGUgYmVzdCBw
ZXJmb3JtYW5jZSAoVEZUUCB0cmFuc2ZlciBhYm91dCAxMDAga2J5dGUvcykgYnV0IGF0Cj4gbGVh
c3QKPiA+ID4gaXQgd29ya3MuCj4gPiA+Cj4gPiA+IFRoYW5rcyEKPiA+ID4KPiA+ID4gLy9NYWdu
dXMKPiA+ID4KPiA+ID4KPiA+ID4KPiA+ID4KPiA+ID4gPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2Ut
LS0tLQo+ID4gPiA+IEZyb206IHJ6YTEgW21haWx0bzpyemExQHNvLWxvZ2ljLm5ldF0KPiA+ID4g
PiBTZW50OiBkZW4gMzEgbWFycyAyMDA4IDExOjE0Cj4gPiA+ID4gVG86IE1hZ251cyBIam9ydGgK
PiA+ID4gPiBDYzogSm9obiBMaW5uOyBnaXQ7IGxpbnV4cHBjLWVtYmVkZGVkQG96bGFicy5vcmcK
PiA+ID4gPiBTdWJqZWN0OiBSZTogWGlsaW54IExMVEVNQUMgZHJpdmVyIGlzc3Vlcwo+ID4gPiA+
Cj4gPiA+ID4gSGkgTWFnbnVzLAo+ID4gPiA+Cj4gPiA+ID4gMS4KPiA+ID4gPiBJIGFtIHVzaW5n
IG5lYXJseSB0aGUgc2FtZSB2ZXJzaW9ucyB0aGVuIHlvdSBhbmQgZ290IHRoZSBzYW1lIHByb2Js
ZW1zCj4gPiA+ID4gdG9vIDstKS4KPiA+ID4gPiBJIHRoaW5rIHRoZXJlIGFyZSBzb21lIHByb2Js
ZW1zIHdpdGggdGhlIGNoZWNrc3VtIG9mZmxvYWRpbmcuCj4gPiA+ID4gVHJ5IHRvIHNuaWZmIHRo
ZSBzb21lIHBhY2thZ2VzIChlLmcuIHdpcmVzaGFyaykuLi4KPiA+ID4gPiBGb3IgbWUgSUNNUCAo
cGluZykgd29ya2VkIGJ1dCB1ZHAgYW5kIHRjcCBub3QgKGJlY2F1c2Ugb2ZmIGEgd3JvbmcKPiA+
ID4gPiBjaGVja3N1bSBpbiB0aGUgdHJhbnNwb3J0IGxheWVyKS4KPiA+ID4gPiBBIHF1aWNrIHNv
bHV0aW9uIGlzIHRvIGp1c3QgZGVhY3RpdmF0ZSBjaGVja3N1bSBvZmZsb2FkaW5nLgo+ID4gPiA+
Cj4gPiA+ID4gMi4KPiA+ID4gPiBJIHJlbWVtYmVyIHNvbWUgcHJvYmxlbXMgd2l0aCBWaXJ0ZXgt
NCBwcmVzYW1wbGVzIHRvby4KPiA+ID4gPiBUaGVyZSB3aGVyZSBwcm9ibGVtcyB3aXRoIHRoZSBo
YXJkLXRlbWFjIHdyYXBwZXIuIFlvdSBoYWQgdG8gdXNlCj4gMS4wMC5hCj4gPiA+ID4gYW5kIG5v
dCBiIHZlcnNpb24uCj4gPiA+ID4gQnV0IEkgZG9uJ3QgaGF2ZSB0aGVzZSBwcm9ibGVtcyB3aXRo
IHRoZSBFREsgOS4yc3AyL0lTRTkuMnNwMyBhbnltb3JlLgo+ID4gPiA+Cj4gPiA+ID4gYWxsIHRo
ZSBiZXN0LAo+ID4gPiA+IFJvYmVydAo+ID4gPiA+Cj4gPiA+ID4gTWFnbnVzIEhqb3J0aCB3cm90
ZToKPiA+ID4gPiA+IEhpIEpvaG4sCj4gPiA+ID4gPgo+ID4gPiA+ID4gVGhhbmtzIGZvciB0aGUg
dmVyeSBmYXN0IHJlcGx5ISBSaWdodCBub3cgSSdtIG5vdCBhdCB3b3JrIHNvIEkgZG9uJ3QKPiA+
ID4gPiA+IGhhdmUgdGhlIGJvYXJkIG9yIEVESyBoZXJlIHRvIHRlc3QgYW55dGhpbmcuCj4gPiA+
ID4gPgo+ID4gPiA+ID4gSSdtIHVzaW5nIGNoZWNrc3VtIG9mZmxvYWQsIGJ1dCBJIGRvbid0IGtu
b3cgaWYgRFJFIGlzIGVuYWJsZWQgb3IKPiBub3QuIEkKPiA+ID4gPiA+IGNhbid0IHJlY2FsbCBz
ZWVpbmcgYW55IHNldHRpbmcgdG8gZW5hYmxlL2Rpc2FibGUgRFJFLi4KPiA+ID4gPiA+Cj4gPiA+
ID4gPiBBIGZldyB0aGluZ3MgdGhhdCBjcm9zc2VkIG15IG1pbmQ6Cj4gPiA+ID4gPgo+ID4gPiA+
ID4gTGFzdCB5ZWFyIEkgZGlkIGEgZGVzaWduIHdpdGggRURLIDguMiwgYmFjayB0aGVuIHRoZXJl
IHdhcyBhbiBpc3N1ZQo+IHdpdGgKPiA+ID4gPiA+IHRoZSBNTDQwMyBib2FyZHMgaGF2aW5nIGFu
IG9sZCByZXZpc2lvbiBvZiB0aGUgRlBHQSB3aGljaCB3YXNuJ3QKPiA+ID4gPiA+IGNvbXBhdGli
bGUgd2l0aCBzb21lIHZlcnNpb25zIG9mIHRoZSBJUCBjb3JlLiBUaGVyZSBhcmUgbm8gc3VjaAo+
IHZlcnNpb24KPiA+ID4gPiA+IGlzc3VlcyB3aXRoIHRoZSB4cHNfbGxfdGVtYWM/Cj4gPiA+ID4g
Pgo+ID4gPiA+ID4gSSBkb24ndCB0aGluayB0aGF0IEkgaGFkIHBoeS1hZGRyIHNldCBpbiB0aGUg
RFRTIGZpbGUuIFdpbGwgdGVzdAo+IHRoYXQgb24KPiA+ID4gPiA+IE1vbmRheS4KPiA+ID4gPiA+
Cj4gPiA+ID4gPiBCZXN0IHJlZ2FyZHMsCj4gPiA+ID4gPiBNYWdudXMKPiA+ID4gPiA+Cj4gPiA+
ID4gPgo+ID4gPiA+ID4gT24gU2F0LCAyMDA4LTAzLTI5IGF0IDA3OjU4IC0wNjAwLCBKb2huIExp
bm4gd3JvdGU6Cj4gPiA+ID4gPgo+ID4gPiA+ID4+IEhpIE1hZ251cywKPiA+ID4gPiA+Pgo+ID4g
PiA+ID4+IFNvcnJ5IHRvIGhlYXIgeW91J3JlIGhhdmluZyBwcm9ibGVtcyB3aXRoIGl0Lgo+ID4g
PiA+ID4+Cj4gPiA+ID4gPj4gSSBhbSBkb2luZyB0ZXN0aW5nIG9uIGFuIE1MNDA1IHdoaWNoIGlz
IHRoZSBzYW1lIGJvYXJkIGJ1dCB3aXRoIGEKPiA+ID4gYmlnZ2VyCj4gPiA+ID4gRlBHQSwgYnV0
IHdpdGggcHBjIGFyY2ggYW5kIEkgZG9uJ3Qgc2VlIHRoaXMgaXNzdWUuIEkgaGF2ZSBkb25lCj4g
bGltaXRlZAo+ID4gPiB0ZXN0aW5nCj4gPiA+ID4gd2l0aCBwb3dlcnBjIGFyY2ggYW5kIHRoZSBM
TCBURU1BQywgYnV0IEkgZGlkbid0IHNlZSB0aGlzIGlzc3VlIHRoZXJlCj4gPiA+IGVpdGhlci4K
PiA+ID4gPiBQb3dlcnBjIGFyY2ggaXMgZGVmaW5pdGVseSBsZXNzIG1hdHVyZSBpbiBteSBleHBl
cmllbmNlIHRoYW4gdGhlIHBwYwo+IGFyY2guCj4gPiA+IEknbGwKPiA+ID4gPiBkbyBhIHF1aWNr
IHRlc3Qgd2l0aCBteSBwb3dlcnBjIGFyY2ggYW5kIG1ha2Ugc3VyZSBhZ2FpbiBJJ20gbm90Cj4g
c2VlaW5nCj4gPiA+IGl0Lgo+ID4gPiA+ID4+Cj4gPiA+ID4gPj4gTXkga2VybmVsIGlzIGZyb20g
dGhlIFhpbGlueCBHaXQgdHJlZSwgYnV0IHRoZXJlIGhhdmUgYmVlbiBhIG51bWJlcgo+IG9mCj4g
PiA+ID4gY2hhbmdlcyB3ZSBoYXZlIHB1c2hlZCBvdXQgc28gSSBkb24ndCBrbm93IGhvdyBsb25n
IGFnbyB5b3UgcHVsbGVkCj4gZnJvbQo+ID4gPiB0aGUgR2l0Cj4gPiA+ID4gdHJlZS4KPiA+ID4g
PiA+Pgo+ID4gPiA+ID4+IE15IEVESyBwcm9qZWN0IGlzIDEwLjEgc28gaXQncyBhIGxpdHRsZSBu
ZXdlci4gSSBhbSB1c2luZyBMTCBURU1BQwo+ID4gPiAxLjAxYSBzbwo+ID4gPiA+IGl0J3MgYSBs
aXR0bGUgbmV3ZXIuIEkgcmV2aWV3ZWQgdGhlIGNoYW5nZSBsb2cgZm9yIHRoZSBMTCBURU1BQyBh
bmQKPiBkb24ndAo+ID4gPiBzZWUKPiA+ID4gPiBhbnkgYmlnIHByb2JsZW1zIHRoYXQgd2VyZSBm
aXhlZCBpbiB0aGUgbmV3ZXIgdmVyc2lvbnMsIG1vcmUgbmV3Cj4gZmVhdHVyZXMuCj4gPiA+IEkn
bGwKPiA+ID4gPiBjaGVjayB3aXRoIHNvbWUgb3RoZXJzIGhlcmUgdG8gc2VlIGlmIEkgbWlzc2Vk
IHNvbWV0aGluZyB0aGVyZS4KPiA+ID4gPiA+Pgo+ID4gPiA+ID4+IEkgYW0gdXNpbmcgRE1BIGFs
c28sIGJ1dCBubyBEUkUgb3IgY2hlY2tzdW0gb2ZmbG9hZC4gWW91IGRpZG4ndCBzYXkKPiA+ID4g
YW55dGhpbmcKPiA+ID4gPiBhYm91dCB0aG9zZS4gSSdtIGdvaW5nIHRvIGluc2VydCBteSBtaHMg
ZmlsZSB0aGF0IGRlc2NyaWJlcyBteSBzeXN0ZW0KPiB0bwo+ID4gPiBsZXQgeW91Cj4gPiA+ID4g
Y29tcGFyZSB5b3VyIHN5c3RlbSBjb25maWd1cmF0aW9uLiBJdCdzIG5vdCBjbGVhciB0byBtZSB5
ZXQgaWYgeW91Cj4gaGF2ZSBhCj4gPiA+IGgvdyBvcgo+ID4gPiA+IHMvdyBwcm9ibGVtLgo+ID4g
PiA+ID4+Cj4gPiA+ID4gPj4gSSdsbCBhbHNvIGluc2VydCBzb21lIG9mIG15IGRldmljZSB0cmVl
IHdpdGggdGhlIExMIFRFTUFDIHNvIHlvdQo+IGNhbgo+ID4gPiBjb21wYXJlCj4gPiA+ID4gKGln
bm9yZSAxNjU1MCBzdHVmZiBhcyB3ZSBhcmUgc3RpbGwgd29ya2luZyBvbiB0aGF0KS4KPiA+ID4g
PiA+Pgo+ID4gPiA+ID4+IFNpbmNlIHlvdSBjYW4ndCBwaW5nIHJlbGlhYmx5IEkgd291bGQgcHJv
YmFibHkgZm9jdXMgb24gdGhhdCBzaW5jZQo+IGl0J3MKPiA+ID4gPiBzaW1wbGVyIHRoYW4gdGhl
IG90aGVyIGlzc3VlcyB5b3UncmUgc2VlaW5nLgo+ID4gPiA+ID4+Cj4gPiA+ID4gPj4gVGhhbmtz
LAo+ID4gPiA+ID4+IEpvaG4KPiA+ID4gPiA+Pgo+ID4gPiA+ID4+Cj4gPiA+ID4gPj4KPiA+ID4g
PiA+PiAjCj4gPiA+ID4KPiA+ID4KPiAjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMj
IyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMKPiA+ID4gPiA+PiAj
IENyZWF0ZWQgYnkgQmFzZSBTeXN0ZW0gQnVpbGRlciBXaXphcmQgZm9yIFhpbGlueCBFREsgMTAu
MS4xIEJ1aWxkCj4gPiA+ID4gRURLX0tfU1AxLjEKPiA+ID4gPiA+PiAjIFRodSBGZWIgMTQgMTQ6
MTE6MTIgMjAwOAo+ID4gPiA+ID4+ICMgVGFyZ2V0IEJvYXJkOiBYaWxpbnggVmlydGV4IDQgTUw0
MDUgRXZhbHVhdGlvbiBQbGF0Zm9ybSBSZXYgMQo+ID4gPiA+ID4+ICMgRmFtaWx5OiB2aXJ0ZXg0
Cj4gPiA+ID4gPj4gIyBEZXZpY2U6IHhjNHZmeDIwCj4gPiA+ID4gPj4gIyBQYWNrYWdlOiBmZjY3
Mgo+ID4gPiA+ID4+ICMgU3BlZWQgR3JhZGU6IC0xMAo+ID4gPiA+ID4+ICMgUHJvY2Vzc29yOiBw
cGM0MDVfMAo+ID4gPiA+ID4+ICMgUHJvY2Vzc29yIGNsb2NrIGZyZXF1ZW5jeTogMzAwLjAwIE1I
ego+ID4gPiA+ID4+ICMgQnVzIGNsb2NrIGZyZXF1ZW5jeTogMTAwLjAwIE1Iego+ID4gPiA+ID4+
ICMgT24gQ2hpcCBNZW1vcnkgOiA4IEtCCj4gPiA+ID4gPj4gIyBUb3RhbCBPZmYgQ2hpcCBNZW1v
cnkgOiAxMjggTUIKPiA+ID4gPiA+PiAjIC0gRERSX1NEUkFNID0gMTI4IE1CCj4gPiA+ID4gPj4g
Iwo+ID4gPiA+Cj4gPiA+Cj4gIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMj
IyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjIyMjCj4gPiA+ID4gPj4gUEFSQU1F
VEVSIFZFUlNJT04gPSAyLjEuMAo+ID4gPiA+ID4+Cj4gPiA+ID4gPj4KPiA+ID4gPiA+PiBQT1JU
IGZwZ2FfMF9SUzIzMl9VYXJ0X3Npbl9waW4gPSBmcGdhXzBfUlMyMzJfVWFydF9zaW4sIERJUiA9
IEkKPiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9SUzIzMl9VYXJ0X3NvdXRfcGluID0gZnBnYV8wX1JT
MjMyX1VhcnRfc291dCwgRElSID0gTwo+ID4gPiA+ID4+IFBPUlQgZnBnYV8wX0xFRHNfNEJpdF9H
UElPX0lPX3BpbiA9IGZwZ2FfMF9MRURzXzRCaXRfR1BJT19JTywgRElSID0KPiA+ID4gSU8sIFZF
Qwo+ID4gPiA+ID0gWzA6M10KPiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9JSUNfRUVQUk9NX1NjbF9w
aW4gPSBmcGdhXzBfSUlDX0VFUFJPTV9TY2wsIERJUiA9IElPCj4gPiA+ID4gPj4gUE9SVCBmcGdh
XzBfSUlDX0VFUFJPTV9TZGFfcGluID0gZnBnYV8wX0lJQ19FRVBST01fU2RhLCBESVIgPSBJTwo+
ID4gPiA+ID4+IFBPUlQgZnBnYV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX0NMS19waW4g
PQo+ID4gPiA+IGZwZ2FfMF9TeXNBQ0VfQ29tcGFjdEZsYXNoX1N5c0FDRV9DTEssIERJUiA9IEkK
PiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9TeXNBQ0VfQ29tcGFjdEZsYXNoX1N5c0FDRV9NUEFfcGlu
ID0KPiA+ID4gPiBmcGdhXzBfU3lzQUNFX0NvbXBhY3RGbGFzaF9TeXNBQ0VfTVBBLCBESVIgPSBP
LCBWRUMgPSBbNjoxXQo+ID4gPiA+ID4+IFBPUlQgZnBnYV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hf
U3lzQUNFX01QRF9waW4gPQo+ID4gPiA+IGZwZ2FfMF9TeXNBQ0VfQ29tcGFjdEZsYXNoX1N5c0FD
RV9NUEQsIERJUiA9IElPLCBWRUMgPSBbMTU6MF0KPiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9TeXNB
Q0VfQ29tcGFjdEZsYXNoX1N5c0FDRV9DRU5fcGluID0KPiA+ID4gPiBmcGdhXzBfU3lzQUNFX0Nv
bXBhY3RGbGFzaF9TeXNBQ0VfQ0VOLCBESVIgPSBPCj4gPiA+ID4gPj4gUE9SVCBmcGdhXzBfU3lz
QUNFX0NvbXBhY3RGbGFzaF9TeXNBQ0VfT0VOX3BpbiA9Cj4gPiA+ID4gZnBnYV8wX1N5c0FDRV9D
b21wYWN0Rmxhc2hfU3lzQUNFX09FTiwgRElSID0gTwo+ID4gPiA+ID4+IFBPUlQgZnBnYV8wX1N5
c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX1dFTl9waW4gPQo+ID4gPiA+IGZwZ2FfMF9TeXNBQ0Vf
Q29tcGFjdEZsYXNoX1N5c0FDRV9XRU4sIERJUiA9IE8KPiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9T
eXNBQ0VfQ29tcGFjdEZsYXNoX1N5c0FDRV9NUElSUV9waW4gPQo+ID4gPiA+IGZwZ2FfMF9TeXNB
Q0VfQ29tcGFjdEZsYXNoX1N5c0FDRV9NUElSUSwgRElSID0gSQo+ID4gPiA+ID4+IFBPUlQgZnBn
YV8wX0REUl9TRFJBTV9ERFJfQ2xrX3BpbiA9IGZwZ2FfMF9ERFJfU0RSQU1fRERSX0NsaywgRElS
ID0KPiBPCj4gPiA+ID4gPj4gUE9SVCBmcGdhXzBfRERSX1NEUkFNX0REUl9DbGtfbl9waW4gPSBm
cGdhXzBfRERSX1NEUkFNX0REUl9DbGtfbiwKPiBESVIKPiA+ID4gPSBPCj4gPiA+ID4gPj4gUE9S
VCBmcGdhXzBfRERSX1NEUkFNX0REUl9BZGRyX3BpbiA9IGZwZ2FfMF9ERFJfU0RSQU1fRERSX0Fk
ZHIsIERJUgo+ID0KPiA+ID4gTywgVkVDCj4gPiA+ID4gPSBbMTI6MF0KPiA+ID4gPiA+PiBQT1JU
IGZwZ2FfMF9ERFJfU0RSQU1fRERSX0JhbmtBZGRyX3BpbiA9Cj4gPiA+IGZwZ2FfMF9ERFJfU0RS
QU1fRERSX0JhbmtBZGRyLCBESVIKPiA+ID4gPiA9IE8sIFZFQyA9IFsxOjBdCj4gPiA+ID4gPj4g
UE9SVCBmcGdhXzBfRERSX1NEUkFNX0REUl9DQVNfbl9waW4gPSBmcGdhXzBfRERSX1NEUkFNX0RE
Ul9DQVNfbiwKPiBESVIKPiA+ID4gPSBPCj4gPiA+ID4gPj4gUE9SVCBmcGdhXzBfRERSX1NEUkFN
X0REUl9DRV9waW4gPSBmcGdhXzBfRERSX1NEUkFNX0REUl9DRSwgRElSID0gTwo+ID4gPiA+ID4+
IFBPUlQgZnBnYV8wX0REUl9TRFJBTV9ERFJfQ1Nfbl9waW4gPSBmcGdhXzBfRERSX1NEUkFNX0RE
Ul9DU19uLCBESVIKPiA9Cj4gPiA+IE8KPiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9ERFJfU0RSQU1f
RERSX1JBU19uX3BpbiA9IGZwZ2FfMF9ERFJfU0RSQU1fRERSX1JBU19uLAo+IERJUgo+ID4gPiA9
IE8KPiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9ERFJfU0RSQU1fRERSX1dFX25fcGluID0gZnBnYV8w
X0REUl9TRFJBTV9ERFJfV0VfbiwgRElSCj4gPQo+ID4gPiBPCj4gPiA+ID4gPj4gUE9SVCBmcGdh
XzBfRERSX1NEUkFNX0REUl9ETV9waW4gPSBmcGdhXzBfRERSX1NEUkFNX0REUl9ETSwgRElSID0K
PiBPLAo+ID4gPiBWRUMgPQo+ID4gPiA+IFszOjBdCj4gPiA+ID4gPj4gUE9SVCBmcGdhXzBfRERS
X1NEUkFNX0REUl9EUVMgPSBmcGdhXzBfRERSX1NEUkFNX0REUl9EUVMsIERJUiA9IElPLAo+ID4g
PiBWRUMgPQo+ID4gPiA+IFszOjBdCj4gPiA+ID4gPj4gUE9SVCBmcGdhXzBfRERSX1NEUkFNX0RE
Ul9EUSA9IGZwZ2FfMF9ERFJfU0RSQU1fRERSX0RRLCBESVIgPSBJTywKPiBWRUMKPiA+ID4gPQo+
ID4gPiA+IFszMTowXQo+ID4gPiA+ID4+IFBPUlQgZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlfR01J
SV9UWERfMF9waW4gPQo+ID4gPiA+IGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX0dNSUlfVFhEXzAs
IERJUiA9IE8sIFZFQyA9IFs3OjBdCj4gPiA+ID4gPj4gUE9SVCBmcGdhXzBfVHJpTW9kZV9NQUNf
R01JSV9HTUlJX1RYX0VOXzBfcGluID0KPiA+ID4gPiBmcGdhXzBfVHJpTW9kZV9NQUNfR01JSV9H
TUlJX1RYX0VOXzAsIERJUiA9IE8KPiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9UcmlNb2RlX01BQ19H
TUlJX0dNSUlfVFhfRVJfMF9waW4gPQo+ID4gPiA+IGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX0dN
SUlfVFhfRVJfMCwgRElSID0gTwo+ID4gPiA+ID4+IFBPUlQgZnBnYV8wX1RyaU1vZGVfTUFDX0dN
SUlfR01JSV9UWF9DTEtfMF9waW4gPQo+ID4gPiA+IGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX0dN
SUlfVFhfQ0xLXzAsIERJUiA9IE8KPiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9UcmlNb2RlX01BQ19H
TUlJX0dNSUlfUlhEXzBfcGluID0KPiA+ID4gPiBmcGdhXzBfVHJpTW9kZV9NQUNfR01JSV9HTUlJ
X1JYRF8wLCBESVIgPSBJLCBWRUMgPSBbNzowXQo+ID4gPiA+ID4+IFBPUlQgZnBnYV8wX1RyaU1v
ZGVfTUFDX0dNSUlfR01JSV9SWF9EVl8wX3BpbiA9Cj4gPiA+ID4gZnBnYV8wX1RyaU1vZGVfTUFD
X0dNSUlfR01JSV9SWF9EVl8wLCBESVIgPSBJCj4gPiA+ID4gPj4gUE9SVCBmcGdhXzBfVHJpTW9k
ZV9NQUNfR01JSV9HTUlJX1JYX0VSXzBfcGluID0KPiA+ID4gPiBmcGdhXzBfVHJpTW9kZV9NQUNf
R01JSV9HTUlJX1JYX0VSXzAsIERJUiA9IEkKPiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9UcmlNb2Rl
X01BQ19HTUlJX0dNSUlfUlhfQ0xLXzBfcGluID0KPiA+ID4gPiBmcGdhXzBfVHJpTW9kZV9NQUNf
R01JSV9HTUlJX1JYX0NMS18wLCBESVIgPSBJCj4gPiA+ID4gPj4gUE9SVCBmcGdhXzBfVHJpTW9k
ZV9NQUNfR01JSV9NSUlfVFhfQ0xLXzBfcGluID0KPiA+ID4gPiBmcGdhXzBfVHJpTW9kZV9NQUNf
R01JSV9NSUlfVFhfQ0xLXzAsIERJUiA9IEkKPiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9UcmlNb2Rl
X01BQ19HTUlJX01ESU9fMF9waW4gPQo+ID4gPiBmcGdhXzBfVHJpTW9kZV9NQUNfR01JSV9NRElP
XzAsCj4gPiA+ID4gRElSID0gSU8KPiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9UcmlNb2RlX01BQ19H
TUlJX01EQ18wX3BpbiA9Cj4gPiA+IGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX01EQ18wLCBESVIK
PiA+ID4gPiA9IE8KPiA+ID4gPiA+PiBQT1JUIGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX1RlbWFj
UGh5X1JTVF9uX3BpbiA9Cj4gPiA+ID4gZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlfVGVtYWNQaHlf
UlNUX24sIERJUiA9IE8KPiA+ID4gPiA+PiBQT1JUIHN5c19jbGtfcGluID0gZGNtX2Nsa19zLCBE
SVIgPSBJLCBTSUdJUyA9IENMSywgQ0xLX0ZSRVEgPQo+ID4gPiAxMDAwMDAwMDAKPiA+ID4gPiA+
PiBQT1JUIHN5c19yc3RfcGluID0gc3lzX3JzdF9zLCBESVIgPSBJLCBSU1RfUE9MQVJJVFkgPSAw
LCBTSUdJUyA9Cj4gUlNUCj4gPiA+ID4gPj4KPiA+ID4gPiA+Pgo+ID4gPiA+ID4+IEJFR0lOIHBw
YzQwNV92aXJ0ZXg0Cj4gPiA+ID4gPj4gUEFSQU1FVEVSIElOU1RBTkNFID0gcHBjNDA1XzAKPiA+
ID4gPiA+PiBQQVJBTUVURVIgSFdfVkVSID0gMi4wMS5hCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENf
RkFTVEVTVF9QTEJfQ0xPQ0sgPSBEUExCMQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0lEQ1JfQkFT
RUFERFIgPSAwYjAxMDAwMDAwMDAKPiA+ID4gPiA+PiBQQVJBTUVURVIgQ19JRENSX0hJR0hBRERS
ID0gMGIwMTExMTExMTExCj4gPiA+ID4gPj4gQlVTX0lOVEVSRkFDRSBKVEFHUFBDID0ganRhZ3Bw
Y18wXzAKPiA+ID4gPiA+PiBCVVNfSU5URVJGQUNFIElQTEIwID0gcGxiCj4gPiA+ID4gPj4gQlVT
X0lOVEVSRkFDRSBEUExCMCA9IHBsYgo+ID4gPiA+ID4+IEJVU19JTlRFUkZBQ0UgSVBMQjEgPSBw
cGM0MDVfMF9pcGxiMQo+ID4gPiA+ID4+IEJVU19JTlRFUkZBQ0UgRFBMQjEgPSBwcGM0MDVfMF9k
cGxiMQo+ID4gPiA+ID4+IEJVU19JTlRFUkZBQ0UgUkVTRVRQUEMgPSBwcGNfcmVzZXRfYnVzCj4g
PiA+ID4gPj4gUE9SVCBDUE1DNDA1Q0xPQ0sgPSBwcm9jX2Nsa19zCj4gPiA+ID4gPj4gUE9SVCBF
SUNDNDA1RVhUSU5QVVRJUlEgPSBFSUNDNDA1RVhUSU5QVVRJUlEKPiA+ID4gPiA+PiBFTkQKPiA+
ID4gPiA+Pgo+ID4gPiA+ID4+IEJFR0lOIGp0YWdwcGNfY250bHIKPiA+ID4gPiA+PiBQQVJBTUVU
RVIgSU5TVEFOQ0UgPSBqdGFncHBjXzAKPiA+ID4gPiA+PiBQQVJBTUVURVIgSFdfVkVSID0gMi4w
MS5hCj4gPiA+ID4gPj4gQlVTX0lOVEVSRkFDRSBKVEFHUFBDMCA9IGp0YWdwcGNfMF8wCj4gPiA+
ID4gPj4gRU5ECj4gPiA+ID4gPj4KPiA+ID4gPiA+PiBCRUdJTiBwbGJfdjQ2Cj4gPiA+ID4gPj4g
UEFSQU1FVEVSIElOU1RBTkNFID0gcGxiCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfRENSX0lOVEZD
RSA9IDAKPiA+ID4gPiA+PiBQQVJBTUVURVIgQ19OVU1fQ0xLX1BMQjJPUEJfUkVBUkIgPSAxMDAK
PiA+ID4gPiA+PiBQQVJBTUVURVIgSFdfVkVSID0gMS4wMi5hCj4gPiA+ID4gPj4gUE9SVCBQTEJf
Q2xrID0gc3lzX2Nsa19zCj4gPiA+ID4gPj4gUE9SVCBTWVNfUnN0ID0gc3lzX2J1c19yZXNldAo+
ID4gPiA+ID4+IEVORAo+ID4gPiA+ID4+Cj4gPiA+ID4gPj4gQkVHSU4geHBzX2JyYW1faWZfY250
bHIKPiA+ID4gPiA+PiBQQVJBTUVURVIgSU5TVEFOQ0UgPSB4cHNfYnJhbV9pZl9jbnRscl8xCj4g
PiA+ID4gPj4gUEFSQU1FVEVSIEhXX1ZFUiA9IDEuMDAuYQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBD
X1NQTEJfTkFUSVZFX0RXSURUSCA9IDY0Cj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfQkFTRUFERFIg
PSAweGZmZmZlMDAwCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfSElHSEFERFIgPSAweGZmZmZmZmZm
Cj4gPiA+ID4gPj4gQlVTX0lOVEVSRkFDRSBTUExCID0gcGxiCj4gPiA+ID4gPj4gQlVTX0lOVEVS
RkFDRSBQT1JUQSA9IHhwc19icmFtX2lmX2NudGxyXzFfcG9ydAo+ID4gPiA+ID4+IEVORAo+ID4g
PiA+ID4+Cj4gPiA+ID4gPj4gQkVHSU4gYnJhbV9ibG9jawo+ID4gPiA+ID4+IFBBUkFNRVRFUiBJ
TlNUQU5DRSA9IHBsYl9icmFtX2lmX2NudGxyXzFfYnJhbQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBI
V19WRVIgPSAxLjAwLmEKPiA+ID4gPiA+PiBCVVNfSU5URVJGQUNFIFBPUlRBID0geHBzX2JyYW1f
aWZfY250bHJfMV9wb3J0Cj4gPiA+ID4gPj4gRU5ECj4gPiA+ID4gPj4KPiA+ID4gPiA+PiBCRUdJ
TiB4cHNfdWFydDE2NTUwCj4gPiA+ID4gPj4gUEFSQU1FVEVSIElOU1RBTkNFID0gUlMyMzJfVWFy
dAo+ID4gPiA+ID4+IFBBUkFNRVRFUiBIV19WRVIgPSAyLjAwLmEKPiA+ID4gPiA+PiBQQVJBTUVU
RVIgQ19JU19BXzE2NTUwID0gMQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0JBU0VBRERSID0gMHg4
M2UwMDAwMAo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0hJR0hBRERSID0gMHg4M2UwZmZmZgo+ID4g
PiA+ID4+IEJVU19JTlRFUkZBQ0UgU1BMQiA9IHBsYgo+ID4gPiA+ID4+IFBPUlQgc2luID0gZnBn
YV8wX1JTMjMyX1VhcnRfc2luCj4gPiA+ID4gPj4gUE9SVCBzb3V0ID0gZnBnYV8wX1JTMjMyX1Vh
cnRfc291dAo+ID4gPiA+ID4+IFBPUlQgSVAySU5UQ19JcnB0ID0gUlMyMzJfVWFydF9JUDJJTlRD
X0lycHQKPiA+ID4gPiA+PiBFTkQKPiA+ID4gPiA+Pgo+ID4gPiA+ID4+IEJFR0lOIHhwc19ncGlv
Cj4gPiA+ID4gPj4gUEFSQU1FVEVSIElOU1RBTkNFID0gTEVEc180Qml0Cj4gPiA+ID4gPj4gUEFS
QU1FVEVSIEhXX1ZFUiA9IDEuMDAuYQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0lOVEVSUlVQVF9Q
UkVTRU5UID0gMQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0dQSU9fV0lEVEggPSA0Cj4gPiA+ID4g
Pj4gUEFSQU1FVEVSIENfSVNfRFVBTCA9IDAKPiA+ID4gPiA+PiBQQVJBTUVURVIgQ19JU19CSURJ
UiA9IDEKPiA+ID4gPiA+PiBQQVJBTUVURVIgQ19BTExfSU5QVVRTID0gMAo+ID4gPiA+ID4+IFBB
UkFNRVRFUiBDX0JBU0VBRERSID0gMHg4MTQwMDAwMAo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0hJ
R0hBRERSID0gMHg4MTQwZmZmZgo+ID4gPiA+ID4+IEJVU19JTlRFUkZBQ0UgU1BMQiA9IHBsYgo+
ID4gPiA+ID4+IFBPUlQgR1BJT19JTyA9IGZwZ2FfMF9MRURzXzRCaXRfR1BJT19JTwo+ID4gPiA+
ID4+IFBPUlQgSVAySU5UQ19JcnB0ID0gTEVEc180Qml0X0lQMklOVENfSXJwdAo+ID4gPiA+ID4+
IEVORAo+ID4gPiA+ID4+Cj4gPiA+ID4gPj4gQkVHSU4geHBzX2lpYwo+ID4gPiA+ID4+IFBBUkFN
RVRFUiBJTlNUQU5DRSA9IElJQ19FRVBST00KPiA+ID4gPiA+PiBQQVJBTUVURVIgSFdfVkVSID0g
Mi4wMC5hCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfQ0xLX0ZSRVEgPSAxMDAwMDAwMDAKPiA+ID4g
PiA+PiBQQVJBTUVURVIgQ19JSUNfRlJFUSA9IDEwMDAwMAo+ID4gPiA+ID4+IFBBUkFNRVRFUiBD
X1RFTl9CSVRfQURSID0gMAo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0JBU0VBRERSID0gMHg4MTYw
MDAwMAo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0hJR0hBRERSID0gMHg4MTYwZmZmZgo+ID4gPiA+
ID4+IEJVU19JTlRFUkZBQ0UgU1BMQiA9IHBsYgo+ID4gPiA+ID4+IFBPUlQgU2NsID0gZnBnYV8w
X0lJQ19FRVBST01fU2NsCj4gPiA+ID4gPj4gUE9SVCBTZGEgPSBmcGdhXzBfSUlDX0VFUFJPTV9T
ZGEKPiA+ID4gPiA+PiBQT1JUIElJQzJJTlRDX0lycHQgPSBJSUNfRUVQUk9NX0lJQzJJTlRDX0ly
cHQKPiA+ID4gPiA+PiBFTkQKPiA+ID4gPiA+Pgo+ID4gPiA+ID4+IEJFR0lOIHhwc19zeXNhY2UK
PiA+ID4gPiA+PiBQQVJBTUVURVIgSU5TVEFOQ0UgPSBTeXNBQ0VfQ29tcGFjdEZsYXNoCj4gPiA+
ID4gPj4gUEFSQU1FVEVSIEhXX1ZFUiA9IDEuMDAuYQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX01F
TV9XSURUSCA9IDE2Cj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfQkFTRUFERFIgPSAweDgzNjAwMDAw
Cj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfSElHSEFERFIgPSAweDgzNjBmZmZmCj4gPiA+ID4gPj4g
QlVTX0lOVEVSRkFDRSBTUExCID0gcGxiCj4gPiA+ID4gPj4gUE9SVCBTeXNBQ0VfQ0xLID0gZnBn
YV8wX1N5c0FDRV9Db21wYWN0Rmxhc2hfU3lzQUNFX0NMSwo+ID4gPiA+ID4+IFBPUlQgU3lzQUNF
X01QQSA9IGZwZ2FfMF9TeXNBQ0VfQ29tcGFjdEZsYXNoX1N5c0FDRV9NUEFfc3BsaXQKPiA+ID4g
PiA+PiBQT1JUIFN5c0FDRV9NUEQgPSBmcGdhXzBfU3lzQUNFX0NvbXBhY3RGbGFzaF9TeXNBQ0Vf
TVBECj4gPiA+ID4gPj4gUE9SVCBTeXNBQ0VfQ0VOID0gZnBnYV8wX1N5c0FDRV9Db21wYWN0Rmxh
c2hfU3lzQUNFX0NFTgo+ID4gPiA+ID4+IFBPUlQgU3lzQUNFX09FTiA9IGZwZ2FfMF9TeXNBQ0Vf
Q29tcGFjdEZsYXNoX1N5c0FDRV9PRU4KPiA+ID4gPiA+PiBQT1JUIFN5c0FDRV9XRU4gPSBmcGdh
XzBfU3lzQUNFX0NvbXBhY3RGbGFzaF9TeXNBQ0VfV0VOCj4gPiA+ID4gPj4gUE9SVCBTeXNBQ0Vf
TVBJUlEgPSBmcGdhXzBfU3lzQUNFX0NvbXBhY3RGbGFzaF9TeXNBQ0VfTVBJUlEKPiA+ID4gPiA+
PiBQT1JUIFN5c0FDRV9JUlEgPSBTeXNBQ0VfQ29tcGFjdEZsYXNoX1N5c0FDRV9JUlEKPiA+ID4g
PiA+PiBFTkQKPiA+ID4gPiA+Pgo+ID4gPiA+ID4+IEJFR0lOIG1wbWMKPiA+ID4gPiA+PiBQQVJB
TUVURVIgSU5TVEFOQ0UgPSBERFJfU0RSQU0KPiA+ID4gPiA+PiBQQVJBTUVURVIgSFdfVkVSID0g
NC4wMC5hCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfTlVNX1BPUlRTID0gMwo+ID4gPiA+ID4+IFBB
UkFNRVRFUiBDX01FTV9QQVJUTk8gPSBIWUIyNUQ1MTIxNjBCRS01Cj4gPiA+ID4gPj4gUEFSQU1F
VEVSIENfTUVNX0RBVEFfV0lEVEggPSAzMgo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX01FTV9EUVNf
V0lEVEggPSA0Cj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfTUVNX0RNX1dJRFRIID0gNAo+ID4gPiA+
ID4+IFBBUkFNRVRFUiBDX01FTV9UWVBFID0gRERSCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfTlVN
X0lERUxBWUNUUkwgPSAyCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfSURFTEFZQ1RSTF9MT0MgPSBJ
REVMQVlDVFJMX1gwWTMtSURFTEFZQ1RSTF9YMFkyCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfUElN
MF9CQVNFVFlQRSA9IDIKPiA+ID4gPiA+PiBQQVJBTUVURVIgQ19QSU0xX0JBU0VUWVBFID0gMgo+
ID4gPiA+ID4+IFBBUkFNRVRFUiBDX1BJTTJfQkFTRVRZUEUgPSAzCj4gPiA+ID4gPj4gUEFSQU1F
VEVSIENfTVBNQ19DTEswX1BFUklPRF9QUyA9IDEwMDAwCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENf
U0RNQTJfUEkyTExfQ0xLX1JBVElPID0gMQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX01QTUNfQkFT
RUFERFIgPSAweDAwMDAwMDAwCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfTVBNQ19ISUdIQUREUiA9
IDB4MDdmZmZmZmYKPiA+ID4gPiA+PiBQQVJBTUVURVIgQ19TRE1BX0NUUkxfQkFTRUFERFIgPSAw
eDg0NjAwMDAwCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfU0RNQV9DVFJMX0hJR0hBRERSID0gMHg4
NDYwZmZmZgo+ID4gPiA+ID4+IEJVU19JTlRFUkZBQ0UgU1BMQjAgPSBwcGM0MDVfMF9pcGxiMQo+
ID4gPiA+ID4+IEJVU19JTlRFUkZBQ0UgU1BMQjEgPSBwcGM0MDVfMF9kcGxiMQo+ID4gPiA+ID4+
IEJVU19JTlRFUkZBQ0UgU0RNQV9MTDIgPSBUcmlNb2RlX01BQ19HTUlJX0xMSU5LMAo+ID4gPiA+
ID4+IEJVU19JTlRFUkZBQ0UgU0RNQV9DVFJMMiA9IHBsYgo+ID4gPiA+ID4+IFBPUlQgRERSX0Fk
ZHIgPSBmcGdhXzBfRERSX1NEUkFNX0REUl9BZGRyCj4gPiA+ID4gPj4gUE9SVCBERFJfQmFua0Fk
ZHIgPSBmcGdhXzBfRERSX1NEUkFNX0REUl9CYW5rQWRkcgo+ID4gPiA+ID4+IFBPUlQgRERSX0NB
U19uID0gZnBnYV8wX0REUl9TRFJBTV9ERFJfQ0FTX24KPiA+ID4gPiA+PiBQT1JUIEREUl9DRSA9
IGZwZ2FfMF9ERFJfU0RSQU1fRERSX0NFCj4gPiA+ID4gPj4gUE9SVCBERFJfQ1NfbiA9IGZwZ2Ff
MF9ERFJfU0RSQU1fRERSX0NTX24KPiA+ID4gPiA+PiBQT1JUIEREUl9SQVNfbiA9IGZwZ2FfMF9E
RFJfU0RSQU1fRERSX1JBU19uCj4gPiA+ID4gPj4gUE9SVCBERFJfV0VfbiA9IGZwZ2FfMF9ERFJf
U0RSQU1fRERSX1dFX24KPiA+ID4gPiA+PiBQT1JUIEREUl9ETSA9IGZwZ2FfMF9ERFJfU0RSQU1f
RERSX0RNCj4gPiA+ID4gPj4gUE9SVCBERFJfRFFTID0gZnBnYV8wX0REUl9TRFJBTV9ERFJfRFFT
Cj4gPiA+ID4gPj4gUE9SVCBERFJfRFEgPSBmcGdhXzBfRERSX1NEUkFNX0REUl9EUQo+ID4gPiA+
ID4+IFBPUlQgRERSX0NsayA9IGZwZ2FfMF9ERFJfU0RSQU1fRERSX0Nsawo+ID4gPiA+ID4+IFBP
UlQgRERSX0Nsa19uID0gZnBnYV8wX0REUl9TRFJBTV9ERFJfQ2xrX24KPiA+ID4gPiA+PiBQT1JU
IE1QTUNfQ2xrMCA9IHN5c19jbGtfcwo+ID4gPiA+ID4+IFBPUlQgTVBNQ19DbGs5MCA9IEREUl9T
RFJBTV9tcG1jX2Nsa185MF9zCj4gPiA+ID4gPj4gUE9SVCBTRE1BMl9DbGsgPSBzeXNfY2xrX3MK
PiA+ID4gPiA+PiBQT1JUIE1QTUNfQ2xrXzIwME1IeiA9IGNsa18yMDBtaHpfcwo+ID4gPiA+ID4+
IFBPUlQgTVBNQ19Sc3QgPSBzeXNfcGVyaXBoX3Jlc2V0Cj4gPiA+ID4gPj4gUE9SVCBTRE1BMl9S
eF9JbnRPdXQgPSBERFJfU0RSQU1fU0RNQTJfUnhfSW50T3V0Cj4gPiA+ID4gPj4gUE9SVCBTRE1B
Ml9UeF9JbnRPdXQgPSBERFJfU0RSQU1fU0RNQTJfVHhfSW50T3V0Cj4gPiA+ID4gPj4gRU5ECj4g
PiA+ID4gPj4KPiA+ID4gPiA+PiBCRUdJTiB4cHNfbGxfdGVtYWMKPiA+ID4gPiA+PiBQQVJBTUVU
RVIgSU5TVEFOQ0UgPSBUcmlNb2RlX01BQ19HTUlJCj4gPiA+ID4gPj4gUEFSQU1FVEVSIEhXX1ZF
UiA9IDEuMDEuYQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX1NQTEJfQ0xLX1BFUklPRF9QUyA9IDEw
MDAwCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfUEhZX1RZUEUgPSAxCj4gPiA+ID4gPj4gUEFSQU1F
VEVSIENfTlVNX0lERUxBWUNUUkwgPSA0Cj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfSURFTEFZQ1RS
TF9MT0MgPSBJREVMQVlDVFJMX1gxWTEtSURFTEFZQ1RSTF9YMVkzLQo+ID4gPiA+IElERUxBWUNU
UkxfWDJZMi1JREVMQVlDVFJMX1gyWTMKPiA+ID4gPiA+PiBQQVJBTUVURVIgQ19URU1BQ19UWVBF
ID0gMQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0JVUzJDT1JFX0NMS19SQVRJTyA9IDEKPiA+ID4g
PiA+PiBQQVJBTUVURVIgQ19CQVNFQUREUiA9IDB4ODFjMDAwMDAKPiA+ID4gPiA+PiBQQVJBTUVU
RVIgQ19ISUdIQUREUiA9IDB4ODFjMGZmZmYKPiA+ID4gPiA+PiBCVVNfSU5URVJGQUNFIFNQTEIg
PSBwbGIKPiA+ID4gPiA+PiBCVVNfSU5URVJGQUNFIExMSU5LMCA9IFRyaU1vZGVfTUFDX0dNSUlf
TExJTkswCj4gPiA+ID4gPj4gUE9SVCBHTUlJX1RYRF8wID0gZnBnYV8wX1RyaU1vZGVfTUFDX0dN
SUlfR01JSV9UWERfMAo+ID4gPiA+ID4+IFBPUlQgR01JSV9UWF9FTl8wID0gZnBnYV8wX1RyaU1v
ZGVfTUFDX0dNSUlfR01JSV9UWF9FTl8wCj4gPiA+ID4gPj4gUE9SVCBHTUlJX1RYX0VSXzAgPSBm
cGdhXzBfVHJpTW9kZV9NQUNfR01JSV9HTUlJX1RYX0VSXzAKPiA+ID4gPiA+PiBQT1JUIEdNSUlf
VFhfQ0xLXzAgPSBmcGdhXzBfVHJpTW9kZV9NQUNfR01JSV9HTUlJX1RYX0NMS18wCj4gPiA+ID4g
Pj4gUE9SVCBHTUlJX1JYRF8wID0gZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlfR01JSV9SWERfMAo+
ID4gPiA+ID4+IFBPUlQgR01JSV9SWF9EVl8wID0gZnBnYV8wX1RyaU1vZGVfTUFDX0dNSUlfR01J
SV9SWF9EVl8wCj4gPiA+ID4gPj4gUE9SVCBHTUlJX1JYX0VSXzAgPSBmcGdhXzBfVHJpTW9kZV9N
QUNfR01JSV9HTUlJX1JYX0VSXzAKPiA+ID4gPiA+PiBQT1JUIEdNSUlfUlhfQ0xLXzAgPSBmcGdh
XzBfVHJpTW9kZV9NQUNfR01JSV9HTUlJX1JYX0NMS18wCj4gPiA+ID4gPj4gUE9SVCBNSUlfVFhf
Q0xLXzAgPSBmcGdhXzBfVHJpTW9kZV9NQUNfR01JSV9NSUlfVFhfQ0xLXzAKPiA+ID4gPiA+PiBQ
T1JUIE1ESU9fMCA9IGZwZ2FfMF9UcmlNb2RlX01BQ19HTUlJX01ESU9fMAo+ID4gPiA+ID4+IFBP
UlQgTURDXzAgPSBmcGdhXzBfVHJpTW9kZV9NQUNfR01JSV9NRENfMAo+ID4gPiA+ID4+IFBPUlQg
VGVtYWNQaHlfUlNUX24gPSBmcGdhXzBfVHJpTW9kZV9NQUNfR01JSV9UZW1hY1BoeV9SU1Rfbgo+
ID4gPiA+ID4+IFBPUlQgR1RYX0NMS18wID0gdGVtYWNfY2xrX3MKPiA+ID4gPiA+PiBQT1JUIFJF
RkNMSyA9IGNsa18yMDBtaHpfcwo+ID4gPiA+ID4+IFBPUlQgTGxpbmtUZW1hYzBfQ0xLID0gc3lz
X2Nsa19zCj4gPiA+ID4gPj4gUE9SVCBUZW1hY0ludGMwX0lycHQgPSBUcmlNb2RlX01BQ19HTUlJ
X1RlbWFjSW50YzBfSXJwdAo+ID4gPiA+ID4+IEVORAo+ID4gPiA+ID4+Cj4gPiA+ID4gPj4gQkVH
SU4gdXRpbF9idXNfc3BsaXQKPiA+ID4gPiA+PiBQQVJBTUVURVIgSU5TVEFOQ0UgPSBTeXNBQ0Vf
Q29tcGFjdEZsYXNoX3V0aWxfYnVzX3NwbGl0XzAKPiA+ID4gPiA+PiBQQVJBTUVURVIgSFdfVkVS
ID0gMS4wMC5hCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfU0laRV9JTiA9IDcKPiA+ID4gPiA+PiBQ
QVJBTUVURVIgQ19MRUZUX1BPUyA9IDAKPiA+ID4gPiA+PiBQQVJBTUVURVIgQ19TUExJVCA9IDYK
PiA+ID4gPiA+PiBQT1JUIFNpZyA9IGZwZ2FfMF9TeXNBQ0VfQ29tcGFjdEZsYXNoX1N5c0FDRV9N
UEFfc3BsaXQKPiA+ID4gPiA+PiBQT1JUIE91dDEgPSBmcGdhXzBfU3lzQUNFX0NvbXBhY3RGbGFz
aF9TeXNBQ0VfTVBBCj4gPiA+ID4gPj4gRU5ECj4gPiA+ID4gPj4KPiA+ID4gPiA+PiBCRUdJTiBw
bGJfdjQ2Cj4gPiA+ID4gPj4gUEFSQU1FVEVSIElOU1RBTkNFID0gcHBjNDA1XzBfaXBsYjEKPiA+
ID4gPiA+PiBQQVJBTUVURVIgSFdfVkVSID0gMS4wMi5hCj4gPiA+ID4gPj4gUE9SVCBQTEJfQ2xr
ID0gc3lzX2Nsa19zCj4gPiA+ID4gPj4gUE9SVCBTWVNfUnN0ID0gc3lzX2J1c19yZXNldAo+ID4g
PiA+ID4+IEVORAo+ID4gPiA+ID4+Cj4gPiA+ID4gPj4gQkVHSU4gcGxiX3Y0Ngo+ID4gPiA+ID4+
IFBBUkFNRVRFUiBJTlNUQU5DRSA9IHBwYzQwNV8wX2RwbGIxCj4gPiA+ID4gPj4gUEFSQU1FVEVS
IEhXX1ZFUiA9IDEuMDIuYQo+ID4gPiA+ID4+IFBPUlQgUExCX0NsayA9IHN5c19jbGtfcwo+ID4g
PiA+ID4+IFBPUlQgU1lTX1JzdCA9IHN5c19idXNfcmVzZXQKPiA+ID4gPiA+PiBFTkQKPiA+ID4g
PiA+Pgo+ID4gPiA+ID4+IEJFR0lOIGNsb2NrX2dlbmVyYXRvcgo+ID4gPiA+ID4+IFBBUkFNRVRF
UiBJTlNUQU5DRSA9IGNsb2NrX2dlbmVyYXRvcl8wCj4gPiA+ID4gPj4gUEFSQU1FVEVSIEhXX1ZF
UiA9IDIuMDAuYQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0VYVF9SRVNFVF9ISUdIID0gMQo+ID4g
PiA+ID4+IFBBUkFNRVRFUiBDX0NMS0lOX0ZSRVEgPSAxMDAwMDAwMDAKPiA+ID4gPiA+PiBQQVJB
TUVURVIgQ19DTEtPVVQwX0ZSRVEgPSAxMDAwMDAwMDAKPiA+ID4gPiA+PiBQQVJBTUVURVIgQ19D
TEtPVVQwX0JVRiA9IFRSVUUKPiA+ID4gPiA+PiBQQVJBTUVURVIgQ19DTEtPVVQwX1BIQVNFID0g
MAo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0NMS09VVDBfR1JPVVAgPSBEQ00wCj4gPiA+ID4gPj4g
UEFSQU1FVEVSIENfQ0xLT1VUMV9GUkVRID0gMTAwMDAwMDAwCj4gPiA+ID4gPj4gUEFSQU1FVEVS
IENfQ0xLT1VUMV9CVUYgPSBUUlVFCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfQ0xLT1VUMV9QSEFT
RSA9IDkwCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfQ0xLT1VUMV9HUk9VUCA9IERDTTAKPiA+ID4g
PiA+PiBQQVJBTUVURVIgQ19DTEtPVVQyX0ZSRVEgPSAzMDAwMDAwMDAKPiA+ID4gPiA+PiBQQVJB
TUVURVIgQ19DTEtPVVQyX0JVRiA9IFRSVUUKPiA+ID4gPiA+PiBQQVJBTUVURVIgQ19DTEtPVVQy
X1BIQVNFID0gMAo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0NMS09VVDJfR1JPVVAgPSBEQ00wCj4g
PiA+ID4gPj4gUEFSQU1FVEVSIENfQ0xLT1VUM19GUkVRID0gMjAwMDAwMDAwCj4gPiA+ID4gPj4g
UEFSQU1FVEVSIENfQ0xLT1VUM19CVUYgPSBUUlVFCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfQ0xL
T1VUM19QSEFTRSA9IDAKPiA+ID4gPiA+PiBQQVJBTUVURVIgQ19DTEtPVVQzX0dST1VQID0gTk9O
RQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBDX0NMS09VVDRfRlJFUSA9IDEyNTAwMDAwMAo+ID4gPiA+
ID4+IFBBUkFNRVRFUiBDX0NMS09VVDRfQlVGID0gVFJVRQo+ID4gPiA+ID4+IFBBUkFNRVRFUiBD
X0NMS09VVDRfUEhBU0UgPSAwCj4gPiA+ID4gPj4gUEFSQU1FVEVSIENfQ0xLT1VUNF9HUk9VUCA9
IE5PTkUKPiA+ID4gPiA+PiBQT1JUIENMS09VVDAgPSBzeXNfY2xrX3MKPiA+ID4gPiA+PiBQT1JU
IENMS09VVDEgPSBERFJfU0RSQU1fbXBtY19jbGtfOTBfcwo+ID4gPiA+ID4+IFBPUlQgQ0xLT1VU
MiA9IHByb2NfY2xrX3MKPiA+ID4gPiA+PiBQT1JUIENMS09VVDMgPSBjbGtfMjAwbWh6X3MKPiA+
ID4gPiA+PiBQT1JUIENMS09VVDQgPSB0ZW1hY19jbGtfcwo+ID4gPiA+ID4+IFBPUlQgQ0xLSU4g
PSBkY21fY2xrX3MKPiA+ID4gPiA+PiBQT1JUIExPQ0tFRCA9IERjbV9hbGxfbG9ja2VkCj4gPiA+
ID4gPj4gUE9SVCBSU1QgPSBuZXRfZ25kCj4gPiA+ID4gPj4gRU5ECj4gPiA+ID4gPj4KPiA+ID4g
PiA+PiBCRUdJTiBwcm9jX3N5c19yZXNldAo+ID4gPiA+ID4+IFBBUkFNRVRFUiBJTlNUQU5DRSA9
IHByb2Nfc3lzX3Jlc2V0XzAKPiA+ID4gPiA+PiBQQVJBTUVURVIgSFdfVkVSID0gMi4wMC5hCj4g
PiA+ID4gPj4gUEFSQU1FVEVSIENfRVhUX1JFU0VUX0hJR0ggPSAwCj4gPiA+ID4gPj4gQlVTX0lO
VEVSRkFDRSBSRVNFVFBQQzAgPSBwcGNfcmVzZXRfYnVzCj4gPiA+ID4gPj4gUE9SVCBTbG93ZXN0
X3N5bmNfY2xrID0gc3lzX2Nsa19zCj4gPiA+ID4gPj4gUE9SVCBEY21fbG9ja2VkID0gRGNtX2Fs
bF9sb2NrZWQKPiA+ID4gPiA+PiBQT1JUIEV4dF9SZXNldF9JbiA9IHN5c19yc3Rfcwo+ID4gPiA+
ID4+IFBPUlQgQnVzX1N0cnVjdF9SZXNldCA9IHN5c19idXNfcmVzZXQKPiA+ID4gPiA+PiBQT1JU
IFBlcmlwaGVyYWxfUmVzZXQgPSBzeXNfcGVyaXBoX3Jlc2V0Cj4gPiA+ID4gPj4gRU5ECj4gPiA+
ID4gPj4KPiA+ID4gPiA+PiBCRUdJTiB4cHNfaW50Ywo+ID4gPiA+ID4+IFBBUkFNRVRFUiBJTlNU
QU5DRSA9IHhwc19pbnRjXzAKPiA+ID4gPiA+PiBQQVJBTUVURVIgSFdfVkVSID0gMS4wMC5hCj4g
PiA+ID4gPj4gUEFSQU1FVEVSIENfQkFTRUFERFIgPSAweDgxODAwMDAwCj4gPiA+ID4gPj4gUEFS
QU1FVEVSIENfSElHSEFERFIgPSAweDgxODBmZmZmCj4gPiA+ID4gPj4gQlVTX0lOVEVSRkFDRSBT
UExCID0gcGxiCj4gPiA+ID4gPj4gUE9SVCBJcnEgPSBFSUNDNDA1RVhUSU5QVVRJUlEKPiA+ID4g
PiA+PiBQT1JUIEludHIgPSBSUzIzMl9VYXJ0X0lQMklOVENfSXJwdCAmIExFRHNfNEJpdF9JUDJJ
TlRDX0lycHQgJgo+ID4gPiA+IElJQ19FRVBST01fSUlDMklOVENfSXJwdCAmIFN5c0FDRV9Db21w
YWN0Rmxhc2hfU3lzQUNFX0lSUSAmCj4gPiA+ID4gVHJpTW9kZV9NQUNfR01JSV9UZW1hY0ludGMw
X0lycHQgJiBERFJfU0RSQU1fU0RNQTJfUnhfSW50T3V0ICYKPiA+ID4gPiBERFJfU0RSQU1fU0RN
QTJfVHhfSW50T3V0Cj4gPiA+ID4gPj4gRU5ECj4gPiA+ID4gPj4KPiA+ID4gPiA+Pgo+ID4gPiA+
ID4+Cj4gPiA+ID4gPj4gI2FkZHJlc3MtY2VsbHMgPSA8MT47Cj4gPiA+ID4gPj4gI3NpemUtY2Vs
bHMgPSA8MT47Cj4gPiA+ID4gPj4gY29tcGF0aWJsZSA9ICJ4bG54LHZpcnRleCI7Cj4gPiA+ID4g
Pj4gbW9kZWwgPSAidGVzdGluZyI7Cj4gPiA+ID4gPj4gRERSX1NEUkFNOiBtZW1vcnlAMCB7Cj4g
PiA+ID4gPj4gZGV2aWNlX3R5cGUgPSAibWVtb3J5IjsKPiA+ID4gPiA+PiByZWcgPSA8IDAgODAw
MDAwMCA+Owo+ID4gPiA+ID4+IH0gOwo+ID4gPiA+ID4+IGNob3NlbiB7Cj4gPiA+ID4gPj4gYm9v
dGFyZ3MgPSAiY29uc29sZT10dHlTMCw5NjAwIGlwPW9uCj4gPiA+ID4gbmZzcm9vdD0xNzIuMTYu
NDAuNzY6L3YycGNsaWVudHMvamhsMjYsdGNwIjsKPiA+ID4gPiA+PiBsaW51eCxzdGRvdXQtcGF0
aCA9ICIvcGxiQDAvc2VyaWFsQDgzZTAwMDAwIjsKPiA+ID4gPiA+PiB9IDsKPiA+ID4gPiA+PiBj
cHVzIHsKPiA+ID4gPiA+PiAjYWRkcmVzcy1jZWxscyA9IDwxPjsKPiA+ID4gPiA+PiAjY3B1cyA9
IDwxPjsKPiA+ID4gPiA+PiAjc2l6ZS1jZWxscyA9IDwwPjsKPiA+ID4gPiA+PiBwcGM0MDVfMDog
Y3B1QDAgewo+ID4gPiA+ID4+IGNsb2NrLWZyZXF1ZW5jeSA9IDwxMWUxYTMwMD47Cj4gPiA+ID4g
Pj4gY29tcGF0aWJsZSA9ICJQb3dlclBDLDQwNSIsICJpYm0scHBjNDA1IjsKPiA+ID4gPiA+PiBk
LWNhY2hlLWxpbmUtc2l6ZSA9IDwyMD47Cj4gPiA+ID4gPj4gZC1jYWNoZS1zaXplID0gPDQwMDA+
Owo+ID4gPiA+ID4+IGRldmljZV90eXBlID0gImNwdSI7Cj4gPiA+ID4gPj4gaS1jYWNoZS1saW5l
LXNpemUgPSA8MjA+Owo+ID4gPiA+ID4+IGktY2FjaGUtc2l6ZSA9IDw0MDAwPjsKPiA+ID4gPiA+
PiBtb2RlbCA9ICJQb3dlclBDLDQwNSI7Cj4gPiA+ID4gPj4gcmVnID0gPDA+Owo+ID4gPiA+ID4+
IHRpbWViYXNlLWZyZXF1ZW5jeSA9IDwxMWUxYTMwMD47Cj4gPiA+ID4gPj4geGxueCxhcHUtY29u
dHJvbCA9IDxkZTAwPjsKPiA+ID4gPiA+PiB4bG54LGFwdS11ZGktMSA9IDxhMTg5ODM+Owo+ID4g
PiA+ID4+IHhsbngsYXB1LXVkaS0yID0gPGEzODk4Mz47Cj4gPiA+ID4gPj4geGxueCxhcHUtdWRp
LTMgPSA8YTU4OWMzPjsKPiA+ID4gPiA+PiB4bG54LGFwdS11ZGktNCA9IDxhNzg5YzM+Owo+ID4g
PiA+ID4+IHhsbngsYXB1LXVkaS01ID0gPGE5OGMwMz47Cj4gPiA+ID4gPj4geGxueCxhcHUtdWRp
LTYgPSA8YWI4YzAzPjsKPiA+ID4gPiA+PiB4bG54LGFwdS11ZGktNyA9IDxhZDhjNDM+Owo+ID4g
PiA+ID4+IHhsbngsYXB1LXVkaS04ID0gPGFmOGM0Mz47Cj4gPiA+ID4gPj4geGxueCxkZXRlcm1p
bmlzdGljLW11bHQgPSA8MD47Cj4gPiA+ID4gPj4geGxueCxkaXNhYmxlLW9wZXJhbmQtZm9yd2Fy
ZGluZyA9IDwxPjsKPiA+ID4gPiA+PiB4bG54LGZhc3Rlc3QtcGxiLWNsb2NrID0gIkRQTEIwIjsK
PiA+ID4gPiA+PiB4bG54LGdlbmVyYXRlLXBsYi10aW1lc3BlY3MgPSA8MT47Cj4gPiA+ID4gPj4g
eGxueCxtbXUtZW5hYmxlID0gPDE+Owo+ID4gPiA+ID4+IHhsbngscHZyLWhpZ2ggPSA8MD47Cj4g
PiA+ID4gPj4geGxueCxwdnItbG93ID0gPDA+Owo+ID4gPiA+ID4+IH0gOwo+ID4gPiA+ID4+IH0g
Owo+ID4gPiA+ID4+IHBsYjogcGxiQDAgewo+ID4gPiA+ID4+ICNhZGRyZXNzLWNlbGxzID0gPDE+
Owo+ID4gPiA+ID4+ICNzaXplLWNlbGxzID0gPDE+Owo+ID4gPiA+ID4+IGNvbXBhdGlibGUgPSAi
eGxueCxwbGItdjQ2LTEuMDIuYSI7Cj4gPiA+ID4gPj4gcmFuZ2VzIDsKPiA+ID4gPiA+PiBJSUNf
RUVQUk9NOiBpMmNAODE2MDAwMDAgewo+ID4gPiA+ID4+IGNvbXBhdGlibGUgPSAieGxueCx4cHMt
aWljLTIuMDAuYSI7Cj4gPiA+ID4gPj4gaW50ZXJydXB0LXBhcmVudCA9IDwmeHBzX2ludGNfMD47
Cj4gPiA+ID4gPj4gaW50ZXJydXB0cyA9IDwgNCAyID47Cj4gPiA+ID4gPj4gcmVnID0gPCA4MTYw
MDAwMCAxMDAwMCA+Owo+ID4gPiA+ID4+IHhsbngsY2xrLWZyZXEgPSA8NWY1ZTEwMD47Cj4gPiA+
ID4gPj4geGxueCxmYW1pbHkgPSAidmlydGV4NCI7Cj4gPiA+ID4gPj4geGxueCxncG8td2lkdGgg
PSA8MT47Cj4gPiA+ID4gPj4geGxueCxpaWMtZnJlcSA9IDwxODZhMD47Cj4gPiA+ID4gPj4geGxu
eCxzY2wtaW5lcnRpYWwtZGVsYXkgPSA8MD47Cj4gPiA+ID4gPj4geGxueCxzZGEtaW5lcnRpYWwt
ZGVsYXkgPSA8MD47Cj4gPiA+ID4gPj4geGxueCx0ZW4tYml0LWFkciA9IDwwPjsKPiA+ID4gPiA+
PiB9IDsKPiA+ID4gPiA+PiBMRURzXzRCaXQ6IGdwaW9AODE0MDAwMDAgewo+ID4gPiA+ID4+IGNv
bXBhdGlibGUgPSAieGxueCx4cHMtZ3Bpby0xLjAwLmEiOwo+ID4gPiA+ID4+IGludGVycnVwdC1w
YXJlbnQgPSA8Jnhwc19pbnRjXzA+Owo+ID4gPiA+ID4+IGludGVycnVwdHMgPSA8IDUgMiA+Owo+
ID4gPiA+ID4+IHJlZyA9IDwgODE0MDAwMDAgMTAwMDAgPjsKPiA+ID4gPiA+PiB4bG54LGFsbC1p
bnB1dHMgPSA8MD47Cj4gPiA+ID4gPj4geGxueCxhbGwtaW5wdXRzLTIgPSA8MD47Cj4gPiA+ID4g
Pj4geGxueCxkb3V0LWRlZmF1bHQgPSA8MD47Cj4gPiA+ID4gPj4geGxueCxkb3V0LWRlZmF1bHQt
MiA9IDwwPjsKPiA+ID4gPiA+PiB4bG54LGZhbWlseSA9ICJ2aXJ0ZXg0IjsKPiA+ID4gPiA+PiB4
bG54LGdwaW8td2lkdGggPSA8ND47Cj4gPiA+ID4gPj4geGxueCxpbnRlcnJ1cHQtcHJlc2VudCA9
IDwxPjsKPiA+ID4gPiA+PiB4bG54LGlzLWJpZGlyID0gPDE+Owo+ID4gPiA+ID4+IHhsbngsaXMt
YmlkaXItMiA9IDwxPjsKPiA+ID4gPiA+PiB4bG54LGlzLWR1YWwgPSA8MD47Cj4gPiA+ID4gPj4g
eGxueCx0cmktZGVmYXVsdCA9IDxmZmZmZmZmZj47Cj4gPiA+ID4gPj4geGxueCx0cmktZGVmYXVs
dC0yID0gPGZmZmZmZmZmPjsKPiA+ID4gPiA+PiB9IDsKPiA+ID4gPiA+PiBSUzIzMl9VYXJ0OiBz
ZXJpYWxAODNlMDAwMDAgewo+ID4gPiA+ID4+IGNvbXBhdGlibGUgPSAieGxueCx4cHMtdWFydDE2
NTUwLTIuMDAuYSI7Cj4gPiA+ID4gPj4gLy8gY29tcGF0aWJsZSA9ICJuczE2NTUwIjsKPiA+ID4g
PiA+PiBkZXZpY2VfdHlwZSA9ICJzZXJpYWwiOwo+ID4gPiA+ID4+IGludGVycnVwdC1wYXJlbnQg
PSA8Jnhwc19pbnRjXzA+Owo+ID4gPiA+ID4+IGludGVycnVwdHMgPSA8IDYgMiA+Owo+ID4gPiA+
ID4+IHJlZyA9IDwgODNlMDAwMDAgMTAwMDAgPjsKPiA+ID4gPiA+PiBjdXJyZW50LXNwZWVkID0g
PGQjOTYwMD47Cj4gPiA+ID4gPj4gY2xvY2stZnJlcXVlbmN5ID0gPGQjMTAwMDAwMDAwPjsgLyog
YWRkZWQKPiA+ID4gPiBieSBqaGwgKi8KPiA+ID4gPiA+PiByZWctc2hpZnQgPSA8Mj47Cj4gPiA+
ID4gPj4geGxueCxmYW1pbHkgPSAidmlydGV4NCI7Cj4gPiA+ID4gPj4geGxueCxoYXMtZXh0ZXJu
YWwtcmNsayA9IDwwPjsKPiA+ID4gPiA+PiB4bG54LGhhcy1leHRlcm5hbC14aW4gPSA8MD47Cj4g
PiA+ID4gPj4geGxueCxpcy1hLTE2NTUwID0gPDE+Owo+ID4gPiA+ID4+IH0gOwo+ID4gPiA+ID4+
IFN5c0FDRV9Db21wYWN0Rmxhc2g6IHN5c2FjZUA4MzYwMDAwMCB7Cj4gPiA+ID4gPj4gY29tcGF0
aWJsZSA9ICJ4bG54LHhwcy1zeXNhY2UtMS4wMC5hIjsKPiA+ID4gPiA+PiBpbnRlcnJ1cHQtcGFy
ZW50ID0gPCZ4cHNfaW50Y18wPjsKPiA+ID4gPiA+PiBpbnRlcnJ1cHRzID0gPCAzIDIgPjsKPiA+
ID4gPiA+PiByZWcgPSA8IDgzNjAwMDAwIDEwMDAwID47Cj4gPiA+ID4gPj4geGxueCxmYW1pbHkg
PSAidmlydGV4NCI7Cj4gPiA+ID4gPj4geGxueCxtZW0td2lkdGggPSA8MTA+Owo+ID4gPiA+ID4+
IH0gOwo+ID4gPiA+ID4+IFRyaU1vZGVfTUFDX0dNSUk6IHhwcy1sbC10ZW1hY0A4MWMwMDAwMCB7
Cj4gPiA+ID4gPj4gI2FkZHJlc3MtY2VsbHMgPSA8MT47Cj4gPiA+ID4gPj4gI3NpemUtY2VsbHMg
PSA8MT47Cj4gPiA+ID4gPj4gY29tcGF0aWJsZSA9ICJ4bG54LGNvbXBvdW5kIjsKPiA+ID4gPiA+
PiBldGhlcm5ldEA4MWMwMDAwMCB7Cj4gPiA+ID4gPj4gY29tcGF0aWJsZSA9ICJ4bG54LHhwcy1s
bC10ZW1hYy0KPiA+ID4gPiAxLjAxLmEiOwo+ID4gPiA+ID4+IGRldmljZV90eXBlID0gIm5ldHdv
cmsiOwo+ID4gPiA+ID4+IGludGVycnVwdC1wYXJlbnQgPQo+ID4gPiA+IDwmeHBzX2ludGNfMD47
Cj4gPiA+ID4gPj4gaW50ZXJydXB0cyA9IDwgMiAyID47Cj4gPiA+ID4gPj4gbGxpbmstY29ubmVj
dGVkID0gPCZQSU0yPjsKPiA+ID4gPiA+PiBsb2NhbC1tYWMtYWRkcmVzcyA9IFsgMDIgMDAgMDAK
PiA+ID4gPiAwMCAwMCAwMSBdOwo+ID4gPiA+ID4+IHJlZyA9IDwgODFjMDAwMDAgNDAgPjsKPiA+
ID4gPiA+PiB4bG54LGJ1czJjb3JlLWNsay1yYXRpbyA9IDwxPjsKPiA+ID4gPiA+PiB4bG54LHBo
eS10eXBlID0gPDE+Owo+ID4gPiA+ID4+IHhsbngscGh5YWRkciA9IDwxPjsKPiA+ID4gPiA+PiB4
bG54LHJ4Y3N1bSA9IDwwPjsKPiA+ID4gPiA+PiB4bG54LHJ4ZmlmbyA9IDwxMDAwPjsKPiA+ID4g
PiA+PiB4bG54LHRlbWFjLXR5cGUgPSA8MT47Cj4gPiA+ID4gPj4geGxueCx0eGNzdW0gPSA8MD47
Cj4gPiA+ID4gPj4geGxueCx0eGZpZm8gPSA8MTAwMD47Cj4gPiA+ID4gPj4gfSA7Cj4gPiA+ID4g
Pj4gfSA7Cj4gPiA+ID4gPj4gbXBtY0AwIHsKPiA+ID4gPiA+PiAjYWRkcmVzcy1jZWxscyA9IDwx
PjsKPiA+ID4gPiA+PiAjc2l6ZS1jZWxscyA9IDwxPjsKPiA+ID4gPiA+PiBjb21wYXRpYmxlID0g
InhsbngsbXBtYy00LjAwLmEiOwo+ID4gPiA+ID4+IFBJTTI6IHNkbWFAODQ2MDAxMDAgewo+ID4g
PiA+ID4+IGNvbXBhdGlibGUgPSAieGxueCxsbC1kbWEtCj4gPiA+ID4gMS4wMC5hIjsKPiA+ID4g
PiA+PiBpbnRlcnJ1cHQtcGFyZW50ID0KPiA+ID4gPiA8Jnhwc19pbnRjXzA+Owo+ID4gPiA+ID4+
IGludGVycnVwdHMgPSA8IDEgMiAwIDIgPjsKPiA+ID4gPiA+PiByZWcgPSA8IDg0NjAwMTAwIDgw
ID47Cj4gPiA+ID4gPj4gfSA7Cj4gPiA+ID4gPj4gfSA7Cj4gPiA+ID4gPj4geHBzX2JyYW1faWZf
Y250bHJfMTogeHBzLWJyYW0taWYtY250bHJAZmZmZmUwMDAgewo+ID4gPiA+ID4+IGNvbXBhdGli
bGUgPSAieGxueCx4cHMtYnJhbS1pZi1jbnRsci0KPiA+ID4gPiAxLjAwLmEiOwo+ID4gPiA+ID4+
IHJlZyA9IDwgZmZmZmUwMDAgMjAwMCA+Owo+ID4gPiA+ID4+IHhsbngsZmFtaWx5ID0gInZpcnRl
eDQiOwo+ID4gPiA+ID4+IH0gOwo+ID4gPiA+ID4+IHhwc19pbnRjXzA6IGludGVycnVwdC1jb250
cm9sbGVyQDgxODAwMDAwIHsKPiA+ID4gPiA+PiAjaW50ZXJydXB0LWNlbGxzID0gPDI+Owo+ID4g
PiA+ID4+IGNvbXBhdGlibGUgPSAieGxueCx4cHMtaW50Yy0xLjAwLmEiOwo+ID4gPiA+ID4+IGlu
dGVycnVwdC1jb250cm9sbGVyIDsKPiA+ID4gPiA+PiByZWcgPSA8IDgxODAwMDAwIDEwMDAwID47
Cj4gPiA+ID4gPj4geGxueCxudW0taW50ci1pbnB1dHMgPSA8Nz47Cj4gPiA+ID4gPj4gfSA7Cj4g
PiA+ID4gPj4gfSA7Cj4gPiA+ID4gPj4gcHBjNDA1XzBfZHBsYjE6IHBsYkAxIHsKPiA+ID4gPiA+
PiAjYWRkcmVzcy1jZWxscyA9IDwxPjsKPiA+ID4gPiA+PiAjc2l6ZS1jZWxscyA9IDwxPjsKPiA+
ID4gPiA+PiBjb21wYXRpYmxlID0gInhsbngscGxiLXY0Ni0xLjAyLmEiOwo+ID4gPiA+ID4+IHJh
bmdlcyA7Cj4gPiA+ID4gPj4gfSA7Cj4gPiA+ID4gPj4gfSA7Cj4gPiA+ID4gPj4KPiA+ID4gPiA+
Pgo+ID4gPiA+ID4+Cj4gPiA+ID4gPj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0KPiA+ID4g
PiA+PiBGcm9tOiBNYWdudXMgSGpvcnRoIFttYWlsdG86bWhAb21uaXN5cy5zZV0KPiA+ID4gPiA+
PiBTZW50OiBTYXR1cmRheSwgTWFyY2ggMjksIDIwMDggNjo1NCBBTQo+ID4gPiA+ID4+IFRvOiBn
aXQKPiA+ID4gPiA+PiBDYzogbGludXhwcGMtZW1iZWRkZWRAb3psYWJzLm9yZwo+ID4gPiA+ID4+
IFN1YmplY3Q6IFhpbGlueCBMTFRFTUFDIGRyaXZlciBpc3N1ZXMKPiA+ID4gPiA+Pgo+ID4gPiA+
ID4+IEhpLAo+ID4gPiA+ID4+Cj4gPiA+ID4gPj4gSSdtIGhhdmluZyBzb21lIG5ldHdvcmtpbmcg
dHJvdWJsZXMgd2l0aCB0aGUgWGlsaW54IExMVEVNQUMgZHJpdmVyCj4gZnJvbQo+ID4gPiB0aGUK
PiA+ID4gPiA+PiBYaWxpbnggTGludXggZ2l0IHRyZWUgKHBvd2VycGMgYXJjaCkgb24gYW4gTUw0
MDMgYm9hcmQuIEVESzkuMlNQMiwKPiA+ID4gPiA+PiB4cHNfbGxfdGVtYWMgdjEuMDAuYgo+ID4g
PiA+ID4+Cj4gPiA+ID4gPj4gVGhlIHdlaXJkIHRoaW5nIGlzLCB0aGF0IGl0IHNvcnQgb2YgaGFs
ZiB3b3Jrcy4gSXQgc3VjY2Vzc2Z1bGx5Cj4gbWFrZXMgYQo+ID4gPiBESENQCj4gPiA+ID4gPj4g
cmVxdWVzdCBhbmQgZ2V0cyBpdHMgSVAgYWRkcmVzcy4gSSB0cmllZCBzZXR0aW5nIHVwIGEgdGZ0
cGQgc2VydmVyLAo+IGFuZAo+ID4gPiBJIGNhbgo+ID4gPiA+ID4+IHNlZSBVRFAgcmVxdWVzdHMg
Y29taW5nIGluIGJ1dCB0aGUgcmVzcG9uc2UgZG9lc24ndCBzZWVtIHRvIGNvbWUKPiBvdXQuIEkK
PiA+ID4gYWxzbwo+ID4gPiA+ID4+IHRyaWVkIHJ1bm5pbmcgYSBUQ1Agc2VydmVyIG9uIHRoZSBi
b2FyZCwgYW5kIGl0IGNhbiBzZWUgYW5kIGFjY2VwdAo+ID4gPiBpbmNvbWluZwo+ID4gPiA+ID4+
IGNvbm5lY3Rpb25zIGJ1dCBhZnRlciB0aGF0IG5vIGRhdGEgc2VlbXMgdG8gZ2V0IHRocm91Z2gu
IEkgY2FuIHBpbmcKPiBvdXQKPiA+ID4gYW5kCj4gPiA+ID4gPj4gZ2V0IGFyb3VuZCA0MCUgcGFj
a2V0IGxvc3MuCj4gPiA+ID4gPj4KPiA+ID4gPiA+PiBMb29raW5nIGF0IC9wcm9jL2ludGVycnVw
dHMsIEkgY2FuIHNlZSBib3RoIFR4RG1hIGludGVycnVwdHMgYW5kCj4gUnhEbWEKPiA+ID4gPiA+
PiBpbnRlcnJ1cHRzLiBObyBldGgwIGludGVycnVwdHMgYnV0IHRoYXQgc2VlbXMgdG8gYmUgT0sg
anVkZ2luZyBieQo+IHRoZQo+ID4gPiBkcml2ZXIKPiA+ID4gPiA+PiBzb3VyY2UgY29tbWVudHMu
IElmY29uZmlnIHNob3dzIG5vIGNvbGxpc3Rpb25zLCBubyBkcm9wcGVkIHBhY2tldHMsCj4gbm8K
PiA+ID4gPiBlcnJvcnMsCj4gPiA+ID4gPj4gc28gdGhlIHN5c3RlbSBzZWVtcyB0byB0aGluayB0
aGF0IGV2ZXJ5dGhpbmcgaXMgT0suCj4gPiA+ID4gPj4KPiA+ID4gPiA+PiBDbHVlcyBhbnlvbmU/
IEknbSBzdGFydGluZyB0byBydW4gb3V0IG9mIGlkZWFzLi4uCj4gPiA+ID4gPj4KPiA+ID4gPiA+
PiBCZXN0IHJlZ2FyZHMsCj4gPiA+ID4gPj4gTWFnbnVzCj4gPiA+ID4gPj4KPiA+ID4gPiA+Pgo+
ID4gPiA+ID4+IC0tCj4gPiA+ID4gPj4KPiA+ID4gPiA+PiBNYWdudXMgSGpvcnRoLCBNLlNjLgo+
ID4gPiA+ID4+IE9tbmlzeXMgSW5zdHJ1bWVudHMgQUIKPiA+ID4gPiA+PiBHcnV2Z2F0YW4gOAo+
ID4gPiA+ID4+IFNFLTQyMSAzMCBWw6RzdHJhIEZyw7ZsdW5kYSwgU1dFREVOCj4gPiA+ID4gPj4g
UGhvbmU6ICs0NiAzMSA3MzQgMzQgMDkKPiA+ID4gPiA+PiBGYXg6ICs0NiAzMSA3MzQgMzQgMjkK
PiA+ID4gPiA+PiBodHRwOi8vd3d3Lm9tbmlzeXMuc2UKPiA+ID4gPiA+Pgo+ID4gPiA+ID4KPiA+
ID4gPiA+IF9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4g
PiA+ID4gPiBMaW51eHBwYy1lbWJlZGRlZCBtYWlsaW5nIGxpc3QKPiA+ID4gPiA+IExpbnV4cHBj
LWVtYmVkZGVkQG96bGFicy5vcmcKPiA+ID4gPiA+IGh0dHBzOi8vb3psYWJzLm9yZy9tYWlsbWFu
L2xpc3RpbmZvL2xpbnV4cHBjLWVtYmVkZGVkCj4gPiA+IF9fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fCj4gPiA+IExpbnV4cHBjLWVtYmVkZGVkIG1haWxpbmcg
bGlzdAo+ID4gPiBMaW51eHBwYy1lbWJlZGRlZEBvemxhYnMub3JnCj4gPiA+IGh0dHBzOi8vb3ps
YWJzLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4cHBjLWVtYmVkZGVkCj4gPiA+Cj4gPiA+Cj4g
PiA+IC0tCj4gPiA+IEpvaGFubiBCYXVkeQo+ID4gPiBqb2hhYWhuQGdtYWlsLmNvbQo+ID4gPiBf
X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwo+ID4gPiDnlKggV2luZG93cyBMaXZlIFNw
YWNlcyDlsZXnpLrkuKrmgKfoh6rmiJHvvIzkuI7lpb3lj4vliIbkuqvnlJ/mtLvvvIEg5LqG6Kej
5pu05aSa5L+h5oGv77yBCj4gPgo+ID4KPiA+Cj4gPiAtLQo+ID4gSm9oYW5uIEJhdWR5Cj4gPiBq
b2hhYWhuQGdtYWlsLmNvbQo+Cj4KPiBfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwo+
IOeUqCBXaW5kb3dzIExpdmUgU3BhY2VzIOWxleekuuS4quaAp+iHquaIke+8jOS4juWlveWPi+WI
huS6q+eUn+a0u++8gSDkuobop6Pmm7TlpJrkv6Hmga/vvIEKCgoKLS0gCkpvaGFubiBCYXVkeQpq
b2hhYWhuQGdtYWlsLmNvbQo=

Xilinx LLTEMAC driver issues

[Magnus Hjorth]

Hi,

I'm having some networking troubles with the Xilinx LLTEMAC driver from =
the
Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
xps_ll_temac v1.00.b=20

The weird thing is, that it sort of half works. It successfully makes a =
DHCP
request and gets its IP address. I tried setting up a tftpd server, and =
I can
see UDP requests coming in but the response doesn't seem to come out. I =
also
tried running a TCP server on the board, and it can see and accept =
incoming
connections but after that no data seems to get through. I can ping out =
and
get around 40% packet loss.

Looking at /proc/interrupts, I can see both TxDma interrupts and RxDma
interrupts. No eth0 interrupts but that seems to be OK judging by the =
driver
source comments. Ifconfig shows no collistions, no dropped packets, no =
errors,
so the system seems to think that everything is OK.=20

Clues anyone? I'm starting to run out of ideas...

Best regards,
Magnus


--

Magnus Hjorth, M.Sc.
Omnisys Instruments AB
Gruvgatan 8
SE-421 30  V=E4stra Fr=F6lunda, SWEDEN
Phone: +46 31 734 34 09
Fax: +46 31 734 34 29
http://www.omnisys.se