* [PATCH 1/6] powerpc/85xx: clean up for mpc8568_mds name @ 2009-04-29 18:14 Haiying Wang 2009-04-29 18:14 ` [PATCH 2/6] powerpc/qe: update risc allocation for QE Haiying Wang 2009-04-30 11:37 ` [PATCH 1/6] powerpc/85xx: clean up for mpc8568_mds name Kumar Gala 0 siblings, 2 replies; 13+ messages in thread From: Haiying Wang @ 2009-04-29 18:14 UTC (permalink / raw) To: linuxppc-dev, galak; +Cc: Haiying Wang Keep an unique machine def for the MPC8568 MDS board to handle some subtle differences between the future MDS board. Also set the bcsrs in setup_arch() only for mpc8568_mds because other mds has different bcsr settings. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> --- arch/powerpc/platforms/85xx/mpc85xx_mds.c | 29 +++++++++++++++-------------- 1 files changed, 15 insertions(+), 14 deletions(-) diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 7dd0290..d34d29a 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -206,23 +206,24 @@ static void __init mpc85xx_mds_setup_arch(void) } if (bcsr_regs) { + if (machine_is(mpc8568_mds)) { #define BCSR_UCC1_GETH_EN (0x1 << 7) #define BCSR_UCC2_GETH_EN (0x1 << 7) #define BCSR_UCC1_MODE_MSK (0x3 << 4) #define BCSR_UCC2_MODE_MSK (0x3 << 0) - /* Turn off UCC1 & UCC2 */ - clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); - clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); + /* Turn off UCC1 & UCC2 */ + clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); + clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); - /* Mode is RGMII, all bits clear */ - clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK | - BCSR_UCC2_MODE_MSK); - - /* Turn UCC1 & UCC2 on */ - setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); - setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); + /* Mode is RGMII, all bits clear */ + clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK | + BCSR_UCC2_MODE_MSK); + /* Turn UCC1 & UCC2 on */ + setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN); + setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN); + } iounmap(bcsr_regs); } #endif /* CONFIG_QUICC_ENGINE */ @@ -257,7 +258,7 @@ static int __init board_fixups(void) return 0; } -machine_arch_initcall(mpc85xx_mds, board_fixups); +machine_arch_initcall(mpc8568_mds, board_fixups); static struct of_device_id mpc85xx_ids[] = { { .type = "soc", }, @@ -276,7 +277,7 @@ static int __init mpc85xx_publish_devices(void) return 0; } -machine_device_initcall(mpc85xx_mds, mpc85xx_publish_devices); +machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); static void __init mpc85xx_mds_pic_init(void) { @@ -321,8 +322,8 @@ static int __init mpc85xx_mds_probe(void) return of_flat_dt_is_compatible(root, "MPC85xxMDS"); } -define_machine(mpc85xx_mds) { - .name = "MPC85xx MDS", +define_machine(mpc8568_mds) { + .name = "MPC8568 MDS", .probe = mpc85xx_mds_probe, .setup_arch = mpc85xx_mds_setup_arch, .init_IRQ = mpc85xx_mds_pic_init, -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/6] powerpc/qe: update risc allocation for QE 2009-04-29 18:14 [PATCH 1/6] powerpc/85xx: clean up for mpc8568_mds name Haiying Wang @ 2009-04-29 18:14 ` Haiying Wang 2009-04-29 18:14 ` [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth Haiying Wang ` (2 more replies) 2009-04-30 11:37 ` [PATCH 1/6] powerpc/85xx: clean up for mpc8568_mds name Kumar Gala 1 sibling, 3 replies; 13+ messages in thread From: Haiying Wang @ 2009-04-29 18:14 UTC (permalink / raw) To: linuxppc-dev, galak; +Cc: Haiying Wang Change the RISC allocation to macros instead of enum, add function to read the number of risc engines from the new property "num-riscs" under qe node in dts. Add new property "num-riscs" description in qe.txt Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> --- .../powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 1 + arch/powerpc/include/asm/qe.h | 18 ++++++++---- arch/powerpc/sysdev/qe_lib/qe.c | 28 ++++++++++++++++++++ 3 files changed, 41 insertions(+), 6 deletions(-) diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt index 78790d5..b6ea613 100644 --- a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt +++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt @@ -21,6 +21,7 @@ Required properties: Recommended properties - brg-frequency : the internal clock source frequency for baud-rate generators in Hz. +- num-riscs: define how many RISC engines the QE has. Example: qe@e0100000 { diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h index 2701753..60314ef 100644 --- a/arch/powerpc/include/asm/qe.h +++ b/arch/powerpc/include/asm/qe.h @@ -152,6 +152,8 @@ unsigned int qe_get_brg_clk(void); int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); int qe_get_snum(void); void qe_put_snum(u8 snum); +unsigned int qe_get_num_of_risc(void); + /* we actually use cpm_muram implementation, define this for convenience */ #define qe_muram_init cpm_muram_init #define qe_muram_alloc cpm_muram_alloc @@ -231,12 +233,16 @@ struct qe_bd { #define QE_ALIGNMENT_OF_PRAM 64 /* RISC allocation */ -enum qe_risc_allocation { - QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */ - QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */ - QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose - RISC 1 or RISC 2 */ -}; +#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ +#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ +#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ +#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ +#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2) +#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2 | \ + QE_RISC_ALLOCATION_RISC3 | \ + QE_RISC_ALLOCATION_RISC4) /* QE extended filtering Table Lookup Key Size */ enum qe_fltr_tbl_lookup_key_size { diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index 01bce37..31a3bb1 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c @@ -575,3 +575,31 @@ struct qe_firmware_info *qe_get_firmware_info(void) } EXPORT_SYMBOL(qe_get_firmware_info); +unsigned int qe_get_num_of_risc(void) +{ + struct device_node *qe; + int size; + unsigned int num_of_risc = 0; + const u32 *prop; + + qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); + if (!qe) { + /* Older devices trees did not have an "fsl,qe" + * compatible property, so we need to look for + * the QE node by name. + */ + qe = of_find_node_by_type(NULL, "qe"); + if (!qe) + return num_of_risc; + } + + prop = of_get_property(qe, "num-riscs", &size); + if (prop && size == sizeof(*prop)) + num_of_risc = *prop; + + of_node_put(qe); + + return num_of_risc; +} +EXPORT_SYMBOL(qe_get_num_of_risc); + -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth 2009-04-29 18:14 ` [PATCH 2/6] powerpc/qe: update risc allocation for QE Haiying Wang @ 2009-04-29 18:14 ` Haiying Wang 2009-04-29 18:14 ` [PATCH 4/6] powerpc/qe: update QE Serial Number Haiying Wang 2009-04-29 20:23 ` [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth Kumar Gala 2009-04-30 4:34 ` [PATCH 2/6] powerpc/qe: update risc allocation for QE Kumar Gala 2009-04-30 11:48 ` Kumar Gala 2 siblings, 2 replies; 13+ messages in thread From: Haiying Wang @ 2009-04-29 18:14 UTC (permalink / raw) To: linuxppc-dev, galak; +Cc: Haiying Wang Change the definition of riscTx and riscRx to unsigned integer instead of enum, and change their values to support 4 risc allocation if the qe has 4 RISC engines. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> --- drivers/net/ucc_geth.c | 14 +++++++++++--- drivers/net/ucc_geth.h | 4 ++-- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c index d3f39e8..3e003fe 100644 --- a/drivers/net/ucc_geth.c +++ b/drivers/net/ucc_geth.c @@ -270,7 +270,7 @@ static int fill_init_enet_entries(struct ucc_geth_private *ugeth, u8 num_entries, u32 thread_size, u32 thread_alignment, - enum qe_risc_allocation risc, + unsigned int risc, int skip_page_for_first_entry) { u32 init_enet_offset; @@ -307,7 +307,7 @@ static int fill_init_enet_entries(struct ucc_geth_private *ugeth, static int return_init_enet_entries(struct ucc_geth_private *ugeth, u32 *p_start, u8 num_entries, - enum qe_risc_allocation risc, + unsigned int risc, int skip_page_for_first_entry) { u32 init_enet_offset; @@ -342,7 +342,7 @@ static int dump_init_enet_entries(struct ucc_geth_private *ugeth, u32 __iomem *p_start, u8 num_entries, u32 thread_size, - enum qe_risc_allocation risc, + unsigned int risc, int skip_page_for_first_entry) { u32 init_enet_offset; @@ -2134,6 +2134,14 @@ static int ucc_struct_init(struct ucc_geth_private *ugeth) return -ENOMEM; } + /* read the number of risc engines, update the riscTx and riscRx + * if there are 4 riscs in QE + */ + if (qe_get_num_of_risc() == 4) { + ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; + ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; + } + ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); if (!ugeth->ug_regs) { if (netif_msg_probe(ugeth)) diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h index 2f8ee7c..46bb1d2 100644 --- a/drivers/net/ucc_geth.h +++ b/drivers/net/ucc_geth.h @@ -1120,8 +1120,8 @@ struct ucc_geth_info { enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc; enum ucc_geth_num_of_threads numThreadsTx; enum ucc_geth_num_of_threads numThreadsRx; - enum qe_risc_allocation riscTx; - enum qe_risc_allocation riscRx; + unsigned int riscTx; + unsigned int riscRx; }; /* structure representing UCC GETH */ -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/6] powerpc/qe: update QE Serial Number 2009-04-29 18:14 ` [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth Haiying Wang @ 2009-04-29 18:14 ` Haiying Wang 2009-04-29 18:14 ` [PATCH 5/6] net/ucc_geth: Assign six threads to Rx for UEC Haiying Wang 2009-04-30 4:35 ` [PATCH 4/6] powerpc/qe: update QE Serial Number Kumar Gala 2009-04-29 20:23 ` [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth Kumar Gala 1 sibling, 2 replies; 13+ messages in thread From: Haiying Wang @ 2009-04-29 18:14 UTC (permalink / raw) To: linuxppc-dev, galak; +Cc: Haiying Wang The latest QE chip may have more Serial Number(SNUM)s of thread to use. We will get the number of SNUMs from device tree by reading the new property "num-snums" , and set 28 as the default number of SNUMs so that it is compatible with the old QE chips' device trees which don't have this new property. The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum table which is 256. Also we update the snum_init[] array with 18 more new SNUMs which are confirmed to be useful on new chip. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> --- .../powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 1 + arch/powerpc/include/asm/qe.h | 3 +- arch/powerpc/sysdev/qe_lib/qe.c | 47 ++++++++++++++++++-- 3 files changed, 46 insertions(+), 5 deletions(-) diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt index b6ea613..9f7df90 100644 --- a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt +++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt @@ -22,6 +22,7 @@ Recommended properties - brg-frequency : the internal clock source frequency for baud-rate generators in Hz. - num-riscs: define how many RISC engines the QE has. +- num-snums: define how many serial number(SNUM) the QE can use for the threads. Example: qe@e0100000 { diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h index 60314ef..e0faf33 100644 --- a/arch/powerpc/include/asm/qe.h +++ b/arch/powerpc/include/asm/qe.h @@ -22,7 +22,7 @@ #include <asm/cpm.h> #include <asm/immap_qe.h> -#define QE_NUM_OF_SNUM 28 +#define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */ #define QE_NUM_OF_BRGS 16 #define QE_NUM_OF_PORTS 1024 @@ -153,6 +153,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); int qe_get_snum(void); void qe_put_snum(u8 snum); unsigned int qe_get_num_of_risc(void); +unsigned int qe_get_num_of_snums(void); /* we actually use cpm_muram implementation, define this for convenience */ #define qe_muram_init cpm_muram_init diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index 31a3bb1..69116d9 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c @@ -61,6 +61,7 @@ struct qe_immap __iomem *qe_immr; EXPORT_SYMBOL(qe_immr); static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */ +static unsigned int qe_num_of_snum; static phys_addr_t qebase = -1; @@ -264,10 +265,14 @@ static void qe_snums_init(void) 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D, 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89, 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9, - 0xD8, 0xD9, 0xE8, 0xE9, + 0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19, + 0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59, + 0x68, 0x69, 0x78, 0x79, 0x80, 0x81, }; - for (i = 0; i < QE_NUM_OF_SNUM; i++) { + qe_num_of_snum = qe_get_num_of_snums(); + + for (i = 0; i < qe_num_of_snum; i++) { snums[i].num = snum_init[i]; snums[i].state = QE_SNUM_STATE_FREE; } @@ -280,7 +285,7 @@ int qe_get_snum(void) int i; spin_lock_irqsave(&qe_lock, flags); - for (i = 0; i < QE_NUM_OF_SNUM; i++) { + for (i = 0; i < qe_num_of_snum; i++) { if (snums[i].state == QE_SNUM_STATE_FREE) { snums[i].state = QE_SNUM_STATE_USED; snum = snums[i].num; @@ -297,7 +302,7 @@ void qe_put_snum(u8 snum) { int i; - for (i = 0; i < QE_NUM_OF_SNUM; i++) { + for (i = 0; i < qe_num_of_snum; i++) { if (snums[i].num == snum) { snums[i].state = QE_SNUM_STATE_FREE; break; @@ -603,3 +608,37 @@ unsigned int qe_get_num_of_risc(void) } EXPORT_SYMBOL(qe_get_num_of_risc); +unsigned int qe_get_num_of_snums(void) +{ + struct device_node *qe; + int size; + unsigned int num_of_snums; + const u32 *prop; + + num_of_snums = 28; /* The default number of snum for threads is 28 */ + qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); + if (!qe) { + /* Older devices trees did not have an "fsl,qe" + * compatible property, so we need to look for + * the QE node by name. + */ + qe = of_find_node_by_type(NULL, "qe"); + if (!qe) + return num_of_snums; + } + + prop = of_get_property(qe, "num-snums", &size); + if (prop && size == sizeof(*prop)) { + num_of_snums = *prop; + if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) { + /* No QE ever has fewer than 28 SNUMs */ + pr_err("QE: number of snum is invalid\n"); + return -EINVAL; + } + } + + of_node_put(qe); + + return num_of_snums; +} +EXPORT_SYMBOL(qe_get_num_of_snums); -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/6] net/ucc_geth: Assign six threads to Rx for UEC 2009-04-29 18:14 ` [PATCH 4/6] powerpc/qe: update QE Serial Number Haiying Wang @ 2009-04-29 18:14 ` Haiying Wang 2009-04-29 18:14 ` [PATCH 6/6] powerpc/85xx: Add MPC8569MDS board support Haiying Wang 2009-04-29 20:25 ` [PATCH 5/6] net/ucc_geth: Assign six threads to Rx for UEC Kumar Gala 2009-04-30 4:35 ` [PATCH 4/6] powerpc/qe: update QE Serial Number Kumar Gala 1 sibling, 2 replies; 13+ messages in thread From: Haiying Wang @ 2009-04-29 18:14 UTC (permalink / raw) To: linuxppc-dev, galak; +Cc: Haiying Wang when there are 46 snums defined in device tree. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> --- drivers/net/ucc_geth.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c index 3e003fe..1f6529f 100644 --- a/drivers/net/ucc_geth.c +++ b/drivers/net/ucc_geth.c @@ -3709,7 +3709,10 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT; ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT; ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4; - ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4; + if (qe_get_num_of_snums() == 46) + ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6; + else + ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4; } if (netif_msg_probe(&debug)) -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 6/6] powerpc/85xx: Add MPC8569MDS board support 2009-04-29 18:14 ` [PATCH 5/6] net/ucc_geth: Assign six threads to Rx for UEC Haiying Wang @ 2009-04-29 18:14 ` Haiying Wang 2009-04-29 20:25 ` [PATCH 5/6] net/ucc_geth: Assign six threads to Rx for UEC Kumar Gala 1 sibling, 0 replies; 13+ messages in thread From: Haiying Wang @ 2009-04-29 18:14 UTC (permalink / raw) To: linuxppc-dev, galak; +Cc: Haiying Wang Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> --- arch/powerpc/boot/dts/mpc8569mds.dts | 514 +++++++++++++++++++++++++++++ arch/powerpc/platforms/85xx/mpc85xx_mds.c | 23 ++ 2 files changed, 537 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/mpc8569mds.dts diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts new file mode 100644 index 0000000..3ddd8c3 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8569mds.dts @@ -0,0 +1,514 @@ +/* + * MPC8569E MDS Device Tree Source + * + * Copyright (C) 2009 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "MPC8569EMDS"; + compatible = "fsl,MPC8569EMDS"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + ethernet0 = &enet0; + ethernet1 = &enet1; + ethernet2 = &enet2; + ethernet3 = &enet3; + pci1 = &pci1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8569@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + device_type = "memory"; + }; + + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus"; + reg = <0 0xe0005000 0 0x1000>; + interrupt = <19 2>; + interrupt-parent = <&mpic>; + + ranges = <0x0 0x0 0xfe000000 0x02000000 + 0x1 0x0 0xf8000000 0x00008000 + 0x2 0x0 0xf0000000 0x04000000 + 0x4 0x0 0xf8008000 0x00008000 + 0x5 0x0 0xf8010000 0x00008000>; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x02000000>; + bank-width = <2>; + device-width = <1>; + }; + + bcsr@1,0 { + compatible = "fsl,mpc8569mds-bcsr"; + reg = <1 0 0x8000>; + }; + + pib@4,0 { + compatible = "fsl,mpc8569mds-pib"; + reg = <4 0 0x8000>; + }; + + pib@5,0 { + compatible = "fsl,mpc8569mds-pib"; + reg = <5 0 0x8000>; + }; + }; + + soc@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8569-immr", "simple-bus"; + ranges = <0x0 0xe0000000 0x100000>; + reg = <0xe0000000 0x1000>; + bus-frequency = <0>; + + ecm-law@0 { + compatible = "fsl,ecm-law"; + reg = <0x0 0x1000>; + fsl,num-laws = <10>; + }; + + ecm@1000 { + compatible = "fsl,mpc8569-ecm", "fsl,ecm"; + reg = <0x1000 0x1000>; + interrupts = <17 2>; + interrupt-parent = <&mpic>; + }; + + memory-controller@2000 { + compatible = "fsl,mpc8569-memory-controller"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + }; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + + rtc@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <43 2>; + interrupt-parent = <&mpic>; + dfsrr; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2>; + interrupt-parent = <&mpic>; + }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8569-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; // 32 bytes + cache-size = <0x80000>; // L2, 512K + interrupt-parent = <&mpic>; + interrupts = <16 2>; + }; + + dma@21300 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma"; + reg = <0x21300 0x4>; + ranges = <0x0 0x21100 0x200>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8569-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + cell-index = <0>; + interrupt-parent = <&mpic>; + interrupts = <20 2>; + }; + dma-channel@80 { + compatible = "fsl,mpc8569-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupt-parent = <&mpic>; + interrupts = <21 2>; + }; + dma-channel@100 { + compatible = "fsl,mpc8569-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupt-parent = <&mpic>; + interrupts = <22 2>; + }; + dma-channel@180 { + compatible = "fsl,mpc8569-dma-channel", + "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupt-parent = <&mpic>; + interrupts = <23 2>; + }; + }; + + crypto@30000 { + compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4", + "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <45 2 58 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x9fe>; + fsl,descriptor-types-mask = <0x3ab0ebf>; + }; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x40000 0x40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + }; + + global-utilities@e0000 { + compatible = "fsl,mpc8569-guts"; + reg = <0xe0000 0x1000>; + fsl,has-rstcr; + }; + + par_io@e0100 { + reg = <0xe0100 0x100>; + device_type = "par_io"; + num-ports = <7>; + + pio1: ucc_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ + 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ + 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/ + 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */ + 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */ + 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */ + 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ + 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */ + 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */ + 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ + 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ + 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ + 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */ + 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */ + 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */ + }; + + pio2: ucc_pin@02 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ + 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ + 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */ + 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */ + 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */ + 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */ + 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */ + 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */ + 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */ + 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */ + 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */ + 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */ + 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */ + 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */ + 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */ + }; + + pio3: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ + 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ + 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/ + 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */ + 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */ + 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */ + 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */ + 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */ + 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */ + 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */ + 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */ + 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */ + 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */ + 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */ + 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */ + }; + + pio4: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ + 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ + 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */ + 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */ + 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */ + 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */ + 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */ + 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */ + 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */ + 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */ + 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */ + 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */ + 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */ + 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */ + 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */ + }; + }; + }; + + qe@e0080000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + ranges = <0x0 0xe0080000 0x40000>; + reg = <0xe0080000 0x480>; + brg-frequency = <0>; + bus-frequency = <0>; + num-riscs = <4>; + num-snums = <46>; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + interrupts = <46 2 46 2>; //high:30 low:30 + interrupt-parent = <&mpic>; + }; + + spi@4c0 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x4c0 0x40>; + interrupts = <2>; + interrupt-parent = <&qeic>; + mode = "cpu"; + }; + + spi@500 { + cell-index = <1>; + compatible = "fsl,spi"; + reg = <0x500 0x40>; + interrupts = <1>; + interrupt-parent = <&qeic>; + mode = "cpu"; + }; + + enet0: ucc@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk12"; + pio-handle = <&pio1>; + phy-handle = <&qe_phy0>; + phy-connection-type = "rgmii-id"; + }; + + mdio@2120 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2120 0x18>; + compatible = "fsl,ucc-mdio"; + + qe_phy0: ethernet-phy@07 { + interrupt-parent = <&mpic>; + interrupts = <1 1>; + reg = <0x7>; + device_type = "ethernet-phy"; + }; + qe_phy1: ethernet-phy@01 { + interrupt-parent = <&mpic>; + interrupts = <2 1>; + reg = <0x1>; + device_type = "ethernet-phy"; + }; + qe_phy2: ethernet-phy@02 { + interrupt-parent = <&mpic>; + interrupts = <3 1>; + reg = <0x2>; + device_type = "ethernet-phy"; + }; + qe_phy3: ethernet-phy@03 { + interrupt-parent = <&mpic>; + interrupts = <4 1>; + reg = <0x3>; + device_type = "ethernet-phy"; + }; + }; + + enet2: ucc@2200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <3>; + reg = <0x2200 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk12"; + pio-handle = <&pio3>; + phy-handle = <&qe_phy2>; + phy-connection-type = "rgmii-id"; + }; + + enet1: ucc@3000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <2>; + reg = <0x3000 0x200>; + interrupts = <33>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + pio-handle = <&pio2>; + phy-handle = <&qe_phy1>; + phy-connection-type = "rgmii-id"; + }; + + enet3: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + pio-handle = <&pio4>; + phy-handle = <&qe_phy3>; + phy-connection-type = "rgmii-id"; + }; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x10000 0x20000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x20000>; + }; + }; + + }; + + /* PCI Express */ + pci1: pcie@e000a000 { + compatible = "fsl,mpc8548-pcie"; + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xe000a000 0x1000>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0 (PEX) */ + 00000 0x0 0x0 0x1 &mpic 0x0 0x1 + 00000 0x0 0x0 0x2 &mpic 0x1 0x1 + 00000 0x0 0x0 0x3 &mpic 0x2 0x1 + 00000 0x0 0x0 0x4 &mpic 0x3 0x1>; + + interrupt-parent = <&mpic>; + interrupts = <26 2>; + bus-range = <0 255>; + ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 + 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>; + clock-frequency = <33333333>; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x10000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x800000>; + }; + }; +}; diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index d34d29a..b2c0a43 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -259,6 +259,7 @@ static int __init board_fixups(void) return 0; } machine_arch_initcall(mpc8568_mds, board_fixups); +machine_arch_initcall(mpc8569_mds, board_fixups); static struct of_device_id mpc85xx_ids[] = { { .type = "soc", }, @@ -278,6 +279,7 @@ static int __init mpc85xx_publish_devices(void) return 0; } machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices); +machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices); static void __init mpc85xx_mds_pic_init(void) { @@ -335,3 +337,24 @@ define_machine(mpc8568_mds) { .pcibios_fixup_bus = fsl_pcibios_fixup_bus, #endif }; + +static int __init mpc8569_mds_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS"); +} + +define_machine(mpc8569_mds) { + .name = "MPC8569 MDS", + .probe = mpc8569_mds_probe, + .setup_arch = mpc85xx_mds_setup_arch, + .init_IRQ = mpc85xx_mds_pic_init, + .get_irq = mpic_get_irq, + .restart = fsl_rstcr_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif +}; -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 5/6] net/ucc_geth: Assign six threads to Rx for UEC 2009-04-29 18:14 ` [PATCH 5/6] net/ucc_geth: Assign six threads to Rx for UEC Haiying Wang 2009-04-29 18:14 ` [PATCH 6/6] powerpc/85xx: Add MPC8569MDS board support Haiying Wang @ 2009-04-29 20:25 ` Kumar Gala 1 sibling, 0 replies; 13+ messages in thread From: Kumar Gala @ 2009-04-29 20:25 UTC (permalink / raw) To: Haiying Wang; +Cc: linuxppc-dev On Apr 29, 2009, at 1:14 PM, Haiying Wang wrote: > when there are 46 snums defined in device tree. > > Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> > --- > drivers/net/ucc_geth.c | 5 ++++- > 1 files changed, 4 insertions(+), 1 deletions(-) Can you be a bit more explicit in the commit message about the detection of 46 snums. How is it that 46 snums equates to 6 threads? - k > > > diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c > index 3e003fe..1f6529f 100644 > --- a/drivers/net/ucc_geth.c > +++ b/drivers/net/ucc_geth.c > @@ -3709,7 +3709,10 @@ static int ucc_geth_probe(struct of_device* > ofdev, const struct of_device_id *ma > ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT; > ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT; > ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4; > - ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4; > + if (qe_get_num_of_snums() == 46) > + ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6; > + else > + ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4; > } > > if (netif_msg_probe(&debug)) > -- > 1.6.0.2 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/6] powerpc/qe: update QE Serial Number 2009-04-29 18:14 ` [PATCH 4/6] powerpc/qe: update QE Serial Number Haiying Wang 2009-04-29 18:14 ` [PATCH 5/6] net/ucc_geth: Assign six threads to Rx for UEC Haiying Wang @ 2009-04-30 4:35 ` Kumar Gala 1 sibling, 0 replies; 13+ messages in thread From: Kumar Gala @ 2009-04-30 4:35 UTC (permalink / raw) To: Haiying Wang; +Cc: linuxppc-dev On Apr 29, 2009, at 1:14 PM, Haiying Wang wrote: > The latest QE chip may have more Serial Number(SNUM)s of thread to > use. We will > get the number of SNUMs from device tree by reading the new property > "num-snums" > , and set 28 as the default number of SNUMs so that it is compatible > with the > old QE chips' device trees which don't have this new property. > The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum > table which > is 256. > Also we update the snum_init[] array with 18 more new SNUMs which are > confirmed to be useful on new chip. > > Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> > --- > .../powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 1 + > arch/powerpc/include/asm/qe.h | 3 +- > arch/powerpc/sysdev/qe_lib/qe.c | 47 +++++++++++ > +++++++-- > 3 files changed, 46 insertions(+), 5 deletions(-) how about updating the existing .dts for this as well. (One patch w/ this and # riscs is fine). - k ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth 2009-04-29 18:14 ` [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth Haiying Wang 2009-04-29 18:14 ` [PATCH 4/6] powerpc/qe: update QE Serial Number Haiying Wang @ 2009-04-29 20:23 ` Kumar Gala 2009-04-29 21:51 ` David Miller 1 sibling, 1 reply; 13+ messages in thread From: Kumar Gala @ 2009-04-29 20:23 UTC (permalink / raw) To: David Miller; +Cc: Linuxppc-dev Development, Netdev, Haiying Wang On Apr 29, 2009, at 1:14 PM, Haiying Wang wrote: > Change the definition of riscTx and riscRx to unsigned integer > instead of enum, > and change their values to support 4 risc allocation if the qe has 4 > RISC > engines. > > Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> > --- Dave, if you can ack this it is probably easier if this goes via the powerpc tree as it had some dependancies. - k > > drivers/net/ucc_geth.c | 14 +++++++++++--- > drivers/net/ucc_geth.h | 4 ++-- > 2 files changed, 13 insertions(+), 5 deletions(-) > > diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c > index d3f39e8..3e003fe 100644 > --- a/drivers/net/ucc_geth.c > +++ b/drivers/net/ucc_geth.c > @@ -270,7 +270,7 @@ static int fill_init_enet_entries(struct > ucc_geth_private *ugeth, > u8 num_entries, > u32 thread_size, > u32 thread_alignment, > - enum qe_risc_allocation risc, > + unsigned int risc, > int skip_page_for_first_entry) > { > u32 init_enet_offset; > @@ -307,7 +307,7 @@ static int fill_init_enet_entries(struct > ucc_geth_private *ugeth, > static int return_init_enet_entries(struct ucc_geth_private *ugeth, > u32 *p_start, > u8 num_entries, > - enum qe_risc_allocation risc, > + unsigned int risc, > int skip_page_for_first_entry) > { > u32 init_enet_offset; > @@ -342,7 +342,7 @@ static int dump_init_enet_entries(struct > ucc_geth_private *ugeth, > u32 __iomem *p_start, > u8 num_entries, > u32 thread_size, > - enum qe_risc_allocation risc, > + unsigned int risc, > int skip_page_for_first_entry) > { > u32 init_enet_offset; > @@ -2134,6 +2134,14 @@ static int ucc_struct_init(struct > ucc_geth_private *ugeth) > return -ENOMEM; > } > > + /* read the number of risc engines, update the riscTx and riscRx > + * if there are 4 riscs in QE > + */ > + if (qe_get_num_of_risc() == 4) { > + ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; > + ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; > + } > + > ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); > if (!ugeth->ug_regs) { > if (netif_msg_probe(ugeth)) > diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h > index 2f8ee7c..46bb1d2 100644 > --- a/drivers/net/ucc_geth.h > +++ b/drivers/net/ucc_geth.h > @@ -1120,8 +1120,8 @@ struct ucc_geth_info { > enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc; > enum ucc_geth_num_of_threads numThreadsTx; > enum ucc_geth_num_of_threads numThreadsRx; > - enum qe_risc_allocation riscTx; > - enum qe_risc_allocation riscRx; > + unsigned int riscTx; > + unsigned int riscRx; > }; > > /* structure representing UCC GETH */ > -- > 1.6.0.2 ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth 2009-04-29 20:23 ` [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth Kumar Gala @ 2009-04-29 21:51 ` David Miller 0 siblings, 0 replies; 13+ messages in thread From: David Miller @ 2009-04-29 21:51 UTC (permalink / raw) To: galak; +Cc: linuxppc-dev, netdev, Haiying.Wang From: Kumar Gala <galak@kernel.crashing.org> Date: Wed, 29 Apr 2009 15:23:21 -0500 > > On Apr 29, 2009, at 1:14 PM, Haiying Wang wrote: > >> Change the definition of riscTx and riscRx to unsigned integer instead >> of enum, >> and change their values to support 4 risc allocation if the qe has 4 >> RISC >> engines. >> >> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> >> --- > > Dave, if you can ack this it is probably easier if this goes via the > powerpc tree as it had some dependancies. Fair enough: Acked-by: David S. Miller <davem@davemloft.net> ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/6] powerpc/qe: update risc allocation for QE 2009-04-29 18:14 ` [PATCH 2/6] powerpc/qe: update risc allocation for QE Haiying Wang 2009-04-29 18:14 ` [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth Haiying Wang @ 2009-04-30 4:34 ` Kumar Gala 2009-04-30 11:48 ` Kumar Gala 2 siblings, 0 replies; 13+ messages in thread From: Kumar Gala @ 2009-04-30 4:34 UTC (permalink / raw) To: Haiying Wang; +Cc: linuxppc-dev On Apr 29, 2009, at 1:14 PM, Haiying Wang wrote: > Change the RISC allocation to macros instead of enum, add function > to read the > number of risc engines from the new property "num-riscs" under qe > node in dts. > Add new property "num-riscs" description in qe.txt > > Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> > --- > .../powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 1 + > arch/powerpc/include/asm/qe.h | 18 ++++++++---- > arch/powerpc/sysdev/qe_lib/qe.c | 28 +++++++++++ > +++++++++ > 3 files changed, 41 insertions(+), 6 deletions(-) This patch is fine, how about one that updates the exist device tree's w/QE for this new property - k ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/6] powerpc/qe: update risc allocation for QE 2009-04-29 18:14 ` [PATCH 2/6] powerpc/qe: update risc allocation for QE Haiying Wang 2009-04-29 18:14 ` [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth Haiying Wang 2009-04-30 4:34 ` [PATCH 2/6] powerpc/qe: update risc allocation for QE Kumar Gala @ 2009-04-30 11:48 ` Kumar Gala 2 siblings, 0 replies; 13+ messages in thread From: Kumar Gala @ 2009-04-30 11:48 UTC (permalink / raw) To: Haiying Wang; +Cc: linuxppc-dev On Apr 29, 2009, at 1:14 PM, Haiying Wang wrote: > Change the RISC allocation to macros instead of enum, add function > to read the > number of risc engines from the new property "num-riscs" under qe > node in dts. > Add new property "num-riscs" description in qe.txt > > Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> > --- > .../powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 1 + > arch/powerpc/include/asm/qe.h | 18 ++++++++---- > arch/powerpc/sysdev/qe_lib/qe.c | 28 +++++++++++ > +++++++++ > 3 files changed, 41 insertions(+), 6 deletions(-) I'm wondering if these should be fsl,num-riscs or fsl,qe-num-riscs since its a new property. Ditto for num-snums. Also, shouldn't both of these be in the Required section of the binding. - k ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/6] powerpc/85xx: clean up for mpc8568_mds name 2009-04-29 18:14 [PATCH 1/6] powerpc/85xx: clean up for mpc8568_mds name Haiying Wang 2009-04-29 18:14 ` [PATCH 2/6] powerpc/qe: update risc allocation for QE Haiying Wang @ 2009-04-30 11:37 ` Kumar Gala 1 sibling, 0 replies; 13+ messages in thread From: Kumar Gala @ 2009-04-30 11:37 UTC (permalink / raw) To: Haiying Wang; +Cc: linuxppc-dev On Apr 29, 2009, at 1:14 PM, Haiying Wang wrote: > Keep an unique machine def for the MPC8568 MDS board to handle some > subtle differences between the future MDS board. Also set the bcsrs in > setup_arch() only for mpc8568_mds because other mds has different > bcsr settings. > > Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> > --- > arch/powerpc/platforms/85xx/mpc85xx_mds.c | 29 ++++++++++++++ > +-------------- > 1 files changed, 15 insertions(+), 14 deletions(-) applied to next - k ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2009-04-30 11:50 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2009-04-29 18:14 [PATCH 1/6] powerpc/85xx: clean up for mpc8568_mds name Haiying Wang 2009-04-29 18:14 ` [PATCH 2/6] powerpc/qe: update risc allocation for QE Haiying Wang 2009-04-29 18:14 ` [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth Haiying Wang 2009-04-29 18:14 ` [PATCH 4/6] powerpc/qe: update QE Serial Number Haiying Wang 2009-04-29 18:14 ` [PATCH 5/6] net/ucc_geth: Assign six threads to Rx for UEC Haiying Wang 2009-04-29 18:14 ` [PATCH 6/6] powerpc/85xx: Add MPC8569MDS board support Haiying Wang 2009-04-29 20:25 ` [PATCH 5/6] net/ucc_geth: Assign six threads to Rx for UEC Kumar Gala 2009-04-30 4:35 ` [PATCH 4/6] powerpc/qe: update QE Serial Number Kumar Gala 2009-04-29 20:23 ` [PATCH 3/6] net/ucc_geth: update riscTx and riscRx in ucc_geth Kumar Gala 2009-04-29 21:51 ` David Miller 2009-04-30 4:34 ` [PATCH 2/6] powerpc/qe: update risc allocation for QE Kumar Gala 2009-04-30 11:48 ` Kumar Gala 2009-04-30 11:37 ` [PATCH 1/6] powerpc/85xx: clean up for mpc8568_mds name Kumar Gala
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