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Sun, 4 Dec 2022 07:10:39 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.7.0-alpha0-1115-g8b801eadce-fm-20221102.001-g8b801ead Mime-Version: 1.0 Message-Id: <81a7715b-559f-4c5c-bdb6-1aa00d409155@app.fastmail.com> In-Reply-To: References: Date: Sun, 04 Dec 2022 13:10:19 +0100 From: "Arnd Bergmann" To: "Dmitry Torokhov" , soc@kernel.org Subject: Re: [RESEND PATCH] soc: fsl: qe: request pins non-exclusively Content-Type: text/plain X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Greg Kroah-Hartman , Linus Walleij , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Li Yang , Andy Shevchenko , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, Qiang Zhao Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Sun, Dec 4, 2022, at 05:50, Dmitry Torokhov wrote: > > SoC team, the problematic patch has been in next for a while and it > would be great to get the fix in to make sure the driver is not broken > in 6.2. Thanks! I have no problem taking thsi patch, but I get a merge conflict that I'm not sure how to resolve: @@@ -186,23 -182,27 +180,43 @@@ struct qe_pin *qe_pin_request(struct de if (WARN_ON(!gc)) { err = -ENODEV; goto err0; ++<<<<<<< HEAD + } + qe_pin->gpiod = gpiod; + qe_pin->controller = gpiochip_get_data(gc); + /* + * FIXME: this gets the local offset on the gpio_chip so that the driver + * can manipulate pin control settings through its custom API. The real + * solution is to create a real pin control driver for this. + */ + qe_pin->num = gpio_chip_hwgpio(gpiod); + + if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) { + pr_debug("%s: tried to get a non-qe pin\n", __func__); + gpiod_put(gpiod); ++======= + } else if (!fwnode_device_is_compatible(gc->fwnode, + "fsl,mpc8323-qe-pario-bank")) { + dev_dbg(dev, "%s: tried to get a non-qe pin\n", __func__); ++>>>>>>> soc: fsl: qe: request pins non-exclusively err = -EINVAL; - goto err0; + } else { + qe_pin->controller = gpiochip_get_data(gc); + /* + * FIXME: this gets the local offset on the gpio_chip so that + * the driver can manipulate pin control settings through its + * custom API. The real solution is to create a real pin control + * driver for this. + */ + qe_pin->num = desc_to_gpio(gpiod) - gc->base; } Could you rebase the patch on top of the soc/driver branch in the soc tree and send the updated version? Arnd