Re: [PATCH 3/3] Enable storage keys for radix - user mode execution

[Balbir Singh <bsingharora@gmail.com>]

On 09/11/16 03:15, Aneesh Kumar K.V wrote:
> Balbir Singh <bsingharora@gmail.com> writes:
> 
>> ISA 3 defines new encoded access authority that allows instruction
>> access prevention in privileged mode and allows normal access
>> to problem state. This patch just enables IAMR (Instruction Authority
>> Mask Register), enabling AMR would require more work.
> 
> 
> We may want to explain what the rules are with details like IAMR class 0
> bit 1 controls the instruction access etc. Also we can metion that we
> now setup user pages such that EAA[0] is set to 0
> 
>>
>> I've tested this with a buggy driver and a simple payload. The payload
>> is specific to the build I've tested.
>>
>> Signed-off-by: Balbir Singh <bsingharora@gmail.com>
>> ---
>>  arch/powerpc/mm/pgtable-radix.c | 19 +++++++++++++++++++
>>  1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
>> index 0fdd8ed..cd3d400 100644
>> --- a/arch/powerpc/mm/pgtable-radix.c
>> +++ b/arch/powerpc/mm/pgtable-radix.c
>> @@ -339,6 +339,24 @@ static void __init radix_init_amor(void)
>>  	mtspr(SPRN_AMOR, amor);
>>  }
>>  
>> +/*
>> + * For radix page tables we setup, the IAMR values as follows
>> + * IMAR = 0100...00 (key 0 is set to 1)
>> + * AMR, UAMR, UAMOR are not affected
>> + */
>> +static void __init radix_init_iamr(void)
>> +{
>> +	unsigned long iamr_mask = 0x4000000000000000;
>> +	unsigned long iamr = mfspr(SPRN_IAMR);
>> +
>> +	if (cpu_has_feature(CPU_FTR_POWER9_DD1))
>> +		return;
> 
> is this needed ?
> 

Yes, IAMR support is DD1+

>> +
>> +	iamr |= iamr_mask;
>> +
>> +	mtspr(SPRN_IAMR, iamr);
>> +}
> 
> Why do '|'. Who else can set this ?
> 
>> +
>>  void __init radix__early_init_mmu(void)
>>  {
>>  	unsigned long lpcr;
>> @@ -398,6 +416,7 @@ void __init radix__early_init_mmu(void)
>>  		radix_init_amor();
>>  	}
>>  
>> +	radix_init_iamr();
>>  	radix_init_pgtable();
>>  }
> 
> What about secondary cpus ?
> 

Oops..Yes, will do a v3. 

> -aneesh
>