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From: Segher Boessenkool <segher@kernel.crashing.org>
Subject: Re: [PATCH 04/61] 8xx: Work around CPU15 erratum.
Date: Thu, 19 Jul 2007 17:01:45 +0200
To: Scott Wood <scottwood@freescale.com>
Cc: linuxppc-dev@ozlabs.org
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> The CPU15 erratum on MPC8xx chips can cause incorrect code execution
> under certain circumstances, where there is a conditional or indirect
> branch in the last word of a page, with a target in the last cache  
> line
> of the next page.  This patch implements one of the suggested
> workarounds, by forcing a TLB miss whenever execution crosses a page
> boundary.  This is done by invalidating the pages before and after the
> one being loaded into the TLB in the ITLB miss handler.

So you never found a bug workaround without the terrible
overhead of this one?  A shame :-(


Segher