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Fri, 29 May 2026 03:58:33 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (smtpav02.fra02v.mail.ibm.com [10.20.54.101]) by smtprelay03.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 64T3wUtj41288156 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 29 May 2026 03:58:30 GMT Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 31F372004E; Fri, 29 May 2026 03:58:30 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1A24320040; Fri, 29 May 2026 03:58:26 +0000 (GMT) Received: from [9.39.19.35] (unknown [9.39.19.35]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 29 May 2026 03:58:25 +0000 (GMT) Message-ID: <85ff1fec-632c-4e5a-9b47-5d4b4a70a1a2@linux.ibm.com> Date: Fri, 29 May 2026 09:28:24 +0530 X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [BUG] sched/cache: "Make LLC id continuous" causes NULL cpumask dereference in build_sched_domains on POWER9 To: Venkat Rao Bagalkote , "Chen, Yu C" , tim.c.chen@linux.intel.com, K Prateek Nayak , Srikar Dronamraju Cc: Madhavan Srinivasan , Ritesh Harjani , "Christophe Leroy (CS GROUP)" , LKML , linuxppc-dev , Peter Zijlstra References: <51154de7-3700-4cb4-82f2-1b3a8fa427f7@linux.ibm.com> From: Shrikanth Hegde Content-Language: en-US In-Reply-To: <51154de7-3700-4cb4-82f2-1b3a8fa427f7@linux.ibm.com> Content-Type: text/plain; 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Sorry for too many mails. On 5/25/26 7:37 PM, Venkat Rao Bagalkote wrote: > Greetings!!! > > I am seeing an early boot kernel panic due to NULL pointer dereference > on a POWER9 (pSeries) system when testing linux-next (next-20260522). > > Based on srikar's suggestion to keep the below, #define arch_llc_mask(cpu) cpu_l2_cache_mask(cpu) which makes it pretty much what chenyu had here https://lore.kernel.org/all/8d14c844-b4a8-4af6-acab-2cfdd42225be@intel.com/ I added the changelog and comments. removed the changes in !CONFIG_MC case since powerpc defines it always. I have changed the chenyu tag to Co-developed-by: instead. I have carried the tested-by and reviewed-by tags since patch is still more or less the same. This is based on tip/master at 5c89783224e9 Merge branch into tip/master: 'x86/tdx' I am planning to send it based on tip tree. Let me know if has to be against a any different tree. Please let me know if there are any concerns. verified below too fixes the panic seen in shared LPAR. ============================================ From: Shrikanth Hegde Date: Thu, 28 May 2026 23:23:43 -0400 Subject: [PATCH] sched/topology: Provide arch_llc_mask for cache aware scheduling Venkat Reported a boot kernel panic next-20260522. Git bisect pointed to b5ea300a17e3 ("sched/cache: Make LLC id continuous") Stacktrace points to llc_mask being null. NIP [c000000000e58504] _find_first_bit+0x44/0x130 LR [c000000000e58500] _find_first_bit+0x40/0x130 Call Trace: build_sched_domains+0xad8/0xe50 sched_init_smp+0xa8/0x164 kernel_init_freeable+0x250/0x370 ret_from_kernel_user_thread+0x14/0x1c On powerpc, cpu_coregroup_mask is available only when the underlying hardware support coregroup. In shared LPAR, QEMU guest or power9 etc coregroup isn't supported. In such cases llc_mask was being referenced when it was null leading to panic. on powerpc, LLC is at SMT core level. So assumption that coregroup(MC) domain point to LLC is wrong. Provide a way for archs to say where its LLC is if it not at MC domain. Fixes: b5ea300a17e3 ("sched/cache: Make LLC id continuous") Reported-by: Venkat Rao Bagalkote Closes: https://lore.kernel.org/all/51154de7-3700-4cb4-82f2-1b3a8fa427f7@linux.ibm.com/ Reviewed-by: Chen Yu Tested-by: Ritesh Harjani (IBM) Co-developed-by: Chen, Yu C Signed-off-by: Shrikanth Hegde --- arch/powerpc/include/asm/topology.h | 6 ++++++ kernel/sched/topology.c | 13 +++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h index 66ed5fe1b718..e3de0f3d8b86 100644 --- a/arch/powerpc/include/asm/topology.h +++ b/arch/powerpc/include/asm/topology.h @@ -135,6 +135,12 @@ struct cpumask *cpu_coregroup_mask(int cpu); const struct cpumask *cpu_die_mask(int cpu); int cpu_die_id(int cpu); +/* Points to where the LLC is. On power9 this will point at CACHE + * domain, On others it will point to SMT domain. In all cases + * cpu_l2_cache_mask points to where LLC is. + */ +#define arch_llc_mask(cpu) cpu_l2_cache_mask(cpu) + #ifdef CONFIG_PPC64 #include diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index df2ceb54c970..622e2e01974c 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -2063,12 +2063,21 @@ const struct cpumask *tl_mc_mask(struct sched_domain_topology_level *tl, int cpu return cpu_coregroup_mask(cpu); } -#define llc_mask(cpu) cpu_coregroup_mask(cpu) +/* + * Majority of architectures have LLC at MC domain level with exception + * such as powerpc. Provide a way for arch to specify where its LLC is + * if it falls in exception category + */ +# ifndef arch_llc_mask +#define arch_llc_mask(cpu) cpu_coregroup_mask(cpu) +# endif #else -#define llc_mask(cpu) cpumask_of(cpu) +#define arch_llc_mask(cpu) cpumask_of(cpu) #endif +#define llc_mask(cpu) arch_llc_mask(cpu) + const struct cpumask *tl_pkg_mask(struct sched_domain_topology_level *tl, int cpu) { return cpu_node_mask(cpu); -- 2.47.3