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From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>, paulus@samba.org,
 mpe@ellerman.id.au, Scott Wood <scottwood@freescale.com>,
 Denis Kirjanov <kda@linux-powerpc.org>
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH V5 00/31] powerpc/mm: Update page table format for book3s
 64
In-Reply-To: <1448321325.4574.19.camel@kernel.crashing.org>
References: <1448274160-28446-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
 <1448321325.4574.19.camel@kernel.crashing.org>
Date: Tue, 24 Nov 2015 09:01:15 +0530
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Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:

> On Mon, 2015-11-23 at 15:52 +0530, Aneesh Kumar K.V wrote:
>> This patch series attempt to update book3s 64 linux page table format to
>> make it more flexible. Our current pte format is very restrictive and we
>> overload multiple pte bits. This is due to the non-availability of free bits
>> in pte_t. We use pte_t to track the validity of 4K subpages. This patch
>> series free up pte_t of 11 bits by moving 4K subpage tracking to the
>> lower half of PTE page. The pte format is updated such that we have a
>> better method for identifying a pte entry at pmd level. This will also enable
>> us to implement hugetlb migration(not yet done in this series).
>> 
>> Before making the changes to the pte format, I am splitting the
>> pte header definition such that we now have the below layout for headers
>
> This series actually completely removes the tracking of the subages,
> right ? IE, it also halves the memory footprint of page tables, doesn't
> it ?
>

No, that is done in the next series.

http://mid.gmane.org/1448274825-30289-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com

-aneesh