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Mon, 4 May 2020 07:36:29 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 958E0AE05F; Mon, 4 May 2020 07:36:29 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 75DADAE060; Mon, 4 May 2020 07:36:28 +0000 (GMT) Received: from skywalker.linux.ibm.com (unknown [9.85.98.100]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP; Mon, 4 May 2020 07:36:28 +0000 (GMT) X-Mailer: emacs 27.0.91 (via feedmail 11-beta-1 I) From: "Aneesh Kumar K.V" To: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH 2/2] powerpc/64s/hash: add torture_hpt kernel boot option to increase hash faults In-Reply-To: <20200503082236.17991-2-npiggin@gmail.com> References: <20200503082236.17991-1-npiggin@gmail.com> <20200503082236.17991-2-npiggin@gmail.com> Date: Mon, 04 May 2020 13:06:25 +0530 Message-ID: <874kswm9s6.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-05-04_04:2020-05-01, 2020-05-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 mlxscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 adultscore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2005040059 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Nicholas Piggin writes: > This option increases the number of hash misses by limiting the number of > kernel HPT entries. This helps stress test difficult to hit paths in the > kernel. > It would nice if we can explain in commit message how we are limiting the number of HPT entries. > Signed-off-by: Nicholas Piggin > --- > .../admin-guide/kernel-parameters.txt | 9 +++ > arch/powerpc/include/asm/book3s/64/mmu-hash.h | 10 +++ > arch/powerpc/mm/book3s64/hash_4k.c | 3 + > arch/powerpc/mm/book3s64/hash_64k.c | 8 +++ > arch/powerpc/mm/book3s64/hash_utils.c | 66 ++++++++++++++++++- > 5 files changed, 95 insertions(+), 1 deletion(-) .... > +void hpt_do_torture(unsigned long ea, unsigned long access, > + unsigned long rflags, unsigned long hpte_group) > +{ > + unsigned long last_group; > + int cpu = raw_smp_processor_id(); > + > + last_group = torture_hpt_last_group[cpu]; > + if (last_group != -1UL) { > + while (mmu_hash_ops.hpte_remove(last_group) != -1) > + ; > + torture_hpt_last_group[cpu] = -1UL; > + } > + > +#define QEMU_WORKAROUND 0 > + > + if (ea >= PAGE_OFFSET) { > + if (!QEMU_WORKAROUND && (access & (_PAGE_READ|_PAGE_WRITE)) && > + !(rflags & (HPTE_R_I|HPTE_R_G))) { > + /* prefetch / prefetchw does not seem to set up a TLB > + * entry with the powerpc systemsim (mambo) emulator, > + * though it works with real hardware. An alternative > + * approach that would work more reliably on quirky > + * emulators like QEMU may be to remember the last > + * insertion and remove that, rather than removing the > + * current insertion. Then no prefetch is required. > + */ > + if ((access & _PAGE_WRITE) && (access & _PAGE_READ)) > + atomic_add(0, (atomic_t *)(ea & ~0x3)); > + else if (access & _PAGE_READ) > + *(volatile char *)ea; > + > + mb(); > + > + while (mmu_hash_ops.hpte_remove(hpte_group) != -1) > + ; Do we get similar hpte faults rate, if we remove everything except the current inserted entry?. If so that would largely simplify the code. > + } else { > + /* Can't prefetch cache-inhibited so clear next time. */ > + torture_hpt_last_group[cpu] = hpte_group; > + } > + } > +} > + > + > #ifdef CONFIG_DEBUG_PAGEALLOC > static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) > { > -- > 2.23.0 -aneesh