From: Michael Ellerman <mpe@ellerman.id.au>
To: Nicholas Piggin <npiggin@gmail.com>
Cc: linuxppc-dev@lists.ozlabs.org,
"Gautham R . Shenoy" <ego@linux.vnet.ibm.com>
Subject: Re: [PATCH 12/13] powerpc/64: runlatch CTRL[RUN] set optimisation
Date: Thu, 15 Jun 2017 19:35:58 +1000 [thread overview]
Message-ID: <874lvhpp8h.fsf@concordia.ellerman.id.au> (raw)
In-Reply-To: <20170614234400.214a1586@roar.ozlabs.ibm.com>
Nicholas Piggin <npiggin@gmail.com> writes:
> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
> index baae104b16c7..f587c1fdf981 100644
> --- a/arch/powerpc/kernel/process.c
> +++ b/arch/powerpc/kernel/process.c
> @@ -1960,11 +1960,25 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
> void notrace __ppc64_runlatch_on(void)
> {
> struct thread_info *ti = current_thread_info();
> - unsigned long ctrl;
>
> - ctrl = mfspr(SPRN_CTRLF);
> - ctrl |= CTRL_RUNLATCH;
> - mtspr(SPRN_CTRLT, ctrl);
> + if (cpu_has_feature(CPU_FTR_ARCH_206)) {
> + /*
> + * Least significant bit (RUN) is the only writable bit of
> + * the CTRL register, so we can avoid mfspr. 2.06 is not the
> + * earliest ISA where this is the case, but it's convenient.
> + */
> + mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
> + } else {
> + unsigned long ctrl;
> +
> + /*
> + * Some architectures (e.g., Cell) have writable fields other
> + * than RUN, so do the read-modify-write.
> + */
> + ctrl = mfspr(SPRN_CTRLF);
> + ctrl |= CTRL_RUNLATCH;
> + mtspr(SPRN_CTRLT, ctrl);
> + }
Does the generated code look any good if you do something like:
unsigned long ctrl;
ctrl = 0;
if (!cpu_has_feature(CPU_FTR_ARCH_206))
ctrl = mfspr(SPRN_CTRLF);
ctrl |= CTRL_RUNLATCH;
mtspr(SPRN_CTRLT, ctrl);
That would offend me slightly less ;)
cheers
next prev parent reply other threads:[~2017-06-15 9:35 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-13 13:05 [PATCH 00/13 v3] idle performance improvements Nicholas Piggin
2017-06-13 13:05 ` [PATCH 01/13] powerpc/64s: idle move soft interrupt mask logic into C code Nicholas Piggin
2017-06-19 12:25 ` [01/13] " Michael Ellerman
2017-06-13 13:05 ` [PATCH 02/13] powerpc/64s: idle hotplug lazy-irq simplification Nicholas Piggin
2017-06-19 12:25 ` [02/13] " Michael Ellerman
2017-06-13 13:05 ` [PATCH 03/13] powerpc/64s: idle process interrupts from system reset wakeup Nicholas Piggin
2017-06-13 13:28 ` Nicholas Piggin
2017-06-14 11:29 ` Michael Ellerman
2017-06-19 12:25 ` [03/13] " Michael Ellerman
2017-06-13 13:05 ` [PATCH 04/13] powerpc/64s: msgclr when handling doorbell exceptions Nicholas Piggin
2017-06-19 12:25 ` [04/13] " Michael Ellerman
2017-06-13 13:05 ` [PATCH 05/13] powerpc/64s: interrupt replay balance the return branch predictor Nicholas Piggin
2017-06-19 12:25 ` [05/13] " Michael Ellerman
2017-06-13 13:05 ` [PATCH 06/13] powerpc/64s: idle branch to handler with virtual mode offset Nicholas Piggin
2017-06-19 12:25 ` [06/13] " Michael Ellerman
2017-06-13 13:05 ` [PATCH 07/13] powerpc/64s: idle avoid SRR usage in idle sleep/wake paths Nicholas Piggin
2017-06-15 12:11 ` Nicholas Piggin
2017-06-19 12:25 ` [07/13] " Michael Ellerman
2017-06-13 13:05 ` [PATCH 08/13] powerpc/64s: idle hmi wakeup is unlikely Nicholas Piggin
2017-06-19 12:25 ` [08/13] " Michael Ellerman
2017-06-13 13:05 ` [PATCH 09/13] powerpc/64s: cpuidle set polling before enabling irqs Nicholas Piggin
2017-06-14 11:40 ` Michael Ellerman
2017-06-14 11:50 ` Nicholas Piggin
2017-06-14 13:05 ` Michael Ellerman
2017-06-13 13:05 ` [PATCH 10/13] powerpc/64s: cpuidle read mostly for common globals Nicholas Piggin
2017-06-13 13:05 ` [PATCH 11/13] powerpc/64s: cpuidle no memory barrier after break from idle Nicholas Piggin
2017-06-13 13:05 ` [PATCH 12/13] powerpc/64: runlatch CTRL[RUN] set optimisation Nicholas Piggin
2017-06-14 11:38 ` Michael Ellerman
2017-06-14 13:44 ` Nicholas Piggin
2017-06-15 9:35 ` Michael Ellerman [this message]
2017-06-13 13:05 ` [PATCH 13/13] powerpc/64s: idle runlatch switch is done with MSR[EE]=0 Nicholas Piggin
2017-06-19 12:25 ` [13/13] " Michael Ellerman
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