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Violators will be prosecuted for from ; Wed, 23 Nov 2016 03:41:23 -0700 From: "Aneesh Kumar K.V" To: Geoff Levand Cc: linuxppc-dev@lists.ozlabs.org Subject: RE: [V2,10/68] powerpc/mm: Update _PAGE_KERNEL_RO In-Reply-To: References: <1460182444-2468-11-git-send-email-aneesh.kumar@linux.vnet.ibm.com> Date: Wed, 23 Nov 2016 16:11:18 +0530 MIME-Version: 1.0 Content-Type: text/plain Message-Id: <874m2yiilt.fsf@linux.vnet.ibm.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Geoff Levand writes: > Hi Aneesh, > >> --- a/arch/powerpc/platforms/ps3/spu.c >> +++ b/arch/powerpc/platforms/ps3/spu.c >> @@ -205,7 +205,7 @@ static void spu_unmap(struct spu *spu) >> static int __init setup_areas(struct spu *spu) >> { >> struct table {char* name; unsigned long addr; unsigned long size;}; >> - static const unsigned long shadow_flags = _PAGE_NO_CACHE | 3; >> + unsigned long shadow_flags = pgprot_val(pgprot_noncached_wc(PAGE_KERNEL_RO)); >> >> spu_pdata(spu)->shadow = __ioremap(spu_pdata(spu)->shadow_addr, >> sizeof(struct spe_shadow), > > This shadow_flags setting doesn't work correctly for PS3. The PS3's LV1 > hypervisor wants the shadow reg pte bits N=1 and PP=11, so (rflags & 7) == 7. > It also doesn't want bit 0x8000000000000000 set. So maybe these: > > (HPTE_R_N | HPTE_R_PP & ~HPTE_R_PP0) > > For what its worth, this is the error for v4.8: > > ps3_hpte_insert:result=LV1_ILLEGAL_PARAMETER_VALUE (-17) vpn=7e4fa575c0000 pa=300000003000 ix=bae0 v=7e4fa575c001 r=8000300000003126 > > I tried different shadow_flags settings to try to get htab_convert_pte_flags() > to give me the right pte bits, but couldn't find anything that would work. > > Here's the only thing I could get to work: > > --- a/arch/powerpc/mm/hash_utils_64.c > +++ b/arch/powerpc/mm/hash_utils_64.c > @@ -222,6 +222,12 @@ unsigned long htab_convert_pte_flags(unsigned long pteflags) > */ > rflags |= HPTE_R_M; > > + if ((pteflags & 0xc000300000000000UL) == 0xc000300000000000UL) { > + pr_info("%s: bad rflags: pteflags= %lx => rflags=%lx\n", > + __func__, pteflags, rflags); > + return 0x127; > + } > + > return rflags; > } > > And here's the output of that: > > htab_convert_pte_flags: bad rflags: pteflags= c00030000000393c => rflags=8000000000000126 > htab_convert_pte_flags: bad rflags: pteflags= c00030000000593c => rflags=8000000000000126 > htab_convert_pte_flags: bad rflags: pteflags= c00030000000793c => rflags=8000000000000126 > htab_convert_pte_flags: bad rflags: pteflags= c00030000000993c => rflags=8000000000000126 > htab_convert_pte_flags: bad rflags: pteflags= c00030000000b93c => rflags=8000000000000126 > htab_convert_pte_flags: bad rflags: pteflags= c00030000000d93c => rflags=8000000000000126 > > Actually, the problem started with (6a119eae942c "powerpc/mm: Add a _PAGE_PTE bit"), > but I could fix that by using 'shadow_flags = (_PAGE_PRESENT | _PAGE_NO_CACHE | _PAGE_USER)'. > > Please let me know what I need for shadow_flags to get those pte bits set. Can you try this patch ? commit 43e05fa840330f0f2deae1e8cc2effd5df68079f Author: Aneesh Kumar K.V Date: Wed Nov 23 15:23:05 2016 +0530 powerpc/mm: Kernel RO fixup for cell Signed-off-by: Aneesh Kumar K.V diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index e88368354e49..c13242bf3098 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -27,6 +27,11 @@ /* * Individual features below. */ +/* + * kernel read only support + * We added the ppp value 0b110 in ISA 2.04 + */ +#define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000) /* * We need to clear top 16bits of va (from the remaining 64 bits )in @@ -103,10 +108,10 @@ #define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2 #define MMU_FTRS_PPC970 MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA #define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE -#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE -#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE -#define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE -#define MMU_FTRS_POWER9 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE +#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO +#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO +#define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO +#define MMU_FTRS_POWER9 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ MMU_FTR_CI_LARGE_PAGE #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index 5503078090cd..78dabf065ba9 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -193,8 +193,12 @@ unsigned long htab_convert_pte_flags(unsigned long pteflags) /* * Kernel read only mapped with ppp bits 0b110 */ - if (!(pteflags & _PAGE_WRITE)) - rflags |= (HPTE_R_PP0 | 0x2); + if (!(pteflags & _PAGE_WRITE)) { + if (mmu_has_feature(MMU_FTR_KERNEL_RO)) + rflags |= (HPTE_R_PP0 | 0x2); + else + rflags |= 0x3; + } } else { if (pteflags & _PAGE_RWX) rflags |= 0x2;