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charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, David Matlack , linux-riscv@lists.infradead.org, Claudio Imbrenda , Janosch Frank , Marc Zyngier , Huacai Chen , Christian Borntraeger , Albert Ou , Bibo Mao , loongarch@lists.linux.dev, Paul Walmsley , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, Oliver Upton , Palmer Dabbelt , David Stevens , kvm-riscv@lists.infradead.org, Anup Patel , Paolo Bonzini , Tianrui Zhao , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Sean Christopherson writes: > Put the page reference acquired by gfn_to_pfn_prot() if > kvm_vm_ioctl_mte_copy_tags() runs into ZONE_DEVICE memory. KVM's less- > than-stellar heuristics for dealing with pfn-mapped memory means that KVM > can get a page reference to ZONE_DEVICE memory. > > Fixes: f0376edb1ddc ("KVM: arm64: Add ioctl to fetch/store tags in a gues= t") > Signed-off-by: Sean Christopherson > --- > arch/arm64/kvm/guest.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c > index 11098eb7eb44..e1f0ff08836a 100644 > --- a/arch/arm64/kvm/guest.c > +++ b/arch/arm64/kvm/guest.c > @@ -1059,6 +1059,7 @@ int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, > page =3D pfn_to_online_page(pfn); > if (!page) { > /* Reject ZONE_DEVICE memory */ > + kvm_release_pfn_clean(pfn); I guess this gets renamed later in the series. However my main comment is does lack of page always mean a ZONE_DEVICE? Looking at pfn_to_online_page() I see a bunch of other checks first. Why isn't it that functions responsibility to clean up after itself if its returning NULLs? > ret =3D -EFAULT; > goto out; > } --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro