Re: [RFC PATCH] powerpc/32: Switch VDSO to C implementation.

[Thomas Gleixner <tglx@linutronix.de>]

Christophe!

Christophe Leroy <christophe.leroy@c-s.fr> writes:
> In do_hres(), I see:
>
> 		cycles = __arch_get_hw_counter(vd->clock_mode);
> 		ns = vdso_ts->nsec;
> 		last = vd->cycle_last;
> 		if (unlikely((s64)cycles < 0))
> 			return -1;
>
> __arch_get_hw_counter() returns a u64 values. On the PPC, this is read 
> from the timebase which is a 64 bits counter.
>
> Why returning -1 if (s64)cycles < 0 ? Does it means we have to mask out 
> the most significant bit when reading the HW counter ?

Only if you expect the HW counter to reach a value which has bit 63
set. That'd require:

uptime		counter frequency

~292 years      1GHz
~ 58 years      5GHz

assumed that the HW counter starts at 0 when the box is powered on.

The reason why this is implemented in this way is that
__arch_get_hw_counter() needs a way to express that the clocksource of
the moment is not suitable for VDSO so that the syscall fallback gets
invoked.

Sure we could have used a pointer for the value and a return value
indicating the validity, but given the required uptime the resulting
code overhead seemed to be not worth it. At least not for me as I'm not
planning to be around 58 years from now :)

Thanks,

        tglx