From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (bilbo.ozlabs.org [103.22.144.67]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xCvDj322dzDqlX for ; Thu, 20 Jul 2017 23:01:57 +1000 (AEST) From: Michael Ellerman To: Geert Uytterhoeven Cc: Matt Brown , "linuxppc-dev\@lists.ozlabs.org" , "linux-ide\@vger.kernel.org" , DRI Development , "adi-buildroot-devel\@lists.sourceforge.net" , Linux MMC List , MTD Maling List , "linux-arm-kernel\@lists.infradead.org" , linux-spi , "linux-serial\@vger.kernel.org" , USB list Subject: Re: [PATCH] powerpc/asm/cacheflush: Cleanup cacheflush function params In-Reply-To: References: <20170720062850.2195-1-matthew.brown.dev@gmail.com> <87mv7zgwpl.fsf@concordia.ellerman.id.au> Date: Thu, 20 Jul 2017 23:01:56 +1000 Message-ID: <87h8y7gt2z.fsf@concordia.ellerman.id.au> MIME-Version: 1.0 Content-Type: text/plain List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Geert Uytterhoeven writes: > On Thu, Jul 20, 2017 at 1:43 PM, Michael Ellerman wrote: >> Matt Brown writes: >>> The cacheflush prototypes currently use start and stop values and each >>> call requires typecasting the address to an unsigned long. >>> This patch changes the cacheflush prototypes to follow the x86 style of >>> using a base and size values, with base being a void pointer. >>> >>> All callers of the cacheflush functions, including drivers, have been >>> modified to conform to the new prototypes. >>> >>> The 64 bit cacheflush functions which were implemented in assembly code >>> (flush_dcache_range, flush_inval_dcache_range) have been translated into >>> C for readability and coherence. > >>> --- a/arch/powerpc/include/asm/cacheflush.h >>> +++ b/arch/powerpc/include/asm/cacheflush.h >>> @@ -51,13 +51,13 @@ static inline void __flush_dcache_icache_phys(unsigned long physaddr) >>> * Write any modified data cache blocks out to memory and invalidate them. >>> * Does not invalidate the corresponding instruction cache blocks. >>> */ >>> -static inline void flush_dcache_range(unsigned long start, unsigned long stop) >>> +static inline void flush_dcache_range(void *start, unsigned long size) >>> { >>> - void *addr = (void *)(start & ~(L1_CACHE_BYTES - 1)); >>> - unsigned long size = stop - (unsigned long)addr + (L1_CACHE_BYTES - 1); >>> + void *addr = (void *)((u32)start & ~(L1_CACHE_BYTES - 1)); >> >> unsigned long would be nicer than u32. > > Indeed. That would make this work on ppc64, too. > After which ppc64 has an identical copy (u64 = unsigned long on ppc64) below? That was Matt's homework to notice that ;) cheers