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Tue, 30 Jun 2020 05:01:39 +0000 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 05U51Z0h32178536 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 30 Jun 2020 05:01:35 GMT Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E64556E050; Tue, 30 Jun 2020 05:01:37 +0000 (GMT) Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D2D926E04E; Tue, 30 Jun 2020 05:01:34 +0000 (GMT) Received: from skywalker.linux.ibm.com (unknown [9.199.48.28]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP; Tue, 30 Jun 2020 05:01:34 +0000 (GMT) X-Mailer: emacs 27.0.91 (via feedmail 11-beta-1 I) From: "Aneesh Kumar K.V" To: Dan Williams Subject: Re: [PATCH updated] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier In-Reply-To: References: <20200629135722.73558-5-aneesh.kumar@linux.ibm.com> <20200629202901.83516-1-aneesh.kumar@linux.ibm.com> Date: Tue, 30 Jun 2020 10:31:31 +0530 Message-ID: <87imf9gn9w.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-06-29_21:2020-06-29, 2020-06-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 adultscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 mlxscore=0 cotscore=-2147483648 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2006300028 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Kara , linux-nvdimm , Jeff Moyer , Oliver O'Halloran , Michal =?utf-8?Q?Such=C3=A1nek?= , linuxppc-dev Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Dan Williams writes: > On Mon, Jun 29, 2020 at 1:29 PM Aneesh Kumar K.V > wrote: >> >> Architectures like ppc64 provide persistent memory specific barriers >> that will ensure that all stores for which the modifications are >> written to persistent storage by preceding dcbfps and dcbstps >> instructions have updated persistent storage before any data >> access or data transfer caused by subsequent instructions is initiated. >> This is in addition to the ordering done by wmb() >> >> Update nvdimm core such that architecture can use barriers other than >> wmb to ensure all previous writes are architecturally visible for >> the platform buffer flush. >> >> Signed-off-by: Aneesh Kumar K.V >> --- >> drivers/md/dm-writecache.c | 2 +- >> drivers/nvdimm/region_devs.c | 8 ++++---- >> include/linux/libnvdimm.h | 4 ++++ >> 3 files changed, 9 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/md/dm-writecache.c b/drivers/md/dm-writecache.c >> index 74f3c506f084..8c6b6dce64e2 100644 >> --- a/drivers/md/dm-writecache.c >> +++ b/drivers/md/dm-writecache.c >> @@ -536,7 +536,7 @@ static void ssd_commit_superblock(struct dm_writecache *wc) >> static void writecache_commit_flushed(struct dm_writecache *wc, bool wait_for_ios) >> { >> if (WC_MODE_PMEM(wc)) >> - wmb(); >> + arch_pmem_flush_barrier(); >> else >> ssd_commit_flushed(wc, wait_for_ios); >> } >> diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c >> index 4502f9c4708d..b308ad09b63d 100644 >> --- a/drivers/nvdimm/region_devs.c >> +++ b/drivers/nvdimm/region_devs.c >> @@ -1206,13 +1206,13 @@ int generic_nvdimm_flush(struct nd_region *nd_region) >> idx = this_cpu_add_return(flush_idx, hash_32(current->pid + idx, 8)); >> >> /* >> - * The first wmb() is needed to 'sfence' all previous writes >> - * such that they are architecturally visible for the platform >> - * buffer flush. Note that we've already arranged for pmem >> + * The first arch_pmem_flush_barrier() is needed to 'sfence' all >> + * previous writes such that they are architecturally visible for >> + * the platform buffer flush. Note that we've already arranged for pmem >> * writes to avoid the cache via memcpy_flushcache(). The final >> * wmb() ensures ordering for the NVDIMM flush write. >> */ >> - wmb(); >> + arch_pmem_flush_barrier(); >> for (i = 0; i < nd_region->ndr_mappings; i++) >> if (ndrd_get_flush_wpq(ndrd, i, 0)) >> writeq(1, ndrd_get_flush_wpq(ndrd, i, idx)); >> diff --git a/include/linux/libnvdimm.h b/include/linux/libnvdimm.h >> index 18da4059be09..66f6c65bd789 100644 >> --- a/include/linux/libnvdimm.h >> +++ b/include/linux/libnvdimm.h >> @@ -286,4 +286,8 @@ static inline void arch_invalidate_pmem(void *addr, size_t size) >> } >> #endif >> >> +#ifndef arch_pmem_flush_barrier >> +#define arch_pmem_flush_barrier() wmb() >> +#endif > > I think it is out of place to define this in libnvdimm.h and it is odd > to give it such a long name. The other pmem api helpers like > arch_wb_cache_pmem() and arch_invalidate_pmem() are function calls for > libnvdimm driver operations, this barrier is just an instruction and > is closer to wmb() than the pmem api routine. > > Since it is a store fence for pmem, so let's just call it pmem_wmb() > and define the generic version in include/linux/compiler.h. It should > probably also be documented alongside dma_wmb() in > Documentation/memory-barriers.txt about why code would use it over > wmb(), and why a symmetric pmem_rmb() is not needed. How about the below? I used pmem_barrier() instead of pmem_wmb(). I guess we wanted this to order() any data access not jus the following stores to persistent storage? W.r.t why a symmetric pmem_rmb() is not needed I was not sure how to explain that. Are you suggesting to explain why a read/load from persistent storage don't want to wait for pmem_barrier() ? modified Documentation/memory-barriers.txt @@ -1935,6 +1935,16 @@ There are some more advanced barrier functions: relaxed I/O accessors and the Documentation/DMA-API.txt file for more information on consistent memory. + (*) pmem_barrier(); + + These are for use with persistent memory to esure the ordering of stores + to persistent memory region. + + For example, after a non temporal write to persistent storage we use pmem_barrier() + to ensures that stores have updated the persistent storage before + any data access or data transfer caused by subsequent instructions is initiated. + =============================== IMPLICIT KERNEL MEMORY BARRIERS modified arch/powerpc/include/asm/barrier.h @@ -97,6 +97,19 @@ do { \ #define barrier_nospec() #endif /* CONFIG_PPC_BARRIER_NOSPEC */ +/* + * pmem_barrier() ensures that all stores for which the modification + * are written to persistent storage by preceding dcbfps/dcbstps + * instructions have updated persistent storage before any data + * access or data transfer caused by subsequent instructions is + * initiated. + */ +#define pmem_barrier pmem_barrier +static inline void pmem_barrier(void) +{ + asm volatile(PPC_PHWSYNC ::: "memory"); +} + #include #endif /* _ASM_POWERPC_BARRIER_H */ modified include/asm-generic/barrier.h @@ -257,5 +257,16 @@ do { \ }) #endif +/* + * pmem_barrier() ensures that all stores for which the modification + * are written to persistent storage by preceding instructions have + * updated persistent storage before any data access or data transfer + * caused by subsequent instructions is + * initiated. + */ +#ifndef pmem_barrier +#define pmem_barrier wmb() +#endif + #endif /* !__ASSEMBLY__ */ #endif /* __ASM_GENERIC_BARRIER_H */