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Tue, 25 May 2021 13:28:00 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B03D913604F; Tue, 25 May 2021 13:27:57 +0000 (GMT) Received: from skywalker.linux.ibm.com (unknown [9.85.69.234]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Tue, 25 May 2021 13:27:57 +0000 (GMT) X-Mailer: emacs 28.0.50 (via feedmail 11-beta-1 I) From: "Aneesh Kumar K.V" To: Linus Torvalds Subject: Re: [PATCH v6 07/11] mm/mremap: Use range flush that does TLB and page walk cache flush In-Reply-To: References: <20210524090114.63446-1-aneesh.kumar@linux.ibm.com> <20210524090114.63446-8-aneesh.kumar@linux.ibm.com> Date: Tue, 25 May 2021 18:57:55 +0530 Message-ID: <87mtsj6izo.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: MiiQgPjX3yUIbyK4DCugCFWFCTmXSa6N X-Proofpoint-ORIG-GUID: hwTdNsxK0OXOzYQvvj0PzFt0-LEZuTnD X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-25_06:2021-05-25, 2021-05-25 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 spamscore=0 mlxlogscore=976 mlxscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2105250081 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nick Piggin , Linux-MM , Kalesh Singh , Joel Fernandes , Andrew Morton , linuxppc-dev Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Linus Torvalds writes: > On Sun, May 23, 2021 at 11:04 PM Aneesh Kumar K.V > wrote: >> >> Add new helper flush_pte_tlb_pwc_range() which invalidates both TLB and >> page walk cache where TLB entries are mapped with page size PAGE_SIZE. > > So I dislike this patch for two reasons: > > (a) naming. > > If the ppc people want to use crazy TLA's that have no meaning outside > of the powerpc community, that's fine. But only in powerpc code. > > "pwc" makes no sense to me, or to anybody else that isn't intimately > involved in low-level powerpc stuff. I assume it's "page walk cache", > but honestly, outside of this area, PWC is mostly used for a specific > type of webcam. > > So there's no way I'd accept this as-is, simply because of that. > flush_pte_tlb_pwc_range() is simply not an acceptable name. You would > have to spell it out, not use an obscure TLA. > > But I think you don't even want to do that, because of How about flush_tlb_and_page_table_cache() ? > > (b) is this even worth it as a public interface? > > Why doesn't the powerpc radix TLB flushing code just always flush the > page table walking cache when the range is larger than a PMD? > > Once you have big flush ranges like that, I don't believe it makes any > sense not to flush the walking cache too. But such a large range invalidate doesn't imply we are freeing page tables. Hence forcing a page table cache flush for large range invalidate can have performance impact. ppc64 don't do a range page table cache invalidate. Hence we will have to flush the full page table cache. > > NOTE! This is particularly true as "flush the walking cache" isn't a > well-defined operation anyway. Which _levels_ of the walking cache? > Again, the size (and alignment) of the flush would actually tell you. > A new boolean "flush" parameter does *NOT* tell that at all. > > So I think this new interface is mis-named, but I also think it's > pointless. Just DTRT automatically when somebody asks for a flush that > covers a PMD range (or a PUD range). > > Linus -aneesh