From: Fabiano Rosas <farosas@linux.ibm.com>
To: Nicholas Piggin <npiggin@gmail.com>,
kvm-ppc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Cc: Nicholas Piggin <npiggin@gmail.com>
Subject: Re: [PATCH v3 19/52] KVM: PPC: Book3S HV P9: Reduce mtmsrd instructions required to save host SPRs
Date: Sat, 16 Oct 2021 10:45:52 -0300 [thread overview]
Message-ID: <87r1clw0a7.fsf@linux.ibm.com> (raw)
In-Reply-To: <20211004160049.1338837-20-npiggin@gmail.com>
Nicholas Piggin <npiggin@gmail.com> writes:
> This reduces the number of mtmsrd required to enable facility bits when
> saving/restoring registers, by having the KVM code set all bits up front
> rather than using individual facility functions that set their particular
> MSR bits.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Aside: at msr_check_and_set what's with MSR_VSX always being implicitly
set whenever MSR_FP is set? I get that it depends on MSR_FP, but if FP
always implies VSX, then you could stop setting MSR_VSX in this patch.
> ---
> arch/powerpc/include/asm/switch_to.h | 2 +
> arch/powerpc/kernel/process.c | 28 +++++++++++++
> arch/powerpc/kvm/book3s_hv.c | 59 ++++++++++++++++++---------
> arch/powerpc/kvm/book3s_hv_p9_entry.c | 1 +
> 4 files changed, 71 insertions(+), 19 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
> index 9d1fbd8be1c7..e8013cd6b646 100644
> --- a/arch/powerpc/include/asm/switch_to.h
> +++ b/arch/powerpc/include/asm/switch_to.h
> @@ -112,6 +112,8 @@ static inline void clear_task_ebb(struct task_struct *t)
> #endif
> }
>
> +void kvmppc_save_user_regs(void);
> +
> extern int set_thread_tidr(struct task_struct *t);
>
> #endif /* _ASM_POWERPC_SWITCH_TO_H */
> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
> index 50436b52c213..3fca321b820d 100644
> --- a/arch/powerpc/kernel/process.c
> +++ b/arch/powerpc/kernel/process.c
> @@ -1156,6 +1156,34 @@ static inline void save_sprs(struct thread_struct *t)
> #endif
> }
>
> +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
> +void kvmppc_save_user_regs(void)
> +{
> + unsigned long usermsr;
> +
> + if (!current->thread.regs)
> + return;
> +
> + usermsr = current->thread.regs->msr;
> +
> + if (usermsr & MSR_FP)
> + save_fpu(current);
> +
> + if (usermsr & MSR_VEC)
> + save_altivec(current);
> +
> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> + if (usermsr & MSR_TM) {
> + current->thread.tm_tfhar = mfspr(SPRN_TFHAR);
> + current->thread.tm_tfiar = mfspr(SPRN_TFIAR);
> + current->thread.tm_texasr = mfspr(SPRN_TEXASR);
> + current->thread.regs->msr &= ~MSR_TM;
> + }
> +#endif
> +}
> +EXPORT_SYMBOL_GPL(kvmppc_save_user_regs);
> +#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
> +
> static inline void restore_sprs(struct thread_struct *old_thread,
> struct thread_struct *new_thread)
> {
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index fca89ed2244f..16365c0e9872 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -4140,6 +4140,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
> struct p9_host_os_sprs host_os_sprs;
> s64 dec;
> u64 tb, next_timer;
> + unsigned long msr;
> int trap;
>
> WARN_ON_ONCE(vcpu->arch.ceded);
> @@ -4151,8 +4152,23 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
> if (next_timer < time_limit)
> time_limit = next_timer;
>
> + vcpu->arch.ceded = 0;
> +
> save_p9_host_os_sprs(&host_os_sprs);
>
> + /* MSR bits may have been cleared by context switch */
> + msr = 0;
> + if (IS_ENABLED(CONFIG_PPC_FPU))
> + msr |= MSR_FP;
> + if (cpu_has_feature(CPU_FTR_ALTIVEC))
> + msr |= MSR_VEC;
> + if (cpu_has_feature(CPU_FTR_VSX))
> + msr |= MSR_VSX;
> + if (cpu_has_feature(CPU_FTR_TM) ||
> + cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
> + msr |= MSR_TM;
> + msr = msr_check_and_set(msr);
> +
> kvmppc_subcore_enter_guest();
>
> vc->entry_exit_map = 1;
> @@ -4161,12 +4177,13 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
> vcpu_vpa_increment_dispatch(vcpu);
>
> if (cpu_has_feature(CPU_FTR_TM) ||
> - cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
> + cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST)) {
> kvmppc_restore_tm_hv(vcpu, vcpu->arch.shregs.msr, true);
> + msr = mfmsr(); /* TM restore can update msr */
> + }
>
> switch_pmu_to_guest(vcpu, &host_os_sprs);
>
> - msr_check_and_set(MSR_FP | MSR_VEC | MSR_VSX);
> load_fp_state(&vcpu->arch.fp);
> #ifdef CONFIG_ALTIVEC
> load_vr_state(&vcpu->arch.vr);
> @@ -4275,7 +4292,6 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
>
> restore_p9_host_os_sprs(vcpu, &host_os_sprs);
>
> - msr_check_and_set(MSR_FP | MSR_VEC | MSR_VSX);
> store_fp_state(&vcpu->arch.fp);
> #ifdef CONFIG_ALTIVEC
> store_vr_state(&vcpu->arch.vr);
> @@ -4825,19 +4841,24 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu)
> unsigned long user_tar = 0;
> unsigned int user_vrsave;
> struct kvm *kvm;
> + unsigned long msr;
>
> if (!vcpu->arch.sane) {
> run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
> return -EINVAL;
> }
>
> + /* No need to go into the guest when all we'll do is come back out */
> + if (signal_pending(current)) {
> + run->exit_reason = KVM_EXIT_INTR;
> + return -EINTR;
> + }
> +
> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> /*
> * Don't allow entry with a suspended transaction, because
> * the guest entry/exit code will lose it.
> - * If the guest has TM enabled, save away their TM-related SPRs
> - * (they will get restored by the TM unavailable interrupt).
> */
> -#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> if (cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
> (current->thread.regs->msr & MSR_TM)) {
> if (MSR_TM_ACTIVE(current->thread.regs->msr)) {
> @@ -4845,12 +4866,6 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu)
> run->fail_entry.hardware_entry_failure_reason = 0;
> return -EINVAL;
> }
> - /* Enable TM so we can read the TM SPRs */
> - mtmsr(mfmsr() | MSR_TM);
> - current->thread.tm_tfhar = mfspr(SPRN_TFHAR);
> - current->thread.tm_tfiar = mfspr(SPRN_TFIAR);
> - current->thread.tm_texasr = mfspr(SPRN_TEXASR);
> - current->thread.regs->msr &= ~MSR_TM;
> }
> #endif
>
> @@ -4865,18 +4880,24 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu)
>
> kvmppc_core_prepare_to_enter(vcpu);
>
> - /* No need to go into the guest when all we'll do is come back out */
> - if (signal_pending(current)) {
> - run->exit_reason = KVM_EXIT_INTR;
> - return -EINTR;
> - }
> -
> kvm = vcpu->kvm;
> atomic_inc(&kvm->arch.vcpus_running);
> /* Order vcpus_running vs. mmu_ready, see kvmppc_alloc_reset_hpt */
> smp_mb();
>
> - flush_all_to_thread(current);
> + msr = 0;
> + if (IS_ENABLED(CONFIG_PPC_FPU))
> + msr |= MSR_FP;
> + if (cpu_has_feature(CPU_FTR_ALTIVEC))
> + msr |= MSR_VEC;
> + if (cpu_has_feature(CPU_FTR_VSX))
> + msr |= MSR_VSX;
> + if (cpu_has_feature(CPU_FTR_TM) ||
> + cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
> + msr |= MSR_TM;
> + msr = msr_check_and_set(msr);
> +
> + kvmppc_save_user_regs();
>
> /* Save userspace EBB and other register values */
> if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
> diff --git a/arch/powerpc/kvm/book3s_hv_p9_entry.c b/arch/powerpc/kvm/book3s_hv_p9_entry.c
> index a7f63082b4e3..fb9cb34445ea 100644
> --- a/arch/powerpc/kvm/book3s_hv_p9_entry.c
> +++ b/arch/powerpc/kvm/book3s_hv_p9_entry.c
> @@ -224,6 +224,7 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc
> vc->tb_offset_applied = vc->tb_offset;
> }
>
> + /* Could avoid mfmsr by passing around, but probably no big deal */
> msr = mfmsr();
>
> host_hfscr = mfspr(SPRN_HFSCR);
next prev parent reply other threads:[~2021-10-16 13:46 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-04 15:59 [PATCH v3 00/52] KVM: PPC: Book3S HV P9: entry/exit optimisations Nicholas Piggin
2021-10-04 15:59 ` [PATCH v3 01/52] powerpc/64s: Remove WORT SPR from POWER9/10 (take 2) Nicholas Piggin
2021-10-04 15:59 ` [PATCH v3 02/52] powerpc/64s: guard optional TIDR SPR with CPU ftr test Nicholas Piggin
2021-10-11 18:44 ` Fabiano Rosas
2021-10-12 2:08 ` Michael Ellerman
2021-10-13 16:51 ` Fabiano Rosas
2021-10-04 16:00 ` [PATCH v3 03/52] KMV: PPC: Book3S HV P9: Use set_dec to set decrementer to host Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 04/52] KVM: PPC: Book3S HV P9: Use host timer accounting to avoid decrementer read Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 05/52] KVM: PPC: Book3S HV P9: Use large decrementer for HDEC Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 06/52] KVM: PPC: Book3S HV P9: Reduce mftb per guest entry/exit Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 07/52] powerpc/time: add API for KVM to re-arm the host timer/decrementer Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 08/52] KVM: PPC: Book3S HV: POWER10 enable HAIL when running radix guests Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 09/52] powerpc/64s: Keep AMOR SPR a constant ~0 at runtime Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 10/52] KVM: PPC: Book3S HV: Don't always save PMU for guest capable of nesting Nicholas Piggin
2021-10-16 12:38 ` Fabiano Rosas
2021-10-20 5:26 ` Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 11/52] powerpc/64s: Always set PMU control registers to frozen/disabled when not in use Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 12/52] powerpc/64s: Implement PMU override command line option Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 13/52] KVM: PPC: Book3S HV P9: Implement PMU save/restore in C Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 14/52] KVM: PPC: Book3S HV P9: Factor PMU save/load into context switch functions Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 15/52] KVM: PPC: Book3S HV P9: Demand fault PMU SPRs when marked not inuse Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 16/52] KVM: PPC: Book3S HV P9: Factor out yield_count increment Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 17/52] KVM: PPC: Book3S HV: CTRL SPR does not require read-modify-write Nicholas Piggin
2021-10-16 12:54 ` Fabiano Rosas
2021-10-04 16:00 ` [PATCH v3 18/52] KVM: PPC: Book3S HV P9: Move SPRG restore to restore_p9_host_os_sprs Nicholas Piggin
2021-10-16 12:59 ` Fabiano Rosas
2021-10-04 16:00 ` [PATCH v3 19/52] KVM: PPC: Book3S HV P9: Reduce mtmsrd instructions required to save host SPRs Nicholas Piggin
2021-10-16 13:45 ` Fabiano Rosas [this message]
2021-10-20 5:35 ` Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 20/52] KVM: PPC: Book3S HV P9: Improve mtmsrd scheduling by delaying MSR[EE] disable Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 21/52] KVM: PPC: Book3S HV P9: Add kvmppc_stop_thread to match kvmppc_start_thread Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 22/52] KVM: PPC: Book3S HV: Change dec_expires to be relative to guest timebase Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 23/52] KVM: PPC: Book3S HV P9: Move TB updates Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 24/52] KVM: PPC: Book3S HV P9: Optimise timebase reads Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 25/52] KVM: PPC: Book3S HV P9: Avoid SPR scoreboard stalls Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 26/52] KVM: PPC: Book3S HV P9: Only execute mtSPR if the value changed Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 27/52] KVM: PPC: Book3S HV P9: Juggle SPR switching around Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 28/52] KVM: PPC: Book3S HV P9: Move vcpu register save/restore into functions Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 29/52] KVM: PPC: Book3S HV P9: Move host OS save/restore functions to built-in Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 30/52] KVM: PPC: Book3S HV P9: Move nested guest entry into its own function Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 31/52] KVM: PPC: Book3S HV P9: Move remaining SPR and MSR access into low level entry Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 32/52] KVM: PPC: Book3S HV P9: Implement TM fastpath for guest entry/exit Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 33/52] KVM: PPC: Book3S HV P9: Switch PMU to guest as late as possible Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 34/52] KVM: PPC: Book3S HV P9: Restrict DSISR canary workaround to processors that require it Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 35/52] KVM: PPC: Book3S HV P9: More SPR speed improvements Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 36/52] KVM: PPC: Book3S HV P9: Demand fault EBB facility registers Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 37/52] KVM: PPC: Book3S HV P9: Demand fault TM " Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 38/52] KVM: PPC: Book3S HV P9: Use Linux SPR save/restore to manage some host SPRs Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 39/52] KVM: PPC: Book3S HV P9: Comment and fix MMU context switching code Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 40/52] KVM: PPC: Book3S HV P9: Test dawr_enabled() before saving host DAWR SPRs Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 41/52] KVM: PPC: Book3S HV P9: Don't restore PSSCR if not needed Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 42/52] KVM: PPC: Book3S HV P9: Avoid tlbsync sequence on radix guest exit Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 43/52] KVM: PPC: Book3S HV Nested: Avoid extra mftb() in nested entry Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 44/52] KVM: PPC: Book3S HV P9: Improve mfmsr performance on entry Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 45/52] KVM: PPC: Book3S HV P9: Optimise hash guest SLB saving Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 46/52] KVM: PPC: Book3S HV P9: Avoid changing MSR[RI] in entry and exit Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 47/52] KVM: PPC: Book3S HV P9: Add unlikely annotation for !mmu_ready Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 48/52] KVM: PPC: Book3S HV P9: Avoid cpu_in_guest atomics on entry and exit Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 49/52] KVM: PPC: Book3S HV P9: Remove most of the vcore logic Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 50/52] KVM: PPC: Book3S HV P9: Tidy kvmppc_create_dtl_entry Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 51/52] KVM: PPC: Book3S HV P9: Stop using vc->dpdes Nicholas Piggin
2021-10-04 16:00 ` [PATCH v3 52/52] KVM: PPC: Book3S HV P9: Remove subcore HMI handling Nicholas Piggin
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