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Mon, 22 Nov 2021 18:34:59 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C03BEAE066; Mon, 22 Nov 2021 18:34:59 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C2B22AE068; Mon, 22 Nov 2021 18:34:58 +0000 (GMT) Received: from localhost (unknown [9.211.110.220]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTPS; Mon, 22 Nov 2021 18:34:58 +0000 (GMT) From: Fabiano Rosas To: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org Subject: Re: [PATCH v1] KVM: PPC: Book3S HV: Prevent POWER7/8 TLB flush flushing SLB In-Reply-To: <20211119031627.577853-1-npiggin@gmail.com> References: <20211119031627.577853-1-npiggin@gmail.com> Date: Mon, 22 Nov 2021 15:34:56 -0300 Message-ID: <87sfvoqbsf.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 1Op9Dl0c0W1UQvg5q0fTgR3RWRIu8OKH X-Proofpoint-GUID: v5DM3-Aj2cH5uebnfwkj4lz-59aPMVGe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-22_08,2021-11-22_02,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 mlxscore=0 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2111220095 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Nicholas Piggin writes: > The POWER9 ERAT flush instruction is a SLBIA with IH=7, which is a > reserved value on POWER7/8. On POWER8 this invalidates the SLB entries > above index 0, similarly to SLBIA IH=0. > > If the SLB entries are invalidated, and then the guest is bypassed, the > host SLB does not get re-loaded, so the bolted entries above 0 will be > lost. This can result in kernel stack access causing a SLB fault. > > Kernel stack access causing a SLB fault was responsible for the infamous > mega bug (search "Fix SLB reload bug"). Although since commit > 48e7b7695745 ("powerpc/64s/hash: Convert SLB miss handlers to C") that > starts using the kernel stack in the SLB miss handler, it might only > result in an infinite loop of SLB faults. In any case it's a bug. > > Fix this by only executing the instruction on >= POWER9 where IH=7 is > defined not to invalidate the SLB. POWER7/8 don't require this ERAT > flush. > > Fixes: 5008711259201 ("KVM: PPC: Book3S HV: Invalidate ERAT when flushing guest TLB entries") > Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas > --- > arch/powerpc/kvm/book3s_hv_builtin.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c > index fcf4760a3a0e..70b7a8f97153 100644 > --- a/arch/powerpc/kvm/book3s_hv_builtin.c > +++ b/arch/powerpc/kvm/book3s_hv_builtin.c > @@ -695,6 +695,7 @@ static void flush_guest_tlb(struct kvm *kvm) > "r" (0) : "memory"); > } > asm volatile("ptesync": : :"memory"); > + // POWER9 congruence-class TLBIEL leaves ERAT. Flush it now. > asm volatile(PPC_RADIX_INVALIDATE_ERAT_GUEST : : :"memory"); > } else { > for (set = 0; set < kvm->arch.tlb_sets; ++set) { > @@ -705,7 +706,9 @@ static void flush_guest_tlb(struct kvm *kvm) > rb += PPC_BIT(51); /* increment set number */ > } > asm volatile("ptesync": : :"memory"); > - asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT : : :"memory"); > + // POWER9 congruence-class TLBIEL leaves ERAT. Flush it now. > + if (cpu_has_feature(CPU_FTR_ARCH_300)) > + asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT : : :"memory"); > } > }